CN201035055Y - Duct spreading device of LRC tester - Google Patents

Abstract

The utility model discloses a channel extending device for LRC tester, which consists of a logical control unit taking a CPLD chip as center, a clock input unit, an analog switch unit, a channel selection input unit and a channel display unit which are respectively connected with the peripheral interface of the CPLD chip. Compared with the single-channel LRC tester without connecting the channel extending device, the utility model has the beneficial effects that the tester not only maintain the advantages of high measuring accuracy and many testing parameters for LRC tester, but also can achieve the testing function of multi-channel by means of the single-channel LRC tester, that is, the tester can measure the physical parameters for a plurality of capacitors, resistors or inductance components in the system at one time in course of industrial production.

Description

A kind of channel expansion device of LRC tester

Technical field

The utility model relates to LRC tester and measuring technique thereof.

Background technology

The LRC tester is the instrument that is used to measure the respective physical parameter of electric capacity, resistance, inductance element.Compare with multimeter commonly used, LRC tester not only measuring accuracy is higher, and multiple parameter that can measuring sensor, such as impedance, quality factor or the like.Yet, because existing LRC tester only has only a pair of measuring head, therefore, once can only be connected with the two poles of the earth of an element, also promptly once can only measure the parameter of an element.And in industrial processes, many times all need once the physical parameter of a plurality of electric capacity, resistance or inductance element in the system to be measured, change with the parameter of monitoring these elements, thereby judge whether system works is normal.In this case, the existing this LRC tester that once can only measure a component parameters just can't have been satisfied the demand.

The utility model content

The technical problems to be solved in the utility model is, a kind of channel expansion device of the LRC tester of can be once the physical parameter of a plurality of electric capacity, resistance or inductance element in the system being measured is provided.

The technical scheme that solve the technical problem is a kind of like this channel expansion device of LRC tester.The logic control element that it is the center by a CPLD chip, constitute with clock input block, analog switch unit, channel selecting input block and passage display unit that the I/O mouth of this CPLD chip is connected respectively.Wherein, the circuit of clock input block comprises the multivibrator that its output terminal links to each other with the I/O mouth of CPLD chip, and the one end by each pull-up resistor link to each other with the I/O mouth of CPLD chip, the two-way of other end ground connection dials bond switching; The circuit of analog switch unit comprises two identical analog switch chips that COM end separately connects with two measuring heads of LRC tester respectively, this cope and drag pattern intend switch chip each the passage pin of identical numbering is connected the two ends of each detected element, the control end pin that cope and drag pattern is intended switch chip links to each other with the I/O mouth of CPLD chip behind the short circuit respectively; The circuit of channel selecting input block comprises that the negative pole of the I/O mouth of one end and CPLD chip and light emitting diode links to each other, the multichannel of other end ground connection is dialled bond switching, and the quantity that this multichannel is dialled bond switching port number and light emitting diode equates with detected element quantity; The circuit of passage display unit comprises the seven-segment decoder that links to each other with the I/O mouth of this CPLD chip and seven sections LED charactrons that link to each other with this seven-segment decoder.

When once a plurality of elements being tested, at first dial bond switching and select to measure the passage that uses by the multichannel in the channel selecting input block, and a plurality of detected element be insert simultaneously that cope and drag pattern intends switch chip each between the passage pin of identical numbering, the passage pin numbering will to dial the channel number that bond switching selects consistent with multichannel.With the CPLD chip is the logic control element at center, the state that one side is dialled bond switching according to multichannel changes analog switch control pin status successively, thereby gating detected element place passage successively, promptly adopt time division multiplexing mode, in turn the detected element that multichannel is dialled in the selected test channel of bond switching is tested, and test result still shows on the LRC tester; The state of dialling bond switching according to two-way comes the clock that the clock input block produces is carried out frequency division on the other hand, thereby controls each channel measurement time.(test process describes in detail in embodiment again).

Compare with the single pass LRC tester that is not connected this channel expansion device, the beneficial effects of the utility model are, it has not only kept LRC tester measuring accuracy height, the advantage that test parameter is many, but also utilize single pass LRC tester to finish multichannel test function, promptly be used for industrial processes, can once measuring the physical parameter of a plurality of electric capacity, resistance or inductance element in the system.

Below in conjunction with accompanying drawing the utility model is further described.

Description of drawings

Fig. 1 is a system chart of the present utility model

Fig. 2 is circuit theory diagrams of the present utility model

Fig. 3 is the clock input of the I unit amplification among Fig. 2 and the schematic diagram of CPLD chip interface circuit

Fig. 4 is the analog switch of the II unit amplification among Fig. 2 and the schematic diagram of CPLD chip interface circuit

Fig. 5 is the channel selecting input of the III unit amplification among Fig. 2 and the schematic diagram of CPLD chip interface circuit

Fig. 6 is the passage demonstration of the IV unit amplification among Fig. 2 and the schematic diagram of CPLD chip interface circuit

Fig. 7 is the logic function figure of CPLD chip in the utility model

Embodiment

A kind of channel expansion device of LRC tester (with reference to figure 1, Fig. 2).The logic control element that this channel expansion device is the center by a CPLD chip, constitute with clock input block I, analog switch unit II, channel selecting input block III and passage display unit IV that the I/O mouth of this CPLD chip is connected respectively.Wherein, the circuit of clock input block I comprises the multivibrator that its output terminal links to each other with the I/O mouth of CPLD chip, and the one end by each pull-up resistor (R1, R2) link to each other with the I/O mouth of CPLD chip, the two-way of other end ground connection dials bond switching (SW-2); The circuit of analog switch unit II comprises two identical analog switch chips that COM end separately connects with two measuring heads of LRC tester respectively, each passage pin that this cope and drag pattern is intended switch chip to identical numbering be connected each detected element (two ends of DEV1～DEV8), the control end pin that cope and drag pattern is intended switch chip links to each other with the I/O mouth of CPLD chip behind the short circuit respectively; (negative pole of D1～D8) links to each other, the multichannel of other end ground connection is dialled bond switching (SW-8), and this multichannel is dialled bond switching (SW-8) port number and light emitting diode, and ((DEV1～DEV8) quantity equates the quantity of D1～D8) with detected element for the I/O mouth that the circuit of channel selecting input block III comprises one end and CPLD chip and light emitting diode; The circuit of passage display unit IV comprises seven-segment decoder that links to each other with the I/O mouth of this CPLD chip and seven sections LED charactron DPY that link to each other with this seven-segment decoder.

Disclose so far,, needn't just can realize the technical solution of the utility model fully by any performing creative labour to those skilled in the art.So above embodiment also is following each routine summation, the content identical with this summation do not given unnecessary details in following each example.

Embodiment 1 (with reference to figure 1, Fig. 2, Fig. 3):

This example is on the basis of summation part, to clock input block wherein for example.In this example, a TC555 chip is arranged in the multivibrator circuit of clock input block I.The VCC of this TC555 chip end and RESET end all are connected with the power supply of+5V voltage, and its OUT holds and is connected with the I/O mouth of CPLD chip, and its GND holds ground connection.Between the VCC of this TC555 chip end and DISCH end, between THRES end and FRIG end and the DISCH end, have access to each resistance (R3, R4) respectively, at its THRES end and FRIG holds and GND has access to an integrating capacitor C1 between holding; Between its CONT end and GND end, have access to a shunt capacitance C2.The other end of pull-up resistor wherein (R1, R2) is connected with the power supply of+5V voltage.In this example, the value of choose reasonable pull-up resistor (R1, R2) and integrating capacitor C1 makes that multivibrator output clock is that frequency is 1Hz, and dutycycle is 50% square wave.The CPLD chip can be dialled the state of bond switching (SW-2) according to two-way, and the multivibrator output signal is carried out different frequency divisions, thereby controls each channel measurement time.

Embodiment 2 (with reference to figure 1, Fig. 2, Fig. 4):

This example is on the basis of summation part or embodiment 1, to analog switch unit wherein for example.In this example, the analog switch chip is two CD4051 chips.The VCC of this CD4051 chip end and INH hold all with the power supply of+5V voltage and are connected, its corresponding control end (A, B, C pin in these two CD4051 chips) all connects with the corresponding I/O mouth of CPLD chip, the equal ground connection of earth terminal of its VEE end, VSS end and described LCR tester.The mode of described " COM end separately is connected with two measuring heads of LRC tester respectively " is, the COM end of a slice CD4051 chip is connected with a plug-in pin P+ who is connected with the positive pole of LCR tester, and the COM end of another sheet CD4051 chip is connected with a plug-in pin P-who is connected with the negative pole of LCR tester.Because these two CD4051 chips of selecting for use of this example have eight pairs of passage pins, promptly the passage pin (is expanded to eight test channel between the C0～C7), just can insert respectively a detected element (DEV1～DEV8) respectively in these eight test channel at each.According to the analog switch principle, the COM of CD4051 holds each constantly can only (pin is connected among the C0～C7) with eight passage pins, and control end (CD4051 chip A, B, C pin) the pin level of specifically with which passage pin connecting by CD4051 determines, promptly by the corresponding I/O pin decision of CPLD.In order to guarantee the level unification of LCR tester and expansion equipment, the equal ground connection of earth terminal of the VEE end of these two CD4051 chips, VSS end and LCR tester---in this example, be to be connected with the earth terminal of LCR tester by the plug-in pin (LRC_GND) of a ground connection is next.

Embodiment 3 (with reference to figure 1, Fig. 2, Fig. 5):

This example is on the basis of summation part, embodiment 1 or embodiment 2, to channel selecting input block wherein for example.In the circuit of this routine channel selecting input block III, (positive pole of D1～D8) links to each other with the corresponding link of an exclusion PAIZU each light emitting diode respectively, and the COM end of this exclusion PAIZU is connected with the power supply of+5V voltage.Multichannel is dialled bond switching (SW-8) and is used for the use passage that the user selects analog switch CD4051, i.e. test channel.Be in " opening " state as dialling a certain road of bond switching (SW-8) when multichannel, corresponding road light emitting diode is just lighted, and shows that simultaneously the corresponding paths pin of CD4051 is connected to detected element.

Embodiment 4 (with reference to figure 1, Fig. 2, Fig. 6):

This example is on the basis of summation part, embodiment 1, embodiment 2 or embodiment 3, to passage display unit wherein for example.In this example, the seven-segment decoder in the passage display unit IV circuit is the TC4511 chip, and the control end of this seven-segment decoder is connected with the I/O mouth of this CPLD chip, and its vdd terminal, BI end and LT end are connected with the power supply of+5V voltage, and its VSS holds and LE holds ground connection.Show the numeral of output 1～8, being used to indicate the test result that shows on the current time LRC tester is the parameter that is positioned at the element of which passage.

Below, in conjunction with the foregoing description, test process of the present utility model is compared detailed explanation.

Two-way is dialled bond switching (SW-2) by artificial selection, on its pin one, the pin two level can produce 00,01,10,11 4 kind of assembled state, the CPLD chip is dialled these four kinds of states of bond switching (SW-2) according to two-way, the clock of the 1Hz frequency that the TC555 chip is produced carries out 0,2,4,8 four kind of frequency division, is used for the internal work clock.The Measuring Time of each the measured passage the when one-period of work clock, corresponding time division multiplex.For example, it is 01 that two-way is dialled bond switching (SW-2) state, and then the internal work clock is 0.5Hz, and every drive test examination time is two seconds.

According to the detected element quantity and the place passage (for example: needing measurement markers is four elements of DEV1～DEV4) that insert in the test channel, open eight tunnel in the channel selecting input block and (for example dial switch corresponding in the bond switching (SW-8), open and be numbered four switches of 1～4, make it be in " opening " attitude), the two ends of these four switches all are converted to low level, the light emitting diode that is numbered D1～D4 simultaneously will be bright, and (DEV1～DEV4) has been in state to be tested to show four detected element.So the user can dial bond switching (SW-8) by eight the tunnel and select the LRC tester to measure the element of which passage.The CPLD chip is finished two functions according to eight tunnel states of dialling each pin of bond switching (SW-8).One is the correct control signal of control end pin (A, B, C in these two CD4051 chips) output to the CD4051 chip, another is that the numbering of the passage of current selection is passed to seven-segment decoder (TC4511 chip) in the binary-coded decimal mode, its BDC sign indicating number is converted to the demonstration sign indicating number of LED charactron DPY correspondence, thereby finishes the function of display channel numbering.The CPLD chip utilizes the work clock that obtains behind the frequency division, each work clock cycle changes the control signal (CD4051 chip A, B, C pin) of a CD4051 chip and the binary-coded decimal input of TC4511 chip, this is a time division multiplexing mode, be that the work clock one-period shows a test channel numbering, the analog switch passage switches once simultaneously.For example, work clock 0.5Hz, detected element is DEV1～DEV4, then CD4051 chip controls signal is followed successively by 000,001,010,011, and the binary-coded decimal of corresponding TC4511 chip is 0001,0010,0011,0100, and each state duration is two seconds, and constantly repeats.

Obviously, in the utility model, finish said process, need in the CPLD chip, to finish the logic function of each module.In view of writing the scope that corresponding program has exceeded utility model, therefore, only introduce simply.As shown in Figure 7, the CPLD chip is dialled bond switching (SW-2) state according to the two-way in the clock input block, has determined the frequency division value to TC555 chip output clock.In CPLD inside, by counter, can realize division function, produced work clock.The CPLD chip is dialled bond switching (SW-8) state according to eight tunnel in the channel selecting input block, has then determined to measure to select which passage, and these passages are carried out mark with coded system.According to work clock, in each cycle, export a coding of measuring passage, use passage 1 such as this cycle, measure DEV1, then to the BDC sign indicating number 0001 of TC4511 chip output channel number, to CD4051 chip output control coding 000; The next work clock cycle is then exported the corresponding encoded of next passage, and the cycle is reciprocal.

By cooperatively interacting of the utility model and corresponding program, system has finished and has utilized single passage LRC tester, with time division multiplexing mode, measures a plurality of detected element parameter functions simultaneously.The measurement result that the LRC tester shows is exactly the parameter value of the detected element of the channel number correspondence that shows of LED charactron.

Claims (8)

1. the channel expansion device of a LRC tester, it is characterized in that the logic control element that this channel expansion device is the center by a CPLD chip, the clock input block (I) that is connected respectively with the I/O mouth of this CPLD chip, analog switch unit (II), channel selecting input block (III) and passage display unit (IV) constitute; The circuit of described clock input block (I) comprises the multivibrator that its output terminal links to each other with the I/O mouth of CPLD chip, and the one end by each pull-up resistor (R1, R2) link to each other with the I/O mouth of CPLD chip, the two-way of other end ground connection dials bond switching (SW-2); The circuit of described analog switch unit (II) comprises two identical analog switch chips that COM end separately connects with two measuring heads of LRC tester respectively, each passage pin that this cope and drag pattern is intended switch chip to identical numbering be connected each detected element (two ends of DEV1～DEV8), the control end pin that cope and drag pattern is intended switch chip links to each other with the I/O mouth of CPLD chip behind the short circuit respectively; (negative pole of D1～D8) links to each other, the multichannel of other end ground connection is dialled bond switching (SW-8), and this multichannel is dialled bond switching (SW-8) port number and light emitting diode, and ((DEV1～DEV8) quantity equates the quantity of D1～D8) with detected element for the I/O mouth that the circuit of described channel selecting input block (III) comprises one end and CPLD chip and light emitting diode; The circuit of described passage display unit (IV) comprises seven-segment decoder that links to each other with the I/O mouth of this CPLD chip and the seven sections LED charactrons (DPY) that link to each other with this seven-segment decoder.

2. according to the channel expansion device of the described LRC tester of claim 1, it is characterized in that a TC555 chip is arranged in the multivibrator circuit of described clock input block (I); The VCC of this TC555 chip end and RESET end all are connected with the power supply of+5V voltage, and its OUT holds and is connected with the I/O mouth of described CPLD chip, and its GND holds ground connection; Between the VCC of this TC555 chip end and DISCH end, between THRES end and FRIG end and the DISCH end, have access to each resistance (R3, R4) respectively, at its THRES end and FRIG holds and GND has access to an integrating capacitor (C1) between holding; Between its CONT end and GND end, have access to a shunt capacitance (C2); The other end of described pull-up resistor (R1, R2) is connected with the power supply of+5V voltage.

3. according to the channel expansion device of claim 1 or 2 described LRC testers, it is characterized in that, described analog switch chip is two CD4051 chips, the VCC of this CD4051 chip end and INH hold all with the power supply of+5V voltage and are connected, its corresponding control end all connects with the corresponding I/O mouth of described CPLD chip, the equal ground connection of earth terminal of its VEE end, VSS end and described LCR tester.

4. according to the channel expansion device of claim 1 or 2 described LRC testers, it is characterized in that, in the circuit of described channel selecting input block (III), (positive pole of D1～D8) links to each other with the corresponding link of an exclusion (PAIZU) each light emitting diode respectively, and the COM end of this exclusion (PAIZU) is connected with the power supply of+5V voltage.

5. according to the channel expansion device of claim 1 or 2 described LRC testers, it is characterized in that, seven-segment decoder in described passage display unit (IV) circuit is the TC4511 chip, and the control end of this seven-segment decoder is connected with the I/O mouth of this CPLD chip, its vdd terminal,

The end and

End is connected with the power supply of+5V voltage, and its VSS holds and LE holds ground connection.

6. according to the channel expansion device of the described LRC tester of claim 3, it is characterized in that, in the circuit of described channel selecting input block (III), (positive pole of D1～D8) links to each other with the corresponding link of an exclusion (PAIZU) each light emitting diode respectively, and the COM end of this exclusion (PAIZU) is connected with the power supply of+5V voltage.

7. according to the channel expansion device of the described LRC tester of claim 3, it is characterized in that the seven-segment decoder in described passage display unit (IV) circuit is the TC4511 chip, the control end of this seven-segment decoder is connected with the I/O mouth of this GPLD chip, its vdd terminal,

The end and

End is connected with the power supply of+5V voltage, and its VSS holds and LE holds ground connection.

8. according to the channel expansion device of the described LRC tester of claim 4, it is characterized in that the seven-segment decoder in described passage display unit (IV) circuit is the TC4511 chip, the control end of this seven-segment decoder is connected with the I/O mouth of this CPLD chip, its vdd terminal,

The end and

End is connected with the power supply of+5V voltage, and its VSS holds and LE holds ground connection.

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