CN201035055Y - A channel expansion device of LRC tester - Google Patents

Abstract

A channel expansion device of an LRC tester. The channel expansion device is composed of a logic control unit centered on a CPLD chip, a clock input unit connected to the peripheral interface of the CPLD chip, an analog switch unit, a channel selection input unit and a channel display unit. Compared with the single-channel LRC tester that is not connected with the channel expansion device, the utility model has the beneficial effect that it not only maintains the advantages of high measurement accuracy and many test parameters of the LRC tester, but also utilizes the single-channel LRC tester The instrument can complete the multi-channel test function, that is, in the process of industrial production, it can measure the physical parameters of multiple capacitance, resistance or inductance components in the system at one time.

Description

A channel expansion device of LRC tester

technical field

The utility model relates to an LRC tester and its measurement technology.

Background technique

The LRC tester is an instrument used to measure the corresponding physical parameters of capacitance, resistance, and inductance components. Compared with commonly used multimeters, LRC testers not only have higher measurement accuracy, but also can measure various parameters of components, such as impedance, quality factor and so on. However, since the existing LRC tester has only one pair of test heads, it can only be connected to the two poles of one component at a time, that is, only one component's parameters can be measured at a time. In the industrial production process, it is often necessary to measure the physical parameters of multiple capacitors, resistors or inductance components in the system at one time, so as to monitor the parameter changes of these components, so as to judge whether the system is working normally. In this case, the existing LRC tester that can only measure one component parameter at a time cannot meet the needs.

Utility model content

The technical problem to be solved by the utility model is to provide a channel expansion device of an LRC tester capable of measuring the physical parameters of multiple capacitors, resistors or inductance elements in the system at one time.

The technical solution for solving the technical problem is such a channel expansion device of the LRC tester. It consists of a logic control unit centered on a CPLD chip, a clock input unit connected to the I/O port of the CPLD chip, an analog switch unit, a channel selection input unit and a channel display unit. Wherein, the circuit of the clock input unit includes a multivibrator whose output end is connected to the I/O port of the CPLD chip, and two multivibrators whose one end is connected to the I/O port of the CPLD chip through a pull-up resistor and the other end is grounded. Road dial key switch; the circuit of the analog switch unit includes two identical analog switch chips whose COM terminals are respectively connected to the two test heads of the LRC tester, and each pair of the same numbered channel pins of the two analog switch chips Connected to both ends of each tested component, the control terminal pins of the two analog switch chips are respectively short-circuited and connected to the I/O port of the CPLD chip; the circuit of the channel selection input unit includes one end and the I/O port of the CPLD chip The port is connected to the negative pole of the light-emitting diode, and the other end is grounded multi-way dial key switch. The number of channels of the multi-way dial key switch and the number of light-emitting diodes are equal to the number of tested elements; the circuit of the channel display unit includes the I of the CPLD chip. The seven-segment decoder connected to the /O port and the seven-segment LED digital tube connected to the seven-segment decoder.

When testing multiple components at one time, the channel used for measurement is first selected by the multi-way dial switch in the channel selection input unit, and multiple tested components are connected to two analog switch chips at the same time, each pair of the same number Between the channel pins, the channel pin number should be consistent with the channel number selected by the multi-way dial switch. The logic control unit centered on the CPLD chip, on the one hand, changes the state of the analog switch control pins sequentially according to the state of the multi-way dial switch, so as to sequentially select the channel where the component under test is located, that is, adopts the time division multiplexing method to sequentially control multiple channels. The component under test in the test channel selected by the two-way dial switch is tested, and the test result is still displayed on the LRC tester; on the other hand, the frequency of the clock generated by the clock input unit is divided according to the state of the two-way dial switch. Thereby controlling the measurement time of each channel. (the test process is described in detail again in the specific embodiment).

Compared with the single-channel LRC tester that is not connected with the channel expansion device, the utility model has the beneficial effect that it not only maintains the advantages of high measurement accuracy and many test parameters of the LRC tester, but also utilizes the single-channel LRC tester The instrument can complete the multi-channel test function, that is, in the process of industrial production, it can measure the physical parameters of multiple capacitance, resistance or inductance components in the system at one time.

Below in conjunction with accompanying drawing, the utility model is further described.

Description of drawings

Fig. 1 is a system block diagram of the utility model

Fig. 2 is the schematic circuit diagram of the utility model

Fig. 3 is the schematic diagram of the clock input and CPLD chip interface circuit amplified by the I unit in Fig. 2

Fig. 4 is the schematic diagram of the analog switch and CPLD chip interface circuit amplified by II unit in Fig. 2

Fig. 5 is the schematic diagram of the channel selection input and CPLD chip interface circuit amplified by III unit in Fig. 2

Fig. 6 is the schematic diagram of the enlarged channel display and CPLD chip interface circuit of the IV unit in Fig. 2

Fig. 7 is the logic function figure of CPLD chip in the utility model

Detailed ways

A channel expansion device of an LRC tester (refer to Fig. 1 and Fig. 2). The channel expansion device is composed of a logic control unit centered on a CPLD chip, a clock input unit I connected to the I/O port of the CPLD chip, an analog switch unit II, a channel selection input unit III and a channel display unit IV. Wherein, the circuit of the clock input unit 1 includes a multivibrator whose output terminal is connected to the I/O port of the CPLD chip, and one end thereof is connected to the I/O port of the CPLD chip by each pull-up resistor (R1, R2) , the two-way dial key switch (SW-2) whose other end is grounded; the circuit of the analog switch unit II includes two identical analog switch chips whose COM ends are respectively connected to the two test heads of the LRC tester. Each pair of channel pins with the same number on the analog switch chip is connected to both ends of each tested component (DEV1~DEV8), and the control terminal pins of the two analog switch chips are shorted and connected to the I/O port of the CPLD chip. The circuit of the channel selection input unit III includes one end of which is connected to the negative pole of the I/O port of the CPLD chip and the light-emitting diode (D1～D8), and a multi-way dial switch (SW-8) whose other end is grounded. The number of channels of the key switch (SW-8) and the number of light-emitting diodes (D1-D8) are equal to the number of the measured components (DEV1-DEV8); the circuit of the channel display unit IV includes seven circuits connected to the I/O port of the CPLD chip. A segment decoder and a seven-segment LED digital tube DPY connected to the seven-segment decoder.

So far, those skilled in the art can fully realize the technical solutions of the present invention without any creative efforts. Therefore, the above specific implementation manners are also general descriptions of the following examples, and the content that is the same as this general description in the following examples will not be repeated.

Embodiment 1 (with reference to Fig. 1, Fig. 2, Fig. 3):

This example is an example of the clock input unit based on the general introduction. In this example, there is a TC555 chip in the multivibrator circuit of the clock input unit I. Both the VCC end and the RESET end of the TC555 chip are connected to a +5V power supply, the OUT end is connected to the I/O port of the CPLD chip, and the GND end is grounded. A resistor (R3, R4) is connected between the VCC terminal and DISCH terminal, THRES terminal, FRIG terminal and DISCH terminal of the TC555 chip, and a resistor (R3, R4) is connected between the THRES terminal, FRIG terminal and GND terminal. An integral capacitor C1; a bypass capacitor C2 is connected between its CONT terminal and GND terminal. The other end of the pull-up resistors (R1, R2) is connected to the +5V power supply. In this example, the values of the pull-up resistors (R1, R2) and the integrating capacitor C1 are reasonably selected so that the output clock of the multivibrator is a square wave with a frequency of 1 Hz and a duty cycle of 50%. The CPLD chip can perform different frequency divisions on the output signal of the multivibrator according to the state of the two-way dial switch (SW-2), thereby controlling the measurement time of each channel.

Embodiment 2 (with reference to Fig. 1, Fig. 2, Fig. 4):

This example is an example of an analog switch unit based on the general description or the first embodiment. In this example, the analog switch chips are two CD4051 chips. Both the VCC terminal and the INH terminal of the CD4051 chip are connected to the +5V voltage power supply, and the corresponding control terminals (A, B, and C pins in the two CD4051 chips) are connected to the corresponding I/O ports of the CPLD chip. Its VEE terminal, VSS terminal and the ground terminal of the LCR tester are all grounded. The method of "connecting the respective COM ends to the two test heads of the LRC tester" is that the COM end of one CD4051 chip is connected to a pin P+ connected to the positive pole of the LCR tester, and the COM end of the other CD4051 chip is connected to the positive pole of the LCR tester. There is a pin P- connected to the negative pole of the LCR tester. Since the two CD4051 chips used in this example have a total of eight pairs of channel pins, that is, each pair of channel pins (C0~C7) is expanded into eight test channels, and these eight test channels can be respectively connected to Each one DUT (DEV1～DEV8). According to the principle of analog switch, the COM terminal of CD4051 can only be connected to one of the eight channel pins (C0~C7) at each moment, and the specific channel pin is connected to by the control terminal of CD4051 (CD4051 chip A , B, C pins) the level of the pin is determined by the corresponding I/O pin of the CPLD. In order to ensure that the level of the LCR tester and the expansion device are uniform, the VEE and VSS terminals of the two CD4051 chips and the ground terminal of the LCR tester are all grounded—in this example, through a grounding pin (LRC_GND) to be connected to the ground terminal of the LCR tester.

Embodiment 3 (with reference to Fig. 1, Fig. 2, Fig. 5):

This example is an example of the channel selection input unit based on the general introduction, embodiment 1 or embodiment 2. In the circuit of the channel selection input unit III in this example, the anodes of each light-emitting diode (D1~D8) are respectively connected to the corresponding connection terminal of an exclusion PAIZU, and the COM terminal of the exclusion PAIZU is connected to a +5V power supply . The multi-way dial switch (SW-8) is used for the user to select the use channel of the analog switch CD4051, that is, the test channel. For example, when one channel of the multi-channel dial switch (SW-8) is in the "on" state, the corresponding LED will light up, and at the same time it indicates that the channel pin of the corresponding channel of CD4051 is connected to the component under test.

Embodiment 4 (with reference to Fig. 1, Fig. 2, Fig. 6):

This example is an example of the channel display unit on the basis of the general description, embodiment 1, embodiment 2 or embodiment 3. In this example, the seven-segment decoder in the IV circuit of the channel display unit is a TC4511 chip, and the control terminal of the seven-segment decoder is connected to the I/O port of the CPLD chip, and its VDD terminal, BI terminal and LT terminal It is connected to the power supply of +5V voltage, and its VSS terminal and LE terminal are grounded. The numbers of display output 1 to 8 are used to indicate the parameter of the component in which channel the test result displayed on the LRC tester at the current moment is.

Next, in combination with the above-mentioned embodiments, the testing process of the present utility model will be described in detail.

The two-way dial switch (SW-2) can be manually selected, and the levels on pin 1 and pin 2 can produce four combination states of 00, 01, 10, and 11. The CPLD chip uses the two-way dial switch (SW-2) 2) In these four states, the 1Hz frequency clock generated by the TC555 chip is divided into four types: 0, 2, 4, and 8, which are used for the internal working clock. One cycle of the working clock corresponds to the measurement time of each measured channel in time division multiplexing. For example, if the status of the two dial switches (SW-2) is 01, the internal working clock is 0.5Hz, and the test time for each channel is two seconds.

According to the number of components under test connected to the test channel and the channel (for example: four components marked DEV1~DEV4 need to be measured), turn on the corresponding switch in the eight-way toggle switch (SW-8) in the channel selection input unit (For example, turn on the four switches numbered 1 to 4 to make them in the "on" state), the two ends of these four switches are converted to low level, and the light-emitting diodes numbered D1 to D4 will be on at the same time, To show that there are four DUTs (DEV1~DEV4) already in the state to be tested. Therefore, the user can select the components of which channels the LRC tester will measure through the eight-way dial switch (SW-8). The CPLD chip completes two functions according to the state of each pin of the eight-way dial switch (SW-8). One is to output the correct control signal to the control terminal pins of the CD4051 chip (A, B, C in the two CD4051 chips), and the other is to pass the number of the currently selected channel to the seven-segment decoder in BCD code (TC4511 chip), which converts the BDC code into the display code corresponding to the LED digital tube DPY, thereby completing the function of displaying the channel number. The CPLD chip uses the working clock obtained after frequency division, and changes the control signal of the CD4051 chip (CD4051 chip A, B, C pins) and the BCD code input of the TC4511 chip once every working clock cycle. This is a time division multiplexing method, that is One cycle of the working clock displays a test channel number, and at the same time, the analog switch channel is switched once. For example, if the working clock is 0.5Hz, and the components under test are DEV1~DEV4, then the control signals of the CD4051 chip are 000, 001, 010, 011 in turn, and the BCD codes corresponding to the TC4511 chip are 0001, 0010, 0011, 0100, and each state lasts The time is two seconds and it repeats continuously.

Obviously, to complete the above process in the utility model, it is necessary to complete the logic functions of each module in the CPLD chip. Since it is beyond the scope of the utility model to write the corresponding program, it is only briefly introduced. As shown in Figure 7, the CPLD chip determines the frequency division value of the output clock of the TC555 chip according to the state of the two-way dial switch (SW-2) in the clock input unit. Inside the CPLD, through the counter, the frequency division function can be realized, and the working clock is generated. The CPLD chip determines which channels are selected for measurement according to the state of the eight-way dial switch (SW-8) in the channel selection input unit, and marks these channels in a coded manner. According to the working clock, in each cycle, output the code of a measurement channel. For example, if channel 1 is used to measure DEV1 in this cycle, the BDC code 0001 of the channel number will be output to the TC4511 chip, and the control code 000 will be output to the CD4051 chip; and the next The working clock cycle outputs the corresponding code of the next channel, and the cycle repeats.

Through the mutual cooperation of the utility model and the corresponding program, the system realizes the function of simultaneously measuring the parameters of multiple tested components by using a single channel LRC tester in a time-division multiplexing manner. The measurement result displayed by the LRC tester is the parameter value of the component under test corresponding to the channel number displayed by the LED digital tube.

Claims (8)

1. a kind of channel expansion device of LRC tester, it is characterized in that, this channel expansion device is the logic control unit of the center by a CPLD chip, the clock input unit (1) that is connected respectively with the I/O mouth of this CPLD chip, An analog switch unit (II), a channel selection input unit (III) and a channel display unit (IV) are formed; the circuit of the clock input unit (I) includes a multivibrator whose output is connected to the I/O port of the CPLD chip device, and one end thereof is connected to the I/O port of the CPLD chip by each pull-up resistor (R1, R2), and the two-way dial key switch (SW-2) that the other end is grounded; the analog switch unit (II) The circuit includes two identical analog switch chips whose COM terminals are respectively connected to the two test heads of the LRC tester. Each pair of channel pins with the same number of the two analog switch chips are connected to each DUT (DEV1～ DEV8) two ends, the control terminal pin of two analog switch chips is connected with the I/O port of CPLD chip after being shorted respectively; The circuit of described channel selection input unit (III) comprises its one end and the I/O of CPLD chip The multi-way dial switch (SW-8) whose O port is connected to the negative pole of the light-emitting diode (D1～D8) and the other end is grounded. The quantity is equal to the number of tested components (DEV1～DEV8); the circuit of the channel display unit (IV) includes a seven-segment decoder connected with the I/O port of the CPLD chip and connected with the seven-segment decoder The seven-segment LED digital tube (DPY). 2. according to the channel expansion device of the described LRC tester of claim 1, it is characterized in that, a TC555 chip is arranged in the multivibrator circuit of described clock input unit (1); The VCC end of this TC555 chip and the RESET end all It is connected to the power supply of +5V voltage, its OUT terminal is connected to the I/O port of the CPLD chip, and its GND terminal is grounded; between the VCC terminal and the DISCH terminal of the TC555 chip, between the THRES terminal and the FRIG terminal and the DISCH terminal There is a resistor (R3, R4) connected between them, an integrating capacitor (C1) is connected between the THRES terminal and the FRIG terminal and the GND terminal; a bypass capacitor is connected between the CONT terminal and the GND terminal (C2); the other end of the pull-up resistors (R1, R2) is connected to a +5V power supply. 3. according to the channel expansion device of the described LRC tester of claim 1 or 2, it is characterized in that, described analog switch chip is two CD4051 chips, and the VCC end and INH end of this CD4051 chip are all connected with the power supply of +5V voltage , its corresponding control terminals are all connected with the corresponding I/O ports of the CPLD chip, and its VEE terminal, VSS terminal and the ground terminal of the LCR tester are all grounded. 4. according to the channel extension device of the described LRC tester of claim 1 or 2, it is characterized in that, in the circuit of described channel selection input unit (III), the anodes of each light emitting diode (D1～D8) are respectively connected with one The corresponding connection terminals of the exclusion (PAIZU) are connected, and the COM terminal of the exclusion (PAIZU) is connected to the power supply of +5V voltage. 5. according to the channel extension device of the described LRC tester of claim 1 or 2, it is characterized in that, the seven-segment decoder in the channel display unit (IV) circuit is a TC4511 chip, and the control of the seven-segment decoder The terminal is connected to the I/O port of the CPLD chip, and its VDD terminal,

End and

The terminal is connected to the power supply of +5V voltage, and its VSS terminal and LE terminal are grounded. 6. according to the channel extension device of the described LRC tester of claim 3, it is characterized in that, in the circuit of described channel selection input unit (III), the anodes of each light-emitting diode (D1～D8) are respectively connected with a resistance (PAIZU) is connected to the corresponding connection terminal, and the COM terminal of the exclusion (PAIZU) is connected to the power supply of +5V voltage. 7. according to the channel extension device of the said LRC tester of claim 3, it is characterized in that, the seven-segment decoder in the said channel display unit (Ⅳ) circuit is a TC4511 chip, and the control terminal of this seven-segment decoder is connected with The I/O port of the GPLD chip is connected, its VDD terminal,

End and

The terminal is connected to the power supply of +5V voltage, and its VSS terminal and LE terminal are grounded. 8. according to the channel extension device of the described LRC tester of claim 4, it is characterized in that, the seven-segment decoder in the channel display unit (IV) circuit is a TC4511 chip, and the control terminal of this seven-segment decoder is connected with The I/O port of the CPLD chip is connected, its VDD terminal,

End and

The terminal is connected to the power supply of +5V voltage, and its VSS terminal and LE terminal are grounded.

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