CN112802754A - Isolation gate trench type MOSFET device and manufacturing method thereof - Google Patents
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention relates to an isolation gate groove type MOSFET device and a manufacturing method thereof.A wet etching oxide layer is adopted, and a gate electrode, a polysilicon electrode at the bottom of a groove and an intermediate oxide layer which meet the design requirement can be well produced; the gate leakage capacitance can be greatly reduced through the polysilicon electrode at the bottom of the groove below the gate electrode; when a reverse bias is applied to the drain terminal, the polysilicon electrode is grounded together with the source terminal through the layout design, so that a stronger electric field can be formed, the transverse depletion effect is further enhanced, and the on-resistance is further reduced.
Description
Technical Field
The invention relates to an isolation gate trench type MOSFET device and a manufacturing method thereof, belonging to the technical field of semiconductors.
Background
With the continuous development of semiconductor technology, the chip size is smaller and smaller, and the operating voltage is also reduced, so that the requirements on power management, particularly the low-voltage direct current-direct current buck conversion efficiency, are higher and higher, and thus, a high-efficiency small-volume switch mode power supply is produced at the same time. For example, in the fields of PC and notebook computer, applications in the fields of electric vehicle, hybrid electric vehicle (new energy vehicle), fast charging, wireless charging, etc. are also rapidly emerging, and almost all of these fields use the power MOSFET device, and the trench MOSFET is an important member of this large family.
As is well known, the ideal on-resistance of a common trench MOSFET device is four times the square of the breakdown voltage, and meanwhile, when the device is applied at high frequency, the switching loss of the common trench MOSFET device is also large, and the characteristics of the common power trench MOSFET device are continuously close to the limit of a silicon material at present; if the on-resistance is to be further reduced, on the one hand, semiconductor materials with higher electron mobility or wider forbidden band width, such as GaAs, SiC, can be used. However, based on the current silicon substrate process, the transfer to GaAs or SiC faces the difficult challenges of various processes, and the wafer price of such GaAs or SiC is much higher than that of the silicon wafer. Therefore, how to further improve the on-resistance and the gate-drain capacitance by optimizing the structure on the basis of the current common trench MOSFET process based on a silicon wafer is an important research.
Compared with the common trench MOSFET, the manufacturing process of the isolation gate trench MOSFET is more complex, the process stability is more strictly controlled, and in the prior art, when an oxide layer between a gate electrode above a trench and a polycrystalline silicon electrode at the bottom of the trench is manufactured, the phenomena of sharp corners (shown in figure 1) and side hooks (shown in figure 11) of a middle oxide layer are easily caused, so that the gate source reverse leakage failure is caused.
Disclosure of Invention
The invention provides an isolated gate groove type MOSFET device and a manufacturing method thereof, aiming at solving the problems in the prior art, and adopting a wet etching oxide layer to well produce a gate electrode meeting the design requirements, a polysilicon electrode at the bottom of a groove and an intermediate oxide layer; the gate leakage capacitance can be greatly reduced through the polysilicon electrode at the bottom of the groove below the gate electrode; when a reverse bias is applied to the drain terminal, the polysilicon electrode is grounded together with the source terminal through the layout design, so that a stronger electric field can be formed, the transverse depletion effect is further enhanced, and the on-resistance is further reduced.
The technical solution of the invention is as follows: a manufacturing method of an isolation gate trench type MOSFET device comprises the following process steps:
s1: providing a substrate wafer, and growing an epitaxial layer on the substrate;
s2, growing a layer of SIN layer and SiO on the epitaxial layer by thermal furnace tube process and PECVD2The hard film layer is used for defining a Cell area, a polycrystalline silicon isolation gate connecting area at the bottom of the groove and a control gate connecting area through photoetching through layout design, etching the hard film, and performing deep groove etching on silicon by taking the hard film as a mask layer after removing a light resistor to form a groove 1, a groove 2 and a groove 3;
s3: etching the SIN layer by a wet method, and then removing the hard film oxide layer to enable the SIN at the opening of the groove to retract inwards, so that the CD at the opening of the groove is larger than the CD in the groove;
s4, growing oxide film by thermal oxidation furnace tube process to cover the surface, the side wall and the bottom of the groove;
s5: filling polycrystalline silicon, filling the whole groove without a cavity, and carrying out CMP grinding on the surface of the polycrystalline silicon to flatten the surface of the polycrystalline silicon;
s6, etching the polysilicon for the first time to be flush with the silicon surface, and then shielding the part of the region where the isolation gate is connected out by photoetching photoresist;
s7: etching the polycrystalline silicon for the second time to the inside of the groove, and reserving the length of the control grid for adjusting the length of the channel on the upper part of the groove;
s8, using the residual polysilicon as a mask to etch the thick oxide layer by a whole surface wet method, removing the redundant thick oxide layer on the surface of the groove and the upper wall end, adopting an over-etching mode, namely etching the thick oxide layer until the upper surface of the thick oxide layer is flush with the upper surface of the residual polysilicon, continuing etching the thick oxide layer, finally enabling the upper surface of the thick oxide layer in the cell area and the control gate connecting area to be slightly lower than the surface of the polysilicon at the bottom of the groove, and removing the light resistance;
s9, filling the insulating oxide layer between the gate electrode above the groove and the polysilicon electrode at the bottom of the groove, wherein HDPCVD is used during filling, and then SACVD is used for filling the insulating oxide layer above the groove;
s10, flattening the CMP surface, and removing the SiN layer on the silicon surface by a wet method;
s11: annealing the insulating isolation oxide layer under N2Environment 1100 deg.c/30 min;
s12, in order to avoid the side hook phenomenon, removing the residual oxide layer on the surface of the master in advance, and completely removing the oxide film with the residual thickness on the surface by adopting LHF solution;
s13, photoetching photoresistance to shield the isolation gate connected region, and designing PR to cover the silicon surface with a width 3 times larger than the wet etching depth of the insulating isolation oxide layer in order to avoid the side hook phenomenon;
s14, wet etching the insulating isolation oxide layer with a reserved thickness greater than 2500A, eliminating side hook phenomenon by removing surface oxide and controlling the width of the photoresist shielding isolation gate connection area, and eliminating surface sharp corner bulge phenomenon by dry etching;
s15: after removing the photoresistance, forming a gate oxide layer on the side wall of the groove;
s16: filling polycrystalline silicon into the groove to form a polycrystalline silicon gate layer, making the gate polycrystalline silicon interface slightly lower than the silicon surface through back etching, forming a body region through ion implantation, performing source region ion implantation through photoetching, and respectively advancing;
s17: depositing an oxide layer to form an insulating dielectric layer, etching holes and filling metal to respectively form a source metal layer, an isolation gate connection metal layer, a control gate connection metal layer and a back metal to form a drain metal layer.
Preferably, in S9, the thickness of the filled insulating oxide layer depends on the distance between the surface of the polysilicon at the bottom of the trench and the silicon surface, and the one-step filling or the multi-step filling is performed according to the filling thickness when HDPCVD is used, or the multi-step filling is performed if the thickness is greater than 20K.
Preferably, in S12, the ratio of hydrofluoric acid to water in the LHF solution is 1: 50.
An isolation gate trench type MOSFET device is manufactured by a manufacturing method of the isolation gate trench type MOSFET device.
The invention has the advantages that: the structure and the manufacturing process are reasonable in design, and the phenomenon of side hook of an isolation gate connection region and the phenomenon of sharp corner bulge of an isolation oxide layer between a gate electrode above the groove and a polycrystalline silicon electrode at the bottom of the groove can be eliminated; parasitic capacitance among a grid, a source and a drain which can prevent the device from working at high speed can be greatly reduced, and an offset region of an isolation grid MOSFET tube has higher doping concentration and can also effectively reduce on-resistance.
Drawings
Figure 1 is a prior art schematic illustration of the appearance of inter-oxide taper angles in the fabrication of an oxide layer between a gate electrode above a trench and a polysilicon electrode at the bottom of the trench.
Fig. 2 is a schematic diagram of step S2 of the method for manufacturing the isolation gate trench MOSFET device according to the present invention.
Fig. 3 is a schematic diagram of step S3 of the method for manufacturing the isolation gate trench MOSFET device according to the present invention.
Fig. 4 is a schematic diagram of step S4 of the method for manufacturing the isolation gate trench MOSFET device according to the present invention.
Fig. 5 is a schematic diagram of step S5 of the method for manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 6 is a schematic diagram of step S6 of the method for manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 7 is a schematic diagram of step S7 of the method for manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 8 is a schematic diagram of step S8 of the method of manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 9 is a schematic diagram of step S9 of the method for manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 10 is a schematic diagram of step S10 of the method for manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 11 is a schematic diagram illustrating a side hook phenomenon occurring when an oxide layer between a gate electrode above a trench and a polysilicon electrode at the bottom of the trench is fabricated according to the related art.
Fig. 12 is a schematic diagram of step S14 of the method of manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 13 is a schematic diagram of the step S15 of the method for manufacturing the isolation gate trench MOSFET device of the present invention.
Fig. 14 is a schematic diagram of step S16 of the method of manufacturing an isolation gate trench MOSFET device according to the present invention.
Fig. 15 is a schematic diagram of step S17 of the method of manufacturing an isolation gate trench MOSFET device according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and specific embodiments.
A manufacturing method of an isolation gate trench type MOSFET device comprises the following process steps:
s1: providing a substrate wafer (Sub) on which an epitaxial layer (drift region) with a certain thickness and a certain resistivity is grown according to the product voltage and on-resistance requirements, wherein when the epitaxial layer, i.e. diffusion region, is usually uniformly doped, the electric field distribution in the drift region has certain non-uniformity which is not obvious under the low voltage of 40V, if the medium-high voltage is 60V-200V, because of enough voltage resistance, the thickness of the epitaxial layer, i.e. the distance of the drift region, will also be relatively thick, in which case if the epitaxial layer is also uniformly doped, the electric field distribution will vary exponentially along the longer distance from the source to the drain, and a decrease in the electric field strength will cause a decrease in the charge balance, i.e. a decrease in the on-resistance, the electric field distribution in medium and high voltage applications can be effectively improved if the graded epitaxial doping is used. So that the appropriate epitaxial layer needs to be selected for different voltages.
S2, growing a layer of SIN layer and SiO on the epitaxial layer by thermal furnace tube process and PECVD2A hard film layer (hardmask), defining a Cell area, a polysilicon isolation gate connecting area at the bottom of the groove and a control gate connecting area by photoetching through a layout design, etching the hard film, removing a light resistance, and then performing silicon deep groove etching by taking the hard film as a mask layer to form a groove 1, a groove 2 and a groove 3 as shown in figure 2;
s3: as shown in fig. 3, the SIN layer is wet etched, and then the hard film oxide layer is removed, so that the SIN at the opening of the trench is inwardly shrunk to form a CD at the opening of the trench larger than a CD inside the trench, thereby avoiding formation of a cavity by subsequent polysilicon filling;
s4, as shown in FIG. 4, growing an oxide film by a thermal oxidation furnace process to cover the surface, the side wall and the bottom of the trench, wherein the thickness of the oxide film is determined according to the designed withstand voltage;
s5: as shown in fig. 5, polysilicon filling is required to fill the entire trench without voids; carrying out CMP grinding on the surface of the polycrystalline silicon to flatten the surface of the polycrystalline silicon;
s6, as shown in FIG. 6, etching the polysilicon for the first time, wherein the etching is level with the silicon surface; then, shielding the part of the region connected with the isolation gate by photoetching light resistance;
s7: as shown in fig. 7, the polysilicon is etched for the second time to the inside of the trench, the depth depends on the length requirement of the charge balance region below, and a certain length needs to be reserved on the upper portion of the trench for the control gate to adjust the length of the channel;
s8, as shown in figure 8, using the residual polysilicon as a mask to etch the thick oxide layer by a wet method to remove the redundant thick oxide layer on the surface and the upper wall end of the trench, etching the thick oxide layer by adopting an over-etching mode and controlling the over-etching amount of the thick oxide layer by etching time, wherein the over-etching is to etch the thick oxide layer until the upper surface of the thick oxide layer is flush with the upper surface of the residual polysilicon, and then continuing to etch the thick oxide layer, finally making the upper surface of the thick oxide layer in the cell region and the control gate connecting region slightly lower than the polysilicon surface at the bottom of the trench, and removing the light resistance;
and S9, as shown in FIG. 9, filling the insulating oxide layer between the gate electrode above the trench and the polysilicon electrode at the bottom of the trench, wherein the thickness of the filled insulating oxide layer depends on the distance between the polysilicon surface at the bottom of the trench and the silicon surface, the filling method is to use HDPCVD, determine one-step filling or multi-step filling according to the filling thickness, find that the effect of adopting the multi-step filling method is better when the thickness is more than 20K according to multiple grouping experiments, and then use SACVD to fill the insulating oxide layer above. This patent uses HDPCVD + SACVD method to fill insulating oxide layer, and HDPCVD is the method of synchronous deposition and sculpture, can avoid along with the condition that filling time slot opening part CD can reduce, can effectually avoid producing in the insulating isolation layer in bottom that forms have the cavity, avoids the condition of gate electrode and isolation polysilicon electrode short circuit.
S10, as shown in FIG. 10, the CMP surface is flattened, and the SiN layer on the silicon surface is removed by a wet method;
s11: annealing the insulating isolation oxide layer to make the film layer more compact, wherein the annealing condition is N2Environment 1100 deg.c/30 min;
s12, because the insulating isolation oxide layer behind the patent is a wet etching method, the insulating isolation oxide layer has isotropic etching characteristic, in order to avoid side hook phenomenon (as shown in figure 11), the residual oxide layer on the surface of the master needs to be removed completely in advance, LHF solution (hydrofluoric acid to water ratio is 1:50) is used in the patent, the speed of the etching solution is stable, and the oxide film with residual thickness on the surface can be completely removed.
S13, photoetching a light resistance to shield the isolation gate connecting region, wherein the insulation isolation oxide layer behind the device is a wet etching method which has isotropic etching characteristic, so that in order to avoid side hook phenomenon (as shown in figure 11), the width of PR covering the silicon surface needs to be designed to be 3 times larger than the wet etching depth of the insulation isolation oxide layer;
s14, as shown in FIG. 12, wet etching the insulating isolation oxide layer with a reserved thickness greater than 2500A, wherein the side hook phenomenon can be eliminated by removing the surface oxide and controlling the width of the region where the photoresist shields the isolation gate, and the surface sharp corner protrusion phenomenon can be eliminated by the wet etching;
s15: as shown in fig. 13, after removing the photoresist, as in the conventional MOSFET process, a gate oxide layer is formed on the sidewall of the trench, the thickness of which depends on the withstand voltage and the threshold voltage;
s16: as shown in fig. 14, as in the conventional MOSFET process, the trench is filled with polysilicon to form a polysilicon gate layer, and the gate polysilicon interface is slightly lower than the silicon surface by etching back; ion implantation is carried out to form a body region, and ion implantation is carried out on a source region through photoetching and is respectively carried out;
s17: as shown in fig. 15: depositing an oxide layer to form the insulating dielectric layer, etching holes and filling metal to form a source metal layer, an isolation gate connection metal layer, a control gate connection metal layer and a back metal to form a drain metal layer respectively.
The above structures and processes are all prior art, and those skilled in the art can use any existing design that can implement its corresponding function.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (4)
1. A manufacturing method of an isolation gate groove type MOSFET device is characterized by comprising the following process steps:
s1: providing a substrate wafer, and growing an epitaxial layer on the substrate;
s2, growing a layer of SIN layer and SiO on the epitaxial layer by thermal furnace tube process and PECVD2The hard film layer is used for defining a Cell area, a polycrystalline silicon isolation gate connecting area at the bottom of the groove and a control gate connecting area through photoetching through layout design, etching the hard film, and performing deep groove etching on silicon by taking the hard film as a mask layer after removing a light resistor to form a groove 1, a groove 2 and a groove 3;
s3: etching the SIN layer by a wet method, and then removing the hard film oxide layer to enable the SIN at the opening of the groove to retract inwards, so that the CD at the opening of the groove is larger than the CD in the groove;
s4, growing oxide film by thermal oxidation furnace tube process to cover the surface, the side wall and the bottom of the groove;
s5: filling polycrystalline silicon, filling the whole groove without a cavity, and carrying out CMP grinding on the surface of the polycrystalline silicon to flatten the surface of the polycrystalline silicon;
s6, etching the polysilicon for the first time to be flush with the silicon surface, and then shielding the part of the region where the isolation gate is connected out by photoetching photoresist;
s7: etching the polycrystalline silicon for the second time to the inside of the groove, and reserving the length of the control grid for adjusting the length of the channel on the upper part of the groove;
s8, using the residual polysilicon as a mask to etch the thick oxide layer by a whole surface wet method, removing the redundant thick oxide layer on the surface of the groove and the upper wall end, adopting an over-etching mode, namely etching the thick oxide layer until the upper surface of the thick oxide layer is flush with the upper surface of the residual polysilicon, continuing etching the thick oxide layer, finally enabling the upper surface of the thick oxide layer in the cell area and the control gate connecting area to be slightly lower than the surface of the polysilicon at the bottom of the groove, and removing the light resistance;
s9, filling the insulating oxide layer between the gate electrode above the groove and the polysilicon electrode at the bottom of the groove, wherein HDPCVD is used during filling, and then SACVD is used for filling the insulating oxide layer above the groove;
s10, flattening the CMP surface, and removing the SiN layer on the silicon surface by a wet method;
s11: annealing the insulating isolation oxide layer under N2Environment 1100 deg.c/30 min;
s12, in order to avoid the side hook phenomenon, removing the residual oxide layer on the surface of the master in advance, and completely removing the oxide film with the residual thickness on the surface by adopting LHF solution;
s13, photoetching photoresistance to shield the isolation gate connected region, and designing PR to cover the silicon surface with a width 3 times larger than the wet etching depth of the insulating isolation oxide layer in order to avoid the side hook phenomenon;
s14, wet etching the insulating isolation oxide layer with a reserved thickness greater than 2500A, eliminating side hook phenomenon by removing surface oxide and controlling the width of the photoresist shielding isolation gate connection area, and eliminating surface sharp corner bulge phenomenon by dry etching;
s15: after removing the photoresistance, forming a gate oxide layer on the side wall of the groove;
s16: filling polycrystalline silicon into the groove to form a polycrystalline silicon gate layer, making the gate polycrystalline silicon interface slightly lower than the silicon surface through back etching, forming a body region through ion implantation, performing source region ion implantation through photoetching, and respectively advancing;
s17: depositing an oxide layer to form an insulating dielectric layer, etching holes and filling metal to respectively form a source metal layer, an isolation gate connection metal layer, a control gate connection metal layer and a back metal to form a drain metal layer.
2. The method of claim 1, wherein in step S9, the thickness of the insulating oxide layer is determined by the distance between the polysilicon surface at the bottom of the trench and the silicon surface, and the step filling or the multiple step filling is performed according to the filling thickness when HDPCVD is used, or if the thickness is greater than 20K, the multiple step filling is performed.
3. The method of claim 1, wherein in S12, the ratio of hydrofluoric acid to water in LHF solution is 1: 50.
4. An isolated gate trench MOSFET device produced by the method for producing an isolated gate trench MOSFET device according to any one of claims 1 to 3.
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| CN113851523A (en) * | 2021-09-02 | 2021-12-28 | 深圳市威兆半导体有限公司 | Shielding gate MOSFET and manufacturing method thereof |
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