CN112787673B - SDM integrator - Google Patents

SDM integrator Download PDF

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CN112787673B
CN112787673B CN202011611520.8A CN202011611520A CN112787673B CN 112787673 B CN112787673 B CN 112787673B CN 202011611520 A CN202011611520 A CN 202011611520A CN 112787673 B CN112787673 B CN 112787673B
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switch
capacitor
charge
time sequence
operational amplifier
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CN112787673A (en
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刘惠强
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3Peak Inc
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3Peak Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
    • H03M3/36—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability by temporarily adapting the operation upon detection of instability conditions

Abstract

The invention discloses an SDM integrator, which comprises an operational amplifier, a sampling capacitor, an integrating capacitor, a charging and discharging unit and a plurality of time sequence switches, wherein: the sampling capacitor is connected between the input signal and the input end of the operational amplifier, at the first moment, the SDM integrator is in a sampling mode, and the input signal charges the sampling capacitor; the integrating capacitor is connected between the output end and the input end of the operational amplifier, and the SDM integrator is in an integrating mode at the second moment; the charge and discharge unit is connected between the operational amplifier output end and the input signal and comprises a plurality of buffers and charge and discharge capacitors, the buffers charge the charge and discharge capacitors at a first moment, and the charge and discharge capacitors couple the output signal in the opposite direction at a second moment so as to raise the voltage of the output signal. According to the invention, the charge and discharge capacitor is charged through the buffer, and the charge and discharge capacitor couples the output signals in the opposite direction so as to lift the voltage of the output signals, so that the signal conversion time of the integrator is reduced, and the time for establishing the whole integrator is shortened.

Description

SDM integrator
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an SDM integrator.
Background
SDM (sigma-delta modulation) integrators are important functional circuits commonly used in signal processing chips, and have a significant impact on the overall performance of the signal processing chip.
FIG. 1 shows a circuit diagram of a prior art SDM integrator, which includes an operational amplifier OP and two sampling capacitors C 1 Two integrating capacitors C F And a plurality of time sequence switches (first time sequence switches S11, S12, second time sequence switches S21, S22, third time sequence switches S31, S32 and fourth time sequence switches S41, S42), wherein the control time sequences of the first time sequence switch, the second time sequence switch, the third time sequence switch and the fourth time sequence switch are phi 1, phi 1d, phi 2d and V42 respectively ICM Is an external reference voltage, V IN And V IP For input signal, V ON And V OP Is the output signal.
Referring to fig. 2, a control timing diagram of the timing switches is shown, where the first timing switch is closed earlier than the second timing switch, and the third timing switch is closed earlier than the fourth timing switch. At a first moment (phi 1), the first time sequence switch and the second time sequence switch are closed, the third time sequence switch and the fourth time sequence switch are opened, the circuit is in a sampling mode, and an input V is input IN And V IP To sampling capacitor C 1 Charging, completing sampling of the lower electrode plate at the moment when the first time sequence switch is switched off, and storing the input signal in the sampling capacitor C 1 In the polar plate of (1); at a second moment (Φ 2), the third timing switch and the fourth timing switch are closed, the first timing switch and the second timing switch are opened, and the circuit enters an integration mode. The input signal and the output signal satisfy:
Figure 827084DEST_PATH_IMAGE001
in the prior art, when the circuit is switched from a first time (Φ 1) to a second time (Φ 2), due to the capacitance C 1 The voltage at the two ends cannot change suddenly, and the high-resistance point VHP/VHN is coupled by the input signal. Since the output of the OP-amp OP is also high impedance to ground, the output will also be coupled. This coupling is in the opposite direction to the final output of the integrator and helps to create a voltage difference at the OP input to put the OP into signal conversion, and when the input signal is large, this coupling increases the signal conversion time of the integrator, thus prolonging the total integrator settling time.
Therefore, in view of the above technical problems, it is necessary to provide an SDM integrator.
Disclosure of Invention
The invention aims to provide an SDM integrator to reduce the signal conversion time of the integrator.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
an SDM integrator, the SDM integrator includes an operational amplifier, a sampling capacitor, an integrating capacitor, a charging and discharging unit and a plurality of time sequence switches, wherein:
the SDM integrator is connected between the input signal and the input end of the operational amplifier, and at a first moment, the SDM integrator is in a sampling mode, and the input signal charges the sampling capacitor;
the integrating capacitor is connected between the output end and the input end of the operational amplifier, and the SDM integrator is in an integrating mode at the second moment;
the charge and discharge unit is connected between the operational amplifier output end and the input signal and comprises a plurality of buffers and charge and discharge capacitors, the buffers charge the charge and discharge capacitors at a first moment, and the charge and discharge capacitors couple the output signal in the opposite direction at a second moment so as to raise the voltage of the output signal.
In one embodiment, the sampling capacitor comprises:
a first sampling capacitor C 11 Is connected to the first input signal V IP And the first input end of the operational amplifier;
second sampling capacitor C 12 Is connected to a second input signal V IN And a second input terminal of the operational amplifier.
In one embodiment, the integrating capacitor comprises:
first integrating capacitor C F1 A first output signal V connected to the first output terminal of the operational amplifier OP And the first input end of the operational amplifier.
Second integrating capacitor C F2 A second output signal V connected to the second output terminal of the operational amplifier ON And the first input end of the operational amplifier.
In one embodiment, the timing switch comprises:
a first timing switch including a first terminal connected to a reference voltage V ICM And a first sampling capacitor C 11 And a first switch S11 connected between the first plates, and a reference voltage V ICM And a second sampling capacitor C 12 A second switch S12 between the first plates;
a second time sequence switch including a first sampling capacitor C connected to the first switch 11 Second plate and first input signal V IP A third switch S21 arranged in between, and a second sampling capacitor C connected in between 12 Second pole plate and second input signal V IN A fourth switch S22 in between;
a third time sequence switch including a first sampling capacitor C connected to the first switch 11 And a fifth switch S31 connected between the first plate of the operational amplifier and the first input terminal of the operational amplifier, and a second sampling capacitor C 12 A sixth switch S32 between the first plate of the operational amplifier and the second input terminal of the operational amplifier;
a fourth timing switch including a switch connected to the reference voltage V ICM And a first sampling capacitor C 11 And a seventh switch S41 connected between the second plates and a reference voltage V ICM And a second sampling capacitor C 12 And an eighth switch S42 between the second pole plates.
In one embodiment, the timing switch:
at a first moment, the first time sequence switch and the second time sequence switch are closed, and the third time sequence switch and the fourth time sequence switch are opened;
at a second moment, the third time sequence switch and the fourth time sequence switch are closed, and the first time sequence switch and the second time sequence switch are disconnected;
wherein the first time sequence switch is closed in advance of the second time sequence switch, and the third time sequence switch is closed in advance of the fourth time sequence switch.
In one embodiment, the charge and discharge unit includes:
first buffer and first charge-discharge capacitor C 21 A first output signal V of the first input terminal of the first buffer and the first output terminal of the operational amplifier OP The second input end is connected with the output end, and the output end is connected with the first charge-discharge capacitor C 21 The second polar plate is connected with a first charging and discharging capacitor C 21 First polar plate and first input signal V IP Connecting;
a second buffer and a second charge-discharge capacitor C 22 A second output signal V between the first input terminal of the second buffer and the second output terminal of the operational amplifier ON The second input end is connected with the output end, and the output end is connected with a second charge-discharge capacitor C 22 The second polar plate is connected with a first charging and discharging capacitor C 22 First polar plate and second input signal V IN Are connected.
In one embodiment, the second timing switch further comprises:
connected to the output end of the first buffer and the first charge-discharge capacitor C 21 And a ninth switch S23 connected between the second plates and a reference voltage V ICM And a first charging/discharging capacitor C 21 And a tenth switch S24 connected between the output terminal of the second buffer and the second charge-discharge capacitor C 22 And an eleventh switch S25 connected between the second plates and a reference voltage V ICM And a second charge-discharge capacitor C 22 A twelfth switch S26 between the first plates;
the timing switch further includes:
a fifth time sequence switch including a first switch connected to the operational amplifierA first output signal V of the output terminal OP And a first charging/discharging capacitor C 21 And a thirteenth switch S51 connected to the first charge/discharge capacitor C 21 First polar plate and first input signal V IP A fourteenth switch S52 in between, and, a second output signal V connected to the second output terminal of the operational amplifier ON And a second charge-discharge capacitor C 22 A fifteenth switch S53 connected between the second plates and a second charging/discharging capacitor C 22 First polar plate and second input signal V IN Sixth switch S54 in between.
In one embodiment, the timing switch:
at the first moment, the second time sequence switch is closed, the fifth time sequence switch is opened, and the first buffer and the second buffer respectively charge and discharge the first charge and discharge capacitor C 21 And a second charge-discharge capacitor C 22 Charging is carried out;
at the second moment, the fifth time sequence switch is closed, the second time sequence switch is opened, and the first charging and discharging capacitor C 21 And a second charge-discharge capacitor C 22 The first output signal V OP And a second output signal V ON Coupled in the opposite direction to raise the first output signal V OP And a second output signal V ON The voltage of (c).
In one embodiment, the fifth timing switch is controlled by a pulse in the second time.
In one embodiment, the first buffer and/or the second buffer is one-stage or multi-stage buffer.
Compared with the prior art, the invention has the following advantages:
according to the invention, the charging and discharging capacitor is charged through the buffer, and the charging and discharging capacitor couples the output signals in the opposite directions so as to lift the voltage of the output signals, so that the signal conversion time of the integrator is reduced, and the time for establishing the whole integrator is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is also possible for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a circuit diagram of a prior art SDM integrator;
FIG. 2 is a timing diagram illustrating the control of a prior art timing switch;
FIG. 3 is a circuit diagram of an SDM integrator in accordance with one embodiment of the present invention;
FIG. 4 is a control timing diagram of the timing switch according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
The invention discloses an SDM integrator, which comprises an operational amplifier, a sampling capacitor, an integrating capacitor, a charging and discharging unit and a plurality of time sequence switches, wherein:
the sampling capacitor is connected between the input signal and the input end of the operational amplifier, at the first moment, the SDM integrator is in a sampling mode, and the input signal charges the sampling capacitor;
the integrating capacitor is connected between the output end and the input end of the operational amplifier, and the SDM integrator is in an integrating mode at the second moment;
the charge and discharge unit is connected between the operational amplifier output end and the input signal and comprises a plurality of buffers and charge and discharge capacitors, the buffers charge the charge and discharge capacitors at a first moment, and the charge and discharge capacitors couple the output signal in the opposite direction at a second moment so as to raise the voltage of the output signal.
The present invention is further illustrated by the following specific examples.
Fig. 3 is a circuit diagram of an SDM integrator in an embodiment of the present invention, where the SDM integrator includes an operational amplifier OP, a sampling capacitor, an integrating capacitor, a charging/discharging unit, and a plurality of timing switches, where:
the sampling capacitor is connected between the input signal and the input end of the operational amplifier, at the first moment, the SDM integrator is in a sampling mode, and the input signal charges the sampling capacitor;
the integrating capacitor is connected between the output end and the input end of the operational amplifier, and the SDM integrator is in an integrating mode at the second moment;
the charge and discharge unit is connected between the operational amplifier output end and the input signal and comprises a plurality of buffers and charge and discharge capacitors, the buffers charge the charge and discharge capacitors at a first moment, and the charge and discharge capacitors couple the output signal in the opposite direction at a second moment so as to raise the voltage of the output signal.
V ICM Is an external reference voltage, V IN And V IP For input signal, V ON And V OP Is the output signal.
Specifically, the sampling capacitor in this embodiment includes:
a first sampling capacitor C 11 Is connected to the first input signal V IP And a first input end of the operational amplifier OP;
second sampling capacitor C 12 Is connected to a second input signal V IN And a second input terminal of the OP-amp.
The integrating capacitor includes:
first integrating capacitor C F1 A first output signal V connected to the first output terminal of the operational amplifier OP OP And a first input terminal of the OP-amp.
Second integrating capacitor C F2 A second output signal V connected to the second output terminal of the operational amplifier OP ON And a first input terminal of the OP-amp.
The charge and discharge unit includes:
a first buffer BUF1 and a first charge-discharge capacitor C 21 A first output signal V between a first input terminal of the first buffer BUF1 and a first output terminal of the operational amplifier OP OP The second input end is connected with the output end, and the output end is connected with the first charge-discharge capacitor C 21 The second electrode plate is connected with the first electrode plate for charging and dischargingContainer C 21 First polar plate and first input signal V IP Connecting;
a second buffer BUF2 and a second charge-discharge capacitor C 22 A second output signal V between the first input terminal of the second buffer BUF2 and the second output terminal of the operational amplifier OP ON The second input end is connected with the output end, and the output end is connected with a second charge-discharge capacitor C 22 The second polar plate is connected with a first charging and discharging capacitor C 22 First polar plate and second input signal V IN Are connected.
The SDM integrator of the present embodiment includes a plurality of timing switches, and specifically includes:
a first timing switch including a first terminal connected to a reference voltage V ICM And a first sampling capacitor C 11 And a first switch S11 connected between the first plates, and a reference voltage V ICM And a second sampling capacitor C 12 A second switch S12 between the first plates;
a second time sequence switch including a first sampling capacitor C connected to the first switch 11 Second plate and first input signal V IP A third switch S21 arranged in between, and a second sampling capacitor C connected in between 12 Second pole plate and second input signal V IN A fourth switch S22 in between;
a third time sequence switch including a first sampling capacitor C connected to the first switch 11 And a fifth switch S31 connected between the first plate of the operational amplifier and the first input terminal of the operational amplifier, and a second sampling capacitor C 12 A sixth switch S32 between the first plate of the operational amplifier and the second input terminal of the operational amplifier;
a fourth timing switch including a switch connected to the reference voltage V ICM And a first sampling capacitor C 11 And a seventh switch S41 connected to the reference voltage V ICM And a second sampling capacitor C 12 And an eighth switch S42 between the second pole plates.
The second timing switch further includes:
connected to the output end of the first buffer and the first charge-discharge capacitor C 21 And a ninth switch S23 connected between the second plates and a reference voltage V ICM And a first charging/discharging capacitor C 21 And a tenth switch S24 connected between the output terminal of the second buffer and the second charging/discharging capacitor C 22 And an eleventh switch S25 connected between the second plates and a reference voltage V ICM And a second charge-discharge capacitor C 22 A twelfth switch S26 between the first plates;
the time sequence switch also comprises:
a fifth time sequence switch including a first output signal V connected to the first output terminal of the operational amplifier OP And a first charging/discharging capacitor C 21 And a thirteenth switch S51 connected to the first charge/discharge capacitor C 21 First polar plate and first input signal V IP A fourteenth switch S52 in between, and, a second output signal V connected to the second output terminal of the operational amplifier ON And a second charge-discharge capacitor C 22 A fifteenth switch S53 connected between the second plates and a second charging/discharging capacitor C 22 First polar plate and second input signal V IN Sixth switch S54 in between.
The circuit in this embodiment is symmetrically distributed, and the first sampling capacitor C 11 And a second sampling capacitor C 12 Identical, first integrating capacitor C F1 And a second integrating capacitor C F2 Identical, the first charge-discharge capacitor C 21 And a second charge-discharge capacitor C 22 Are identical.
The sampling capacitor, the integrating capacitor and the charging and discharging capacitor in this embodiment are all polar capacitors, the first electrode plate is a positive electrode plate of the capacitor, and the second electrode plate is a negative electrode plate of the capacitor.
Fig. 4 is a control timing diagram of the timing switch in the present embodiment, and the control principle is as follows:
at a first moment (phi 1), the first time sequence switch and the second time sequence switch are closed, the third time sequence switch and the fourth time sequence switch are opened, the circuit is in a sampling mode, and an input signal V is input IN And V IP For the first sampling capacitor C 11 And a second sampling capacitor C 12 Charging is carried out;
at the same time, the second time sequence switch is closed, the fifth time sequence switch is opened, and the first time sequence switch is openedThe buffer BUF1 and the second buffer BUF2 respectively charge and discharge the first charging and discharging capacitor C 21 And a second charge-discharge capacitor C 22 And charging is carried out.
At a second moment (phi 2), the third time sequence switch and the fourth time sequence switch are closed, the first time sequence switch and the second time sequence switch are disconnected, and the circuit enters an integration mode;
meanwhile, the fifth time sequence switch is closed, the second time sequence switch is opened, and the first charging and discharging capacitor C 21 And a second charge-discharge capacitor C 22 The first output signal V OP And a second output signal V ON Coupled in the opposite direction to raise the first output signal V OP And a second output signal V ON The voltage of (c).
The control time sequences of the first time sequence switch, the second time sequence switch, the third time sequence switch and the fourth time sequence switch are phi 1, phi 1d, phi 2 and phi 2d respectively, and the control time sequence of the fifth time sequence switch is phi 2_ pul. And the first time sequence switch is closed in advance of the second time sequence switch, and the third time sequence switch is closed in advance of the fourth time sequence switch.
In this embodiment, the first charge/discharge capacitor C is added 21 And a second charge-discharge capacitor C 22 The charge and discharge capacitor can couple the output signal in the opposite direction, and the output signal has an instant step rise. If the charge and discharge capacitance is selected properly, the step rise will make the output signal approach the final stable voltage quickly, thereby reducing the signal conversion time (slew) of the integrator.
In the present embodiment, it is assumed that the input signal changes slowly and can be considered to be unchanged in two adjacent time instants, which is an application condition in SDM with high OSR and thus is easily satisfied.
Since the present application only requires a back-coupling process, in order not to affect the output, the fifth timing switch in the present embodiment is controlled by a pulse in the second time, as shown in fig. 4.
The first buffer BUF1 and the second buffer BUF2 in this embodiment are used for charging and discharging the first charging and discharging capacitor C respectively at a first time (phi 1) 21 And a second charge-discharge capacitor C 22 Charging is carried out, the two buffersThe punch has enough time to charge the charging and discharging capacitor, high precision is not required, and the power consumption and the area required by the punch can be small.
In addition, at the first time (Φ 2), the input signal does not need to be applied to the first sampling capacitor C 11 And a second sampling capacitor C 12 Charging, whereby the input signal is directly connected to the first charging and discharging capacitor C 21 And a second charging and discharging capacitor C 22 To one end of (a). If the input driving capability is weak, one or more stages of buffers can be added on the basis of the first buffer BUF1 and the second buffer BUF2, and the buffers are similar to BUF1/BUF2 and do not need high precision.
The technical scheme shows that the invention has the following beneficial effects:
according to the invention, the charge and discharge capacitor is charged through the buffer, and the charge and discharge capacitor couples the output signals in the opposite direction so as to lift the voltage of the output signals, so that the signal conversion time of the integrator is reduced, and the time for establishing the whole integrator is shortened.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (9)

1. An SDM integrator, comprising an operational amplifier, a sampling capacitor, an integrating capacitor, a charging and discharging unit and a plurality of time sequence switches, wherein:
the SDM integrator is connected between the input signal and the input end of the operational amplifier, and at a first moment, the SDM integrator is in a sampling mode, and the input signal charges the sampling capacitor;
the integrating capacitor is connected between the output end and the input end of the operational amplifier, and the SDM integrator is in an integrating mode at the second moment;
the charge and discharge unit is connected between the operational amplifier output end and the input signal and comprises a plurality of buffers and charge and discharge capacitors, the buffers charge the charge and discharge capacitors at a first moment, and the charge and discharge capacitors couple the output signal in the opposite direction at a second moment so as to lift the voltage of the output signal;
the timing switch includes:
a first timing switch including a first terminal connected to a reference voltage V ICM And a first sampling capacitor C 11 And a first switch S11 connected between the first plates, and a reference voltage V ICM And a second sampling capacitor C 12 A second switch S12 between the first plates;
a second time sequence switch including a first sampling capacitor C connected to the first switch 11 Second plate and first input signal V IP A third switch S21 arranged in between, and a second sampling capacitor C connected in between 12 Second pole plate and second input signal V IN A fourth switch S22 in between;
a third time sequence switch including a first sampling capacitor C connected to the first switch 11 And a fifth switch S31 connected between the first plate of the operational amplifier and the first input terminal of the operational amplifier, and a second sampling capacitor C 12 A sixth switch S32 between the first plate of the operational amplifier and the second input terminal of the operational amplifier;
a fourth timing switch including a switch connected to the reference voltage V ICM And a first sampling capacitor C 11 And a seventh switch S41 connected between the second plates and a reference voltage V ICM And a second sampling capacitor C 12 Of the second plateAnd an eighth switch S42.
2. The SDM integrator of claim 1, wherein the sampling capacitor comprises:
a first sampling capacitor C 11 Is connected to the first input signal V IP And the first input end of the operational amplifier;
second sampling capacitor C 12 Is connected to a second input signal V IN And a second input terminal of the operational amplifier.
3. The SDM integrator of claim 2, wherein the integrating capacitor comprises:
first integrating capacitor C F1 A first output signal V connected to the first output terminal of the operational amplifier OP And between the first input end of the operational amplifier
Second integrating capacitor C F2 A second output signal V connected to the second output terminal of the operational amplifier ON And the first input end of the operational amplifier.
4. The SDM integrator of claim 1, wherein the timing switch:
at a first moment, the first time sequence switch and the second time sequence switch are closed, and the third time sequence switch and the fourth time sequence switch are opened;
at a second moment, the third time sequence switch and the fourth time sequence switch are closed, and the first time sequence switch and the second time sequence switch are disconnected;
wherein the first time sequence switch is closed in advance of the second time sequence switch, and the third time sequence switch is closed in advance of the fourth time sequence switch.
5. The SDM integrator of claim 1, wherein the charge and discharge unit comprises:
first buffer and first charge-discharge capacitor C 21 A first output signal V of the first input terminal of the first buffer and the first output terminal of the operational amplifier OP The second input end is connected with the output end, and the output end is connected with the first charge-discharge capacitorC 21 The second polar plate is connected with a first charging and discharging capacitor C 21 First polar plate and first input signal V IP Connecting;
a second buffer and a second charge-discharge capacitor C 22 A second output signal V between the first input terminal of the second buffer and the second output terminal of the operational amplifier ON The second input end is connected with the output end, and the output end is connected with a second charge-discharge capacitor C 22 The second polar plate is connected with a first charging and discharging capacitor C 22 First polar plate and second input signal V IN Are connected.
6. The SDM integrator of claim 5, wherein the second timing switch further comprises:
connected to the output end of the first buffer and the first charge-discharge capacitor C 21 And a ninth switch S23 connected between the second plates and a reference voltage V ICM And a first charging/discharging capacitor C 21 And a tenth switch S24 connected between the output terminal of the second buffer and the second charge-discharge capacitor C 22 And an eleventh switch S25 connected between the second plates and a reference voltage V ICM And a second charge-discharge capacitor C 22 A twelfth switch S26 between the first plates;
the timing switch further includes:
a fifth time sequence switch including a first output signal V connected to the first output terminal of the operational amplifier OP And a first charging/discharging capacitor C 21 And a thirteenth switch S51 connected to the first charge/discharge capacitor C 21 First polar plate and first input signal V IP A fourteenth switch S52 in between, and, a second output signal V connected to the second output terminal of the operational amplifier ON And a second charge-discharge capacitor C 22 A fifteenth switch S53 connected between the second plates and a second charging/discharging capacitor C 22 First polar plate and second input signal V IN Sixth switch S54 in between.
7. The SDM integrator of claim 6, wherein the timing switch:
at the first moment, the second time sequence switch is closed, the fifth time sequence switch is opened, and the first buffer and the second buffer respectively charge and discharge the first charge and discharge capacitor C 21 And a second charge-discharge capacitor C 22 Charging is carried out;
at the second moment, the fifth time sequence switch is closed, the second time sequence switch is opened, and the first charging and discharging capacitor C 21 And a second charge-discharge capacitor C 22 The first output signal V OP And a second output signal V ON Coupled in the opposite direction to raise the first output signal V OP And a second output signal V ON The voltage of (c).
8. The SDM integrator of claim 7, wherein the fifth timing switch is controlled by a pulse in the second time instance.
9. The SDM integrator of claim 5, wherein the first buffer and/or the second buffer is one or more stages of buffers.
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102025330A (en) * 2009-09-15 2011-04-20 雅马哈株式会社 Class-d amplifier

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US11867773B2 (en) * 2019-06-18 2024-01-09 Texas Instruments Incorporated Switched capacitor integrator circuit with reference, offset cancellation and differential to single-ended conversion

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102025330A (en) * 2009-09-15 2011-04-20 雅马哈株式会社 Class-d amplifier

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