CN216819709U - Triple voltage exponential function switch capacitor booster circuit - Google Patents

Abstract

The utility model discloses a triple voltage exponential function switch capacitor booster circuit which is formed by cascading more than 2 booster stages with the same structure. Each boosting unit comprises three capacitors and seven switching tubes, and the three capacitors are regularly charged and discharged by controlling the on and off of the switching tubes. The output voltage amplitude of each stage is approximately equal to three times of the input voltage amplitude of each stage, and a plurality of triple voltage unit structures are connected in series to form a triple voltage exponential function switch capacitor booster circuit. Compared with the traditional voltage doubling exponential function switch capacitor booster circuit, the utility model can obtain higher output voltage under the same stage number, or can achieve the same boosting effect by using fewer stage numbers, has higher energy efficiency and saves the chip area.

Description

Triple voltage exponential function switch capacitor booster circuit

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a triple voltage exponential function switch capacitor booster circuit.

Background

Low power self-powered energy harvesting technology is one of the important trends in the development of wearable electronic devices in the future. In the low power self-powered energy harvesting technology, the conventional boost circuit structure is mostly based on a linear charge pump, which is typically represented by Dickson charge pump proposed in 1976 and various linear charge pump structures developed based on the Dickson charge pump, and these circuits are characterized by relatively constant voltage difference between stages. However, due to the influence of various non-ideal factors such as MOS body effect, the output current of the linear charge pump is small, the output resistance is large, the oscillation frequency of the clock control signal is not allowed to be too high, the output voltage can be maintained stable only by externally connecting a capacitor with a large capacitance value at the output end, and meanwhile, the defects of high static current, large static loss and the like exist. Therefore, the boosting effect of the conventional boosting circuit (such as the voltage-doubling exponential-function switched capacitor boosting circuit shown in fig. 1) is still to be improved, and the power supply voltage requirement of the subsequent load circuit can be met only by multistage series connection in many application scenarios, so that the chip area is large and the cost is high.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the problem that the boosting effect of the traditional booster circuit needs to be improved, and provides a triple-voltage exponential function switch capacitor booster circuit.

In order to solve the problems, the utility model is realized by the following technical scheme:

a triple voltage exponential function switch capacitor booster circuit is formed by cascading more than 2 booster stages with the same structure; each boosting stage consists of 4 clocked switches SWN 1- SWN 4, 3 clocked switches SWP 1- SWP 3 and 3 capacitors C1-C3; the S end of the clock control switch SWN1, the S end of the clock control switch SWN2 and the S end of the clock control switch SWN4 are connected and then used as the input anode of the voltage boosting stage; the W end of the clock control switch SWN1 and the S end of the clock control switch SWP1 are connected with the upper electrode plate of the capacitor C1; the W end of the clock control switch SWN2 and the S end of the clock control switch SWP2 are connected with the upper pole plate of the capacitor C2; the lower pole plate of the capacitor C2, the W end of the clock control switch SWP1 and the S end of the clock control switch SWN3 are connected; the W end of the clock control switch SWN4 and the S end of the clock control switch SWP3 are connected with the lower pole plate of the capacitor C3; the W end of the clock-controlled switch SWP2 is connected with the upper electrode plate of the capacitor C3 and then is used as the output anode of the boosting stage; the lower polar plate of the capacitor C1, the W end of the clock control switch SWN3 and the W end of the clock control switch SWP3 are connected and then used as the input negative electrode and the output negative electrode of the boosting stage; control ends of the clock-controlled switches SWN 1-SWN 4 are connected with a first clock signal A, and control ends of the clock-controlled switches SWP 1-SWP 3 are connected with a second clock signal B; the input anode of the first stage boost stage is connected with the anode of the environment energy source VIN, and the input cathode of the first stage boost stage is connected with the cathode of the environment energy source VIN; the output anode of the previous stage is connected with the input anode of the next stage, and the output cathode of the previous stage is connected with the input cathode of the next stage; the input anode of the last stage of the boosting stage forms the output anode of the triple-voltage exponential function switch capacitor boosting circuit, and the input cathode of the last stage of the boosting stage forms the output cathode of the triple-voltage exponential function switch capacitor boosting circuit.

In the above scheme, the first clock signal a and the second clock signal B are clock control signals with equal amplitude and frequency and opposite phases.

Compared with the prior art, the triple-voltage exponential function switched capacitor boosting circuit is formed by connecting the single-stage triple-voltage switched capacitor boosting circuit in series, the obtained output voltage VOUT is equal to the input voltage VIN which is multiplied by the power N of 3, namely VOUT is equal to 3^NX VIN, and a conventional double voltage exponential switching capacitor boost circuit, which results in an output voltage of VOUT is equal to the input voltage VIN multiplied by 2 to the power N, i.e. VOUT is 2^NxVIN, wherein N is a number of stages. Compared with a voltage-doubling exponential function switched capacitor boosting circuit, the voltage-doubling exponential function switched capacitor boosting circuit can obtain higher output voltage under the same stage number, or can achieve the same boosting effect by using fewer stage numbers, so that the energy efficiency is higher, and the chip area is saved.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional voltage-doubling exponential-function switched capacitor boost circuit.

Fig. 2 is a schematic circuit diagram of a triple voltage exponential function switched capacitor boost circuit according to the present invention.

Fig. 3 is a comparison graph of the boosting effect of the triple voltage exponential function switched capacitor boosting circuit and the double voltage exponential function switched capacitor boosting circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to specific examples.

Referring to fig. 2, a triple-voltage exponential function switched capacitor boost circuit is formed by cascading 4 boost stages with the same structure.

Since the 4 voltage boosting stages have the same structure, the first stage voltage boosting stage will be described as an example. The first stage of boost stage consists of 7 clocked switches SWN 1-SWN 4, SWP 1- SWP 3 and 3 capacitors C1-C3. The S end of the clock control switch SWN1, the S end of the clock control switch SWN2 and the S end of the clock control switch SWN4 are connected and then used as the input anode of the voltage boosting stage; the W end of the clock control switch SWN1 and the S end of the clock control switch SWP1 are connected with the upper electrode plate of the capacitor C1; the W end of the clock control switch SWN2 and the S end of the clock control switch SWP2 are connected with the upper pole plate of the capacitor C2; the lower pole plate of the capacitor C2, the W end of the clock control switch SWP1 and the S end of the clock control switch SWN3 are connected; the W end of the clock control switch SWN4 and the S end of the clock control switch SWP3 are connected with the lower pole plate of the capacitor C3; the W end of the clock-controlled switch SWP2 is connected with the upper electrode plate of the capacitor C3 and then used as the output anode of the boost stage; the lower plate of the capacitor C1, the W end of the clock switch SWN3 and the W end of the clock switch SWP3 are connected to serve as the input negative electrode and the output negative electrode of the boosting stage. Control terminals of the clocked switches SWN1 to SWN4 are connected to a first clock signal a, and control terminals of the clocked switches SWP1 to SWP3 are connected to a second clock signal B. The first clock signal A and the second clock signal B are clock control signals with equal amplitude and frequency and opposite phases, the clock control switches SWN 1-SWN 4 and the clock control switches SWP 1-SWP 3 are alternately switched on under the control of the first clock signal A and the second clock signal B, namely, the two conditions are included, the first condition is that the clock control switches SWN 1-SWN 4 are switched off, and the clock control switches SWP 1-SWP 3 are switched on; in the second case, the clocked switches SWN1 to SWN4 are turned on, and the clocked switches SWP1 to SWP3 are turned off. The on and off of the clock control switch is controlled by the clock control signals A and B to regularly charge and discharge the capacitor, so that the output voltage amplitude VOUTn of a single stage is three times of the input voltage amplitude VINn of the single stage, namely the single stage VOUTn is 3 VINn.

The input anode of the first stage boost stage is connected with the anode of the environmental energy source VIN, and the input cathode of the first stage boost stage is connected with the cathode of the environmental energy source VIN. The output anode of the first stage boost stage is connected with the input anode of the second stage boost stage, and the output cathode of the first stage boost stage is connected with the input cathode of the second stage boost stage. The output anode of the second stage boost stage is connected with the input anode of the third stage boost stage, and the output cathode of the second stage boost stage is connected with the input cathode of the third stage boost stage. The output anode of the third stage boost stage is connected with the input anode of the fourth stage boost stage, and the output cathode of the third stage boost stage is connected with the input cathode of the fourth stage boost stage. The input anode of the fourth stage boost stage forms the output anode of the triple-voltage exponential function switch capacitor boost circuit, and the input cathode of the fourth stage boost stage forms the output cathode of the triple-voltage exponential function switch capacitor boost circuit.

The working principle of the utility model is as follows:

when the clock-controlled switch SWN is turned on and the clock-controlled switch SWP is turned off: the ambient energy source VIN charges the capacitors C1 and C2 through the clocked switches SWN1, SWN2 and SWN3, the capacitors C3, C4 and C5 through the clocked switches SWN4, SWN5, SWN6 and SWN7, the capacitors C6, C7 and C8 through the clocked switches SWN8, SWN9, SWN10 and SWN11, the capacitors C9, C10 and C11 through the clocked switches SWN12, SWN13, SWN14 and SWN15, and the output node VOUT through the clocked switches SWN16 and C12, respectively.

When the clock-controlled switch SWP is turned on and the clock-controlled switch SWN is turned off: the conduction of the clocked switches SWP1, SWP2 and SWP3 causes charge redistribution among the capacitors C1, C2 and C3, and the terminal voltage of the capacitor C3 is equal to the sum of the voltages of the capacitors C1 and C2; the conduction of the clocked switches SWP4, SWP5 and SWP6 causes charge redistribution to occur on the capacitors C4, C5 and C6, and the terminal voltage of the capacitor C6 is equal to the sum of the voltages of the capacitors C4 and C5; the conduction of the clocked switches SWP7, SWP8 and SWP9 causes charge redistribution among the capacitors C7, C8 and C9, and the terminal voltage of the capacitor C9 is equal to the sum of the voltages of the capacitors C7 and C8; the conduction of the clocked switches SWP10, SWP11 and SWP12 causes charge redistribution to occur across capacitors C10, C11 and C12, with the terminal voltage of capacitor C12 being equal to the sum of the voltages of capacitors C10 and C11.

1) Initialization process (i.e. charge redistribution process):

taking the first stage boost stage and the second stage boost stage as an example: when the clock-controlled switch SWN is turned on and the clock-controlled switch SWP is turned off, the capacitors C1 and C2 are connected in parallel, and the voltages at the two ends are equal to the input environmental energy source VIN, namely the power supply voltage; at the next moment, when the clock-controlled switch SWN is turned off and the clock-controlled switch SWP is turned on, the capacitors C1 and C2 become series connection, and the lower plate of the capacitor C2 is connected with the upper plate of the capacitor C1, since the voltage at the two ends of the capacitor cannot change suddenly, the voltage of the upper plate of the capacitor C2 jumps to 2VIN, and at this time, a loop formed by the capacitors C1, C2 and C3 generates charge redistribution, so that the voltages of the upper plate of the capacitor C2 and the upper plate of the capacitor C3 are reduced. When the clock-controlled switch SWN is turned on again and the clock-controlled switch SWP is turned off again, the upper plate of the capacitor C3, the upper plate of the capacitor C4, the upper plate of the capacitor C5 and the lower plate of the capacitor C6 are connected, and the voltage of the upper plate of the capacitor C3 is reduced again through charge distribution. When the clock-controlled switch SWN is turned on each time, the voltages of the upper electrode plates of the capacitors C1 and C2 are both VIN, and the voltage of the lower electrode plate of the capacitor C3 is also VIN; each time the clocked switch SWP is turned on, the upper plate of the capacitor C2 is close to 2VIN, which is greater than the upper plate voltage of the capacitor C3, so that the capacitors C1, C2 and C3 generate charge redistribution, and the upper plate voltage of the capacitor C3 is raised. After a long enough time, the charges are continuously redistributed to make the voltage difference at the two ends of all the capacitors tend to be stable and reach the maximum value under the corresponding conduction period, and the circuit finishes the initialization process. After the system is stabilized, when the clocked switch SWP is turned on, the capacitors C1, C2 and C3 are connected in series, the terminal voltage of C3 reaches the maximum value and depends on the maximum terminal voltage of the capacitor C2, and at this time, the upper plate of the capacitor C2 reaches the maximum voltage 2VIN, so that the voltage of the upper plate of the capacitor C3 is 2VIN, and the circuit completes the initialization process. This charge redistribution occurs at the capacitors C6, C9, and C12, as well as the initialization process, based on the same operating principle.

2) And (3) steady-state process:

for the first stage boost stage, in the first clock cycle, the clocked switches SWN 1-SWN 4 are turned on to charge the capacitors C1 and C2 with the charges transferred from the input terminal of the ambient energy source VIN, the voltages of the upper plates of the capacitors C1 and C2 are equal to the ambient energy source VIN, the voltages of the lower plates of the capacitors C1 and C2 are grounded, and the voltage difference between the charged capacitor C1 and the capacitor C2 is equal to the ambient energy source VIN. In the second clock cycle, the clocked switches SWN 1-SWN 4 of the first stage boost stage are turned off, while the clocked switches SWP 1-SWP 3 are turned on. The lower plate of the capacitor C2 is connected with the upper plate of the capacitor C1, so that the voltage of the lower plate of the capacitor C2 is changed into VIN, the voltage of the two ends of the capacitor cannot be suddenly changed, the voltage of the upper plate of the capacitor C2 is changed into 2VIN, the upper plate of the capacitor C2 is connected with the upper plate of the capacitor C3, the grounding voltage of the lower plate of the capacitor C3 is 0, and the voltage difference of the two ends of the capacitor C3 is 2 VIN. Then, in the next clock cycle, the clock control switches are switched to turn on the clock control switches SWN 1-SWN 4, turn off the clock control switches SWP 1-SWP 3, and charge the upper plate of the capacitor C2 and the lower plate of the capacitor C3 to VIN. The voltage Vout1 of the upper plate of the capacitor C3 becomes 3VIN (3 VIN) because the voltage between the two ends of the capacitor can not change suddenly¹VIN) and output, thus completing the boosting of the first stage boosting stage by three times.

For the second stage boost stage, in the first clock cycle, the clocked switches SWN 5-SWN 8 are turned on, so that the output of the first stage boost stage is used as the input of the second stage boost stage to transfer charges to the capacitors C4 and C5 for charging, and the voltages of the upper plates of the capacitors C4 and C5 are Vout1 (namely 3:)¹VIN), the lower plates of the capacitors C4 and C5 are grounded, and the voltage difference between the two ends is equal to 3 VIN. In the second clock period, the clocked switch SWN 5E of the second stage boost stageSWN8 is turned off, while clocked switches SWP4 SWP6 are turned on. The lower plate of the capacitor C5 is connected with the upper plate of the capacitor C4, so that the lower plate voltage of the capacitor C5 is changed to 3VIN, and the upper plate voltage of the capacitor C5 is changed to 6VIN because the capacitor pressure difference cannot change suddenly. The upper plate of the capacitor C5 is connected with the upper plate of the capacitor C6, the grounding voltage of the lower plate of the capacitor C6 is 0, and the voltage difference of the capacitor C6 is 6 VIN. Then, in the next clock cycle, the clock control switches are switched to turn on the clock control switches SWN5 to SWN8, turn off the clock control switches SWP4 to SWP6, and charge the upper plate of the capacitor C5 and the lower plate of the capacitor C6 to 3 VIN. Since the voltage difference of the capacitor cannot change abruptly, the voltage of the upper plate of the capacitor C6 becomes 9VIN (i.e. 3 times 3VIN, i.e. 3 times that of the capacitor C6²VIN) and output, and finishing the boosting of the second stage boosting stage by three times.

For the third stage boost stage, in the first clock cycle, the clocked switches SWN 9-SWN 12 are turned on, so that the output of the second stage boost stage is used as the input terminal of the third stage boost stage to transfer charges to the capacitors C7 and C8 for charging, the voltages of the upper plates of the capacitors C7 and C8 are Vout2 (i.e., 9VIN), the voltages of the lower plates of the capacitors C7 and C8 are grounded, and the voltage difference between the two ends is equal to 9 VIN. In the second clock cycle, the clocked switches SWN9 to SWN12 of the third stage boost stage are turned off, and the clocked switches SWP7 to SWP9 are turned on. The lower plate of the capacitor C8 is connected with the upper plate of the capacitor C7, so that the lower plate voltage of the capacitor C8 is 9VIN, and the upper plate voltage of the capacitor C8 is 18VIN because the capacitor pressure difference cannot change suddenly. The upper plate of the capacitor C8 is connected with the upper plate of the capacitor C9, the grounding voltage of the lower plate of the capacitor C9 is 0, and the voltage difference of the capacitor C9 is 18 VIN. Then, in the next clock cycle, the clock control switches are switched to turn on the clock control switches SWN 9-SWN 12 of the third stage boost stage, turn off the clock control switches SWP 7-SWP 9, and charge the upper plate of the capacitor C8 and the lower plate of the capacitor C9 to 9 VIN. Because the voltage difference of the capacitor cannot change suddenly, the voltage of the upper plate of the capacitor C9 becomes 27VIN (namely 3 times 9VIN, namely 3 times of 9VIN)³VIN) and output. And completing the boosting of the third stage boosting stage by three times.

For the fourth stage boost stage, in the first clock cycle, the clocked switches SWN 13-SWN 16 are turned on to charge the capacitors C10 and C11 with the output of the third stage boost stage as the input of the fourth stage boost stage, and the capacitors are chargedThe voltage of the upper plates of the capacitors C10 and C11 is Vout3 (namely 27VIN), the lower plates of the capacitors C10 and C11 are grounded, and the voltage difference between the two ends is equal to 27 VIN. In the second clock cycle, the clocked switches SWN13 to SWN16 of the third stage boost stage are turned off, and the clocked switches SWP10 to SWP12 are turned on. The lower plate of the capacitor C11 is connected with the upper plate of the capacitor C10, so that the lower plate voltage of the capacitor C11 is 27VIN, and the upper plate voltage of the capacitor C11 is 54VIN because the capacitor pressure difference cannot suddenly change. The upper plate of the capacitor C11 is connected to the upper plate of the capacitor C12, the ground voltage of the lower plate of the capacitor C12 is 0, and the voltage difference of the capacitor C12 is 54 VIN. Then, in the next clock cycle, the clock control switches are switched to turn on the clock control switches SWN 13-SWN 16 of the third stage boost stage, turn off the clock control switches SWP 10-SWP 12, and charge the upper plate of the capacitor C11 and the lower plate of the capacitor C12 to 27 VIN. Since the capacitor voltage difference cannot change abruptly, the voltage of the upper plate of the capacitor C12 becomes 81VIN (3 times 27VIN, i.e. 3)⁴VIN), so the final output Vout is 81VIN (i.e., 3)⁴VIN), completing the boosting of the third voltage of the fourth stage voltage boosting stage, i.e. the boosting of the three-voltage exponential function switch capacitor of the whole circuit.

Simulation software is used for carrying out simulation verification on the voltage doubling exponential function switched capacitor booster circuit and the voltage tripling exponential function switched capacitor booster circuit, as shown in fig. 3, under the condition that the input voltage is also 200mV, the first stage, the second stage, the third stage and the fourth stage of the voltage doubling exponential function switched capacitor booster circuit can respectively output 0.398V, 0.794V, 1.586V and 3.171V, and the effect of approximate square boosting is achieved; the first stage, the second stage, the third stage and the fourth stage of the triple-voltage exponential function switch capacitor booster circuit respectively output 0.552V, 1.632V, 4.875V and 14.596V, and the N-stage triple-voltage exponential function switch capacitor booster circuit is approximately cubically boosted, namely 3^NDouble effect.

It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and therefore, the present invention is not limited to the above-mentioned specific embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.

Claims (2)

1. A triple voltage exponential function switch capacitor booster circuit is characterized in that: the power supply is formed by cascading more than 2 boosting stages with the same structure;

each boosting stage consists of 4 clocked switches SWN 1-SWN 4, 3 clocked switches SWP 1-SWP 3 and 3 capacitors C1-C3; the S end of the clock control switch SWN1, the S end of the clock control switch SWN2 and the S end of the clock control switch SWN4 are connected and then serve as the input anode of the boost stage; the W end of the clock control switch SWN1 and the S end of the clock control switch SWP1 are connected with the upper electrode plate of the capacitor C1; the W end of the clock control switch SWN2 and the S end of the clock control switch SWP2 are connected with the upper pole plate of the capacitor C2; the lower pole plate of the capacitor C2, the W end of the clock control switch SWP1 and the S end of the clock control switch SWN3 are connected; the W end of the clock control switch SWN4 and the S end of the clock control switch SWP3 are connected with the lower pole plate of the capacitor C3; the W end of the clock-controlled switch SWP2 is connected with the upper electrode plate of the capacitor C3 and then used as the output anode of the boost stage; the lower polar plate of the capacitor C1, the W end of the clock control switch SWN3 and the W end of the clock control switch SWP3 are connected and then used as the input negative electrode and the output negative electrode of the boosting stage; control ends of the clock-controlled switches SWN 1-SWN 4 are connected with a first clock signal A, and control ends of the clock-controlled switches SWP 1-SWP 3 are connected with a second clock signal B;

the input anode of the first stage boost stage is connected with the anode of the environment energy source VIN, and the input cathode of the first stage boost stage is connected with the cathode of the environment energy source VIN; the output positive electrode of the previous stage of the boost stage is connected with the input positive electrode of the next stage of the boost stage, and the output negative electrode of the previous stage of the boost stage is connected with the input negative electrode of the next stage of the boost stage; the input anode of the last stage of the boosting stage forms the output anode of the triple-voltage exponential function switch capacitor boosting circuit, and the input cathode of the last stage of the boosting stage forms the output cathode of the triple-voltage exponential function switch capacitor boosting circuit.

2. The voltage tripled exponential switched capacitor boost circuit of claim 1, wherein the first clock signal a and the second clock signal B are clock control signals having equal amplitude and frequency and opposite phases.

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