CN112787638A

CN112787638A - Double-channel synchronous multiple loading pulse generation method

Info

Publication number: CN112787638A
Application number: CN202011579629.8A
Authority: CN
Inventors: 吴迪; 王薪贵; 鲍温霞; 王靖; 杨智勇; 禹明慧; 郑分刚; 陶智; 张晓俊
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2021-05-11

Abstract

The invention discloses a double-channel synchronous reloading pulse generating method, which comprises a clock generating module, a synchronous reloading counting module and a signal edge triggering module, and comprises the following steps: 1) the clock generation module generates two counting clock signals with similar frequencies and a synchronous loading signal; 2) outputting the counting clock and the synchronous loading signal to a synchronous reloading counting module; 3) when the counting value of the synchronous reloading counting module meets the condition, an indicating signal is output to the signal edge triggering module to generate a pulse signal with a required width, so that the FPGA direct output of the nanosecond pulse signal is realized. Through the mode, the nanosecond transient pulse is directly generated through the vernier effect generated between the two channels and the logic operation of the indicating signal, and on the basis, the pulse width modulation with nanosecond precision can be realized through changing the counting value.

Description

Double-channel synchronous multiple loading pulse generation method

Technical Field

The invention relates to the field of industrial control and optoelectronic communication, in particular to a double-channel synchronous reloading pulse generation method.

Background

The high-speed pulse signal is used as the basis of modern electronic technology and has wide application in the aspects of electronic communication, industrial control, acquisition, measurement and the like. With the continuous development of information science, in order to make the electronic device have better versatility and flexibility, narrower and narrower pulse width and high-precision pulse width modulation are important development directions for high-speed pulse signal generation.

In the beginning of the 20 th century, humans have begun to use string vibrations to generate pulse signals of a certain frequency. Then, the pulse width generated by using gas and spark discharge is reduced from millisecond level to microsecond level. It is expensive to develop and complex in design process, and has been rarely used again.

Since the 20 th century and the 70 th era, the original analog signal processing was replaced by digital signal processing, and a method of generating a pulse signal by using integrated logic gate control was applied [6 ]. With the continuous development of computer technology, programmable real-time pulse generating circuits become the mainstream. The devices such as the single chip microcomputer and the microcontroller have the advantages of low cost and small volume, and the method for generating pulses by controlling the input and output ports of the single chip microcomputer and the microcontroller by using clock signals becomes a common method at present. However, the clock frequency of such devices is generally low, so the precision is relatively low, and the devices are limited by peripheral analog circuits, and have poor control flexibility and weak interference resistance. The programmable logic devices such as FPGA have incomparable superiority in the field of pulse signal generation with the remarkable advantages of high flexibility, good real-time performance, high data processing efficiency and the like, pulse generation with nanosecond precision and pulse width modulation are realized, most of measurement and control requirements are met, but the requirement of high working frequency is needed for further reducing the pulse width, and the requirement is generally difficult to be met by a general FPGA. Although the method of building a semiconductor transistor circuit can realize an extremely narrow pulse signal, it cannot realize pulse width adjustment due to circuit design, and is difficult to use. The edge compression technology based on the nonlinear transmission line can greatly compress the transition time of the edge of the pulse signal to generate a picosecond-level pulse signal through the setting of transmission materials, technical processes and parameters, but the nonlinear transmission line technology is not disclosed and has technical monopoly. In addition, the technology of generating the pulse with higher resolution by using the polarization gating technology has just started, the design is very complicated, and the generated pulse width is difficult to control and utilize, which is the current leading-edge subject.

Disclosure of Invention

The invention aims to provide a double-channel synchronous reloading pulse generation method, which directly generates nanosecond transient pulses for indicating signal logic operation through a vernier effect generated between two channels, and can realize nanosecond-precision pulse width modulation by changing a counting value on the basis.

In order to solve the technical problems, the invention adopts a technical scheme that: the double-channel synchronous complex loading pulse generation method comprises a clock generation module, a synchronous complex loading counting module and a signal edge triggering module, and comprises the following steps:

1) the clock generation module generates two counting clock signals with similar frequencies and a synchronous loading signal;

2) outputting the counting clock and the synchronous loading signal to a synchronous reloading counting module;

3) when the counting value of the synchronous reloading counting module meets the condition, an indicating signal is output to the signal edge triggering module to generate a pulse signal with a required width, so that the FPGA direct output of the nanosecond pulse signal is realized.

Further, the step 1) clock generation module generates two clock signals CLK a and CLK B with similar frequencies and a LOAD signal LOAD of 1 MHz.

Further, the synchronous reloading counting module in step 2) includes a first channel reload _ a and a second channel reload _ B, where the first channel reload _ a and the second channel reload _ B respectively count respective input clock pulses, and the count values are input a _ Value and B _ Value, respectively.

Further, the clock signal CLK a is used as a count clock for synchronizing the first channel reload _ a of the multiple load count section; the clock signal CLK B is used as the counting clock of the second channel reload _ B.

Further, when the rising edge of the LOAD signal LOAD clock signal arrives, a _ Value and B _ Value are synchronously loaded into the two counting channels again, and the next round of counting is restarted.

Furthermore, each time the count Value reaches the loaded count Value a _ Value or B _ Value, the corresponding counting channel generates an indication Signal, the indication Signal generated by the first channel reload _ a is a SET Signal, the indication Signal generated by the second channel reload _ B is a RESET Signal, and due to different counting clock frequencies, a phase difference exists between the generated rising edges of the SET and RESET signals, and the rising edges of the SET and RESET signals trigger the level inversion of the output Signal, so that a transient pulse Signal with adjustable pulse width is generated.

Further, the LOAD signal continuously and repeatedly LOADs the counting values of the two channels synchronously, and the pulse signal continuously appears at a certain frequency to realize pulse generation.

Further, the clock generation module uses a single phase-locked loop, and the generated optimal clock signals are 48MHz and 50 MHz.

Further, the reloading counting module is designed by a register state, and the state of the state machine is controlled by the input RELOAD signal and the count value cnt.

Further, the signal edge triggering module is composed of a basic logic gate and a latch, and the latch respectively latches a signal state and an output signal q.

The invention has the beneficial effects that: the double-channel synchronous reloading pulse generation method can count clock signals with similar frequencies and generate indication signals by using the double-channel synchronous reloading counting module under the limited FPGA working frequency, and finally can achieve nanosecond pulse resolution of 0.833 ns.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of a dual channel synchronous reload pulse generation method of the present invention;

FIG. 2 is a timing diagram of a dual channel synchronous reload pulse generation of the present invention;

FIG. 3 is a RTL view of a dual channel synchronous reload pulse generation method of the present invention;

FIG. 4 is a PLL structure diagram of an FPGA chip of the dual-channel synchronous multiple loading pulse generation method of the present invention;

FIG. 5 is an RTL view of the synchronous reload module of the dual channel synchronous reload pulse generation method of the present invention;

FIG. 6 is a timing diagram of the operation of the synchronous reload module of the dual channel synchronous reload pulse generating method of the present invention;

FIG. 7 is a signal edge trigger module RTL view of a dual channel synchronous multiple loading pulse generation method of the present invention;

FIG. 8 is a Modelsim minimum resolution simulation waveform of a dual channel synchronous multiple loading pulse generation method of the present invention;

FIG. 9 is a ModelSim functional simulation waveform of a dual channel synchronous reload pulse generation method of the present invention;

fig. 10 is a 0.833ns pulse signal waveform of a dual channel synchronous reload pulse generation method of the present invention;

FIG. 11 is an 4.998ns pulse signal waveform of a two-channel synchronous multiple load pulse generation method of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings and described in accordance with the drawings are exemplary only, and the invention is not limited to these embodiments.

It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.

Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 to 10, an embodiment of the present invention includes: a double-channel synchronous multiple loading pulse generation method comprises a clock generation module, a synchronous multiple loading counting module and a signal edge triggering module, and comprises the following steps:

Aiming at the problems of the pulse signal generating method designed by the FPGA at present, the double-channel synchronous reloading pulse generating method is provided, and a nanosecond transient pulse generating system is designed based on the double-channel synchronous reloading pulse generating method. The system adopts a dual-channel structure to generate indication signal output for a clock signal rising edge technology with similar frequency, utilizes a vernier effect generated between the two channels to directly generate nanosecond transient pulse for indication signal logic operation, and can realize nanosecond-precision pulse width modulation by changing a count value on the basis.

According to the double-channel synchronous reloading pulse generation method, the highest working frequency of the current general FPGA is usually below 500MHz, and the generation requirement of directly generating nanosecond transient pulses cannot be met. The double-channel synchronous reloading pulse generation method comprises three parts, namely Clock generation (Clock Generator), synchronous reloading count (reload _ A, Reloader _ B) and Signal edge Trigger (Signal edge Trigger). The clock generation section mainly generates two clock signals having similar frequencies and a loading signal. The synchronous complex loading counting part is a control module which is formed by two counting channels capable of being loaded with counting values synchronously by loading signals, each channel counts respective clock signals and generates indication signals, and the two generated indication signals are triggered through signal edges to realize narrow pulses with nanosecond precision generated by output level inversion.

As shown in FIG. 1, the dual channel synchronous multiple LOAD pulse generation method first generates two clock signals CLK A and CLK B with similar frequencies and a LOAD signal LOAD of 1 MHz. The CLK A frequency is higher and is used as the counting clock of the first channel reload _ A of the synchronous reloading counting part, and the CLK B frequency is slightly lower and is used as the counting clock of the second channel reload _ B. The two channels respectively count respective input clock pulses, the count values are respectively input A _ Value and B _ Value, and when the rising edge of the LOAD clock signal arrives, the A _ Value and the B _ Value are synchronously loaded into the two counting channels again to restart the next round of counting. When the counting Value reaches the loaded counting Value A _ Value or B _ Value, the corresponding counting channel generates an indication Signal, the indication Signal generated by the channel Reloader _ A is an SET Signal, the indication Signal generated by the channel Reloader _ B is a RESET Signal, and due to different counting clock frequencies, a phase difference exists between the rising edges of the generated SET and RESET signals, and the level of the output Signal is triggered to flip at the rising edges of the SET and RESET signals, so that a transient pulse Signal with adjustable pulse width can be generated. The LOAD signal continuously LOADs the counting values of the two channels synchronously, and the pulse signal continuously appears at a certain frequency to realize pulse generation. A timing diagram for the two-channel synchronous reload pulse generation is shown in fig. 2.

When the rising edge of the generated LOAD signal LOAD arrives, the count values a _ Value and B _ Value are loaded into the two channels synchronously. The two channels are counted respectively by using CLK _ A and CLK _ B, the rising edge count value of each clock signal is reduced by 1, when the count value becomes 0, the two channels respectively output SET and RESET signals, the rising edge of the SET signal enables the output OUT to be SET to 1, the rising edge of the RESET signal enables the output OUT to be SET to 0, and transient pulse signals are generated. When the next rising edge of the LOAD signal comes, synchronous reloading of the double-channel counting value is achieved, and the generation process of the pulse signal is repeated.

The width of the generated pulse signal is related to the input count values (a _ Value, B _ Value) and the frequency of the input clocks (CLK a, CLK B), the frequency of the input clocks determines the minimum resolution of the pulse signal width, for example, 48MHz and 50MHz, the time required for the 48MHz clock to count once is 1/48MHz, the time required for the 50MHz clock to count once is 1/50MHz, and through the above analysis, the time difference between the two channel counting is the minimum resolution of the output, and the minimum resolution can be calculated as:

i.e. a minimum pulse width of 0.833ns is generated.

The calculation formula of the pulse width W generated by changing the count value is as follows:

according to the pulse width calculation formula, the pulse widths corresponding to the values of a _ Value and B _ Value are shown in table 1.

TABLE 1 relationship between pulse width and values of A _ Value and B _ Value (unit: ns)

When the values of A _ Value and B _ Value are both 0, the pulse width is 0, and no pulse signal is generated; when a _ Value is equal to B _ Value, the generated pulse width is a _ Value (or B _ Value) × 0.833 ns; under other Value conditions, if the clock frequency is 50MHz and 48MHz, and the initial loading signal is 1MHz, to enable the module to generate the indication signal before the next initial reloading, the maximum count values B _ Value and a _ Value are 49 and 47, respectively, and when a _ Value takes the maximum Value of 49, and B _ Value takes the maximum Value of 47, the maximum pulse width can be generated, and the width is 999.151 ns.

The transient pulse generation method based on the dual-channel synchronous reloading is a nanosecond transient pulse generation system, an RTL view of the system is shown in figure 3, and the system can be divided into a clock generation module, a synchronous reloading module and a signal edge triggering module. These three important module designs will be detailed herein below.

The clock is used as the basis of a sequential circuit and is very important in the whole FPGA program development process. Clock signals of any frequency can be generated by using a direct digital frequency synthesis (DDS) technology, and any clock signal combination within the working frequency of the FPGA can be generated by a multi-phase-locked loop (PLL). However, the dual-channel synchronous multiple loading pulse generation method provided by the invention has extremely high requirements on the phase synchronism of the generated clock, and the methods cannot ensure that the initial phases of the signals are completely the same. In order to ensure that the phases of clock signals are equal and the frequencies of the clock signals are stable, a clock generation module of the dual-channel synchronous complex loading pulse generation method is designed by using a single phase-locked loop. Because the multiple clocks generated by using a single phase-locked loop are restricted by the internal structure of the FPGA, the frequency of the generated clock needs to be carefully designed. After many tests, the generated optimal clock signals are 48MHz and 50 MHz.

As shown in fig. 4, the PLL is a closed-loop frequency control system, and the nanosecond pulser designed herein uses an Altera FPGA chip to perform parameter setting on the PLL through an IP core. Firstly, a 50MHz clock generated by an external crystal oscillator generates a 2MHz clock through a pre-frequency divider (N is 25) and is sent to a phase discriminator, the phase discriminator compares a feedback signal with an input clock, and a control signal is sent out to drive a voltage-controlled oscillator to adjust the frequency of an output clock through a loop filter until the two signals are synchronous. When the feedback counter M in the feedback loop is 24, the system is stable when the output clock is 48MHz, which is equivalent to performing 25 frequency division and 24 frequency multiplication on 50MHz to output a 48MH clock signal.

The 50MHz and 48MHz clocks generated by the clock generation module are used as the working clocks of the double-channel synchronous complex loading counting module.

The double-channel synchronous repeated loading counting module consists of two repeated loading counting modules and plays a role in core control in the design of the transient pulse generating circuit. In order to generate a pulse signal with stable frequency, the indication signals output by the two channel modules are required to synchronously and stably appear according to a certain period, and the output of the indication signals is directly controlled by the pulse counting value, so that whether the two channel counting values can be synchronously reloaded or not can have a great influence on the generated pulse signal.

In order to realize the periodic synchronous reloading of the count value, a reloading counting module design method is provided, an RTL view of the method is shown as 5, the reloading counting module is designed by a register state, and the state of a state machine is controlled by an input RELOAD signal and the count value cnt together. The working state of the initial state machine is 0, the Selector12 selects and outputs a Signal of 0, each bit of the eight-bit count register cnt is controlled by the Selector to be a fixed value and remains unchanged, and the loading Signal is waited to load the count value. When the rising edge of the RELOAD Signal comes, the operating state of the state machine changes to 1, the register cnt is given an initial value and then counts down at the rising edge of the CLK Signal, and the comparator outputs a change when the cnt counts to 0, so that the Selector12 outputs 1 to change the Signal to high level, and simultaneously the operating state of the state machine changes to 2. Operating state 2 remains for one CLK clock cycle and pulls the indicator signal low into state 3. And when the state 3 detects the falling edge of the LOAD signal, the state returns to the state 0 to wait for the next loading signal, so that the cnt register is prevented from being repeatedly loaded in one loading signal for multiple times.

The working timing diagram of the reloading module of this design is shown in fig. 6, where a LOAD count Value starts counting triggered by a rising edge of a LOAD signal, when each rising edge of a CLK clock signal arrives, the Value of the register is decremented by 1, when the Value in the register is decremented by 1 and becomes 0, the counting is completed, an indication signal is output, and after a clock cycle is maintained, the next loading is waited. When the rising edge of the LOAD signal comes next time, the Value is reloaded, counting is started again, and a stable indicating signal is generated according to a certain period.

When the initial phases of the counting clock signals of the two compound loading counting modules are the same and the same LOAD signal is used for carrying out compound loading of the counting value, the double-channel synchronous compound loading counting module is formed. The double-channel synchronous complex loading module counts two generated indication signals and generates corresponding transient pulse signals through the Signal edge triggering module.

The signal edge triggering module is used for outputting transient pulse signals, and the phase difference of the generated indicating signals is different according to the difference of preset counting values of the synchronous reloading counting module. To realize a pulse signal with any width in table 1, it is strictly required that the signal edge trigger block realizes that the output signal becomes high level at the time of the rising edge of the input signal SET and becomes low level at the time of the rising edge of RESET. When the output indication signals of the two-channel synchronous reloading counter, namely the rising edge moments of the SET and RESET signals are very close to each other, the high and low levels of the output signals can be turned over in a very short time to generate a very narrow transient pulse signal. One possible design approach is presented herein, with an RTL view as shown in fig. 7.

The circuit actually comprises a basic logic gate and a latch, wherein the latch respectively latches a signal state and an output signal q.state as state quantities to represent the current state of the RESET signal. When the state is 1, the rising edge of the RESET signal is reached and the RESET still keeps high level; the state changes only when the state of the RESET signal changes, otherwise, the state is latched by a latch. The initial states of the SET and RESET signals are both low level, and at this time, the state and the output q state are both 0. As soon as the RESET signal rising edge arrives, the latch RESET pin ACLR of the output q is enabled, the q value is cleared, and then the state is set to 1. When the rising edge of the SET signal comes, as long as the rising edge does not occur at the same time of the RESET signal, the SET of the q latch can always become the high level output 1 after the logic operation.

The truth table of the signal edge trigger module designed by the invention is shown in table 2.

Table 2 signal edge triggered module truth table

As shown in the truth table of the edge triggered module, the SET signal is low, the output signal is 0 only when the RESET signal reaches the rising edge, and the output remains unchanged in other states. At the rising edge of the SET, only the RESET signal outputs 0 for the rising edge module at the same time, and the rest states are all 1. When the SET signal is in a high level or a falling edge state, only the rising edge of the RESET signal triggers the 0 output, and the output is kept unchanged in other states. From the truth table, the output state can be triggered to change only by the rising edges of the input signals SET and RESET, the rising edge of SET makes the output signal 1, the rising edge of RESET makes the output signal 0, and when the rising edges of SET and RESET come together, the state of the output signal becomes 0.

Through the design of the functional modules, nanosecond-level pulse generation is realized. The pulse generator firstly generates two paths of clock signals with similar frequencies of 50MHz and 48MHz by the clock generating module, and the two paths of clock signals are respectively used as working clocks of the synchronous complex loading module Reloader _ A, Reloader _ B. The reload _ A, Reloader _ B generates the indication signals Signal _ a and Signal _ B, respectively, and if the count Value a _ Value is equal to B _ Value is equal to 1, both reload _ a and reload _ B will output the indication signals after one working period, and the rising edge of Signal _ a will come before Signal _ B due to the higher frequency of CLK _ a, and the time difference between the two is 0.833 ns.

Signal _ A and Signal _ B are input into the Signal edge triggering module, wherein the Signal _ A is used as SET, and the Signal _ B is used as RESET. The Signal edge triggering module can trigger output change only at the rising edge of the Signal, when the rising edge of the Signal _ A comes, the output Signal becomes 1, and after 0.833ns, the rising edge of the Signal _ B Signal sets the output Signal to be 0, so that a narrow pulse Signal with the width of 0.833ns is generated.

The invention adopts Modelsim software to perform functional simulation. To test the minimum accuracy of the pulse width, the count values of the synchronous reload modules are all set to 1, and a 50MHz square wave is used as an input clock. The results of the experiment are shown in FIG. 8. When the initial count values of the dual-channel synchronous multiple loading counting module are all 1, the generated pulse width is the minimum pulse width which can be generated by the dual-channel synchronous multiple loading pulse generation method and is also the minimum resolution of pulse width adjustment. According to a pulse width calculation formula, the generated pulse width is 0.833ns, the pulse width is the same as that of a Modelsim simulation result, and the minimum resolution simulation is correct.

When the counting values are all set to be 6, the simulation waveform is shown in fig. 9, the pulse width value calculated by using the Modelsim scale is 4.998ns, and according to the pulse width calculation formula, when the initial counting values are all 6, the output pulse width is 4.998ns, the result is completely consistent, and the experimental pulse width modulation functional verification result is correct.

Next, the pulse signal actually generated by the FPGA was tested using an oscilloscope. The FPGA uses Altera's EP4CE15F23C8 chip. The model of the oscilloscope is the crossflow DL9240, the analog bandwidth is 1.5GHz, and the highest real-time sampling rate is 10 GSa/s. Fig. 10 and 11 show waveforms of signals with set widths of 0.833ns and 4.998ns, respectively, each cell representing a time of 5ns, and the actual pulse signals shown in the figures are matched with the set values by measuring the widths of the effective portions of the pulse signals. The results of the oscilloscope show that the pulse generator realizes nanosecond pulse signal generation and pulse width modulation.

Through the analysis of the experimental data, the performances of the dual-channel synchronous reloading pulse generation method and other narrow pulse generation methods are shown in table 3.

TABLE 3 Dual-channel synchronous reloading pulse generation method and other methods for generating pulse parameters

The direct counting method is that the frequency of an external crystal oscillator is multiplied by using an internal phase-locked loop of the FPGA, the frequency is used as a counting clock for counting, at least 1GHz stable working frequency is needed for generating a pulse signal with the resolution of 1ns, and the general FPGA obviously cannot meet the requirement. The coding and decoding generation method of the pulse utilizes only 1 and 0 states of the pulse signal, the pulse signal is cut in the form of time slices, and the pulse state of each time slice is represented by a one-bit binary number. And the binary sequence data is sent to the FPGA through the upper computer to generate a corresponding pulse signal. However, the minimum time slice accuracy of the encoding and decoding is limited by the working frequency of the FPGA, and it is difficult to realize higher resolution.

In addition, the double-triode parallel circuit generates a pulse signal with larger amplitude but larger pulse width by utilizing an avalanche effect generated by the parallel connection of an LC circuit damping principle and the double radio frequency triodes. Although the double not gate structure design for realizing narrow pulse generation by utilizing the competition hazard of the digital logic device generates an extremely narrow pulse signal, the pulse width of the double not gate structure design is limited by the circuit design and cannot be adjusted.

The direct counting method and the coding and decoding generation method of the pulse improve the minimum resolution by improving the working frequency of the FPGA. The working frequency of a common FPGA is generally within 500MHz, and the minimum resolution of pulse width modulation is not less than 2 ns. Different from the principle, the double-channel synchronous complex loading pulse generation method is characterized in that under the limited FPGA working frequency, the double-channel synchronous complex loading counting module is used for respectively counting 48MHz clock signals and 50MHz clock signals with similar frequencies and generating indication signals. The indication signals of the two channels will generate a phase difference due to the vernier effect. The equivalent working frequency of the narrow pulse generated by the phase difference can reach more than 1GHz, and is irrelevant to the maximum working frequency of the FPGA, so that the nanosecond pulse resolution of 0.833ns can be finally achieved. Moreover, the design of the double-triode parallel circuit with the non-adjustable 0.833ns minimum pulse width contrast pulse width of the double-channel synchronous reloading pulse generation method still has remarkable advantages. The double-NOT gate structure design can generate a narrow pulse signal with the minimum pulse width of 0.15ns, but after the circuit design is completed, the pulse width cannot be adjusted, and the application is difficult. The method not only realizes the generation of the narrow pulse signal of 0.833ns, but also realizes the pulse width adjustment precision of 0.833 ns.

Furthermore, it should be noted that in the present specification, "include" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed, or further includes elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should take the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments understood by those skilled in the art.

Claims

1. A double-channel synchronous reloading pulse generation method is characterized by comprising a clock generation module, a synchronous reloading counting module and a signal edge triggering module, and comprises the following steps:

2. The dual channel synchronous multiple loading pulse generating method of claim 1, wherein: the step 1) is that the clock generation module generates two clock signals CLK A and CLK B with similar frequencies and a loading signal LOAD with 1 MHz.

3. The dual channel synchronous multiple loading pulse generating method of claim 1, wherein: the step 2) synchronous reloading counting module comprises a first channel reload _ a and a second channel reload _ B, the first channel reload _ a and the second channel reload _ B respectively count respective input clock pulses, and the count values are respectively input a _ Value and B _ Value.

4. The dual channel synchronous multiple loading pulse generating method according to claim 2 or 3, characterized in that: the clock signal CLK A is used as a counting clock of a first channel Reloader _ A of the synchronous reloading counting part; the clock signal CLK B is used as the counting clock of the second channel reload _ B.

5. The dual channel synchronous multiple loading pulse generating method according to claim 2 or 3, characterized in that: when the rising edge of the LOAD signal LOAD clock signal arrives, a _ Value and B _ Value are synchronously loaded into the two counting channels again, and the next round of counting is restarted.

6. The dual channel synchronous multiple loading pulse generating method of claim 5, wherein: when the counting Value reaches the loaded counting Value A _ Value or B _ Value each time, the corresponding counting channel generates an indication Signal, the indication Signal generated by the first channel Reloader _ A is an SET Signal, the indication Signal generated by the second channel Reloader _ B is a RESET Signal, and due to different counting clock frequencies, a phase difference exists between the generated SET Signal rising edge and the RESET Signal rising edge, and the output Signal level is triggered to overturn at the SET Signal rising edge and the RESET Signal rising edge, so that a transient pulse Signal with adjustable pulse width is generated.

7. The dual channel synchronous multiple loading pulse generating method of claim 1, wherein: the LOAD signal continuously LOADs the counting values of the two channels synchronously and repeatedly, and the pulse signal continuously appears at a certain frequency to realize pulse generation.

8. The dual channel synchronous multiple loading pulse generating method of claim 1, wherein: the clock generation module uses a single phase locked loop and generates the best clock signals as 48MHz and 50 MHz.

9. The dual channel synchronous multiple loading pulse generating method of claim 1, wherein: the reloading counting module is designed by a register state, and the state of the state machine is controlled by the input RELOAD signal and the count value cnt.

10. The dual channel synchronous multiple loading pulse generating method of claim 1, wherein: the signal edge triggering module is composed of a basic logic gate and a latch, and the latch respectively latches a signal state and an output signal q.