CN100583641C - Digital tracking method of synchronous phase angle - Google Patents

Abstract

This invention relates to simultaneous phase angle digital tracing method in the relative technique field and is characterized by the following: first inputting the simultaneous signals into radio measurement circuit to get the frequency division of outer crystal clock of CI and plug parameters of CR; then using the CI, CR as frequency division values input to the plug and division circuit.

Description

A kind of digital tracking method of synchronous phase angle

Technical field

The present invention relates to a kind of digital tracking method of synchronous phase angle, this method can be carried out accurate frequency and Phase Tracking to the square wave synchronizing signal of input, produces accurate 0.01 electrical degree synchronization pulse output, belongs to the Phase Tracking technical field.

Background technology

In the control field of electrical engineering, devices such as static reacance generator, active filter, dynamic electric voltage recovery device for example, various control procedures need accurate frequency and phase place of following the tracks of line voltage usually.Development along with digital signal processor (hereinafter to be referred as DSP) and programmable gate array (hereinafter to be referred as FPGA), full-digital control has become inexorable trend, and it is very necessary that the frequency of line voltage and phase place are carried out the numeral output that exact figure followed the tracks of and obtained synchronous phase angle.

Need carry out in the synchronous numerical control system line voltage, normally adopt the method for digital phase-locked loop, as being recorded and narrated in 01804819.6 the patent of invention " digital phase-locked loop ", realize that existing digital phase-locked loop needs to produce by digital phase discriminator earlier the phase error signal of locked signal and lockin signal, by phase error being carried out lowpass digital filter and digital controlled oscillator obtains synchronizing frequency doubling signal, synchronizing frequency doubling signal obtains lockin signal by frequency division again and constitutes feedback control loop again.

Realization to existing digital phase-locked loop need comprise a plurality of links such as digital phase discriminator, digital filter, digital controlled oscillator and feedback divider, implement more complicated, and wherein the parameter designing and the transfer function analysis of lowpass digital filter all compare difficulty.Need carry out in the synchronous numerical control system line voltage,,,, needs occupied bigger system resource if in FPGA, digital phase-locked loop is realized with increasing the complexity and the cost of Control System Design if adopt the digital phase-locked loop chip.

Summary of the invention

The objective of the invention is to propose a kind of digital tracking method of synchronous phase angle.

The digital tracking method of the synchronous phase angle that the present invention proposes comprises following each step:

Step 1: the square wave synchronizing signal is input to frequency measurement circuit, obtains the frequency division multiple C of external crystal-controlled oscillation clock signal _IWith interpolation coefficient C _R, described step 1 contains following steps successively:

Step 1.1: described frequency measurement circuit at the rising edge of square wave synchronizing signal with frequency division multiple C _IWith interpolation coefficient C _RAll zero clearings;

Step 1.2: at the described square wave synchronizing signal of step 1.1 rising edge, to described frequency measurement circuit input external crystal-controlled oscillation clock signal, and 360 external crystal-controlled oscillation clock cycle of every mistake are described interpolation coefficient C _RIncrease progressively 1, obtain:

$C_R=\mathrm{INT}[100\×\mathrm{RES}\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)]$

Wherein, T ₁Be described square wave synchronous signal cycle;

T _CLKBe the cycle of described external crystal-controlled oscillation clock;

INT is a bracket function;

RES gets the remainder function

Step 1.3: whenever interpolation coefficient C _RAfter being incremented to 100, described C _RZero clearing, and frequency division multiple C _IIncrease progressively 1, obtain

$C_I=\mathrm{INT}\left[\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)\right];$

Step 1.4: when the next rising edge of described square wave synchronizing signal arrives, the frequency division multiple C of this moment _IWith interpolation coefficient C _RLatch output as frequency measurement circuit;

Step 1.5: return step 1, enter next square wave synchronizing signal processing procedure;

Step 2: with frequency division multiple C _I, interpolation coefficient C _RAs the frequency division counter controlling value, input interpolation counting frequency dividing circuit described external crystal-controlled oscillation clock division, obtains the pulse signal that the average clock cycle is 0.01 electrical degree, and described step 2 contains following steps again successively:

Step 2.1: described interpolation counting frequency dividing circuit is according to the frequency division multiple C of input _I, interpolation coefficient C _RObtain following counting controlling value:

C _I1＝C _I

C _I2＝C _I+1

C _R1＝100-C _R

C _R2＝C _R

Step 2.2: described interpolation counting frequency dividing circuit carries out C to outside crystal oscillator clock signal _I1Frequency division doubly obtains the output pulse of interpolation counting frequency dividing circuit, until exported C _R1Individual pulse;

Step 2.3: outside crystal oscillator clock signal is carried out C _I2Times frequency division obtains the output pulse signal of interpolation counting frequency dividing circuit, until exported C _R2Individual pulse;

Step 2.4: repeating step 2.2～2.3 obtains the pulse signal that the average clock cycle is 0.01 electrical degree.

The digital tracking method of the synchronous phase angle that the present invention proposes can obtain can both accurately following the tracks of 0.01 electrical degree synchronization pulse of input square wave synchronizing signal on frequency and phase place.With respect to existing digital phase-locked loop method, the present invention only needs frequency measurement circuit and two links of interpolative divide circuit, has simplified significantly the synchronization signal processing process.Adopt the method for interpolative divide to eliminate the time error that method is brought that the frequency division multiple is simply rounded.Frequency measurement circuit and interpolative divide circuit cooperatively interact, and a shared external crystal-controlled oscillation clock makes measurement result and external crystal-controlled oscillation clock frequency irrelevant, has improved versatility, has also eliminated the influence that the external clock trueness error is brought simultaneously.Method of the present invention is not limited only to obtain the synchronization pulse of 0.01 electrical degree, if change the count parameter of frequency measurement circuit, adopts method of the present invention can obtain the corresponding synchronization pulse of electrical degree arbitrarily.

Method simplicity of design of the present invention, accuracy height can be very easy be realized in FPGA, also can be applied in the special-purpose design of integrated circuit.Application of the present invention is applicable to and need carries out in the numerical control system of accurate measurement and tracking electric network voltage phase.Method of the present invention is not limited only to the line voltage locking phase is followed the tracks of, in the occasion that also can be applied to other frequency signal is measured.

Description of drawings

Fig. 1 is the theory diagram of existing digital phase-locked loop method.

Fig. 2 is the theory diagram of the synchronous phase angle digital tracking method that proposes of the present invention.

Fig. 3 be in the embodiment of the invention when the line voltage fixed-frequency is 50.00Hz, the 0.01 electrical degree synchronization pulse schematic diagram that obtains.

During Fig. 4 in the embodiment of the invention with 0.01 electrical degree synchronization pulse as the phase angle synchronization accumulator clock input obtain the schematic diagram of 16 bit digital synchronous phase angles.

Embodiment

The digital tracking method of the synchronous phase angle that the present invention proposes comprises following each step: below in conjunction with description of drawings.

The theory diagram of synchronous phase angle digital tracking method of the present invention as shown in Figure 2.Input of the present invention is a square wave synchronizing signal, and its rising edge and line voltage positive going zeror crossing point are synchronous, and the time between two rising edges is exactly line voltage power frequency period T ₁For the synchronous phase angle signal that makes output and the frequency precise synchronization of line voltage, need at first adopt the external crystal-controlled oscillation clock signal that the frequency of square wave synchronizing signal is carried out numeral and follow the tracks of.A power frequency period T ₁Corresponding 360 electrical degrees in the present invention, are utilized pairing time of 0.01 electrical degree and external crystal-controlled oscillation clock cycle T _CLKRatio as frequency measurement sign amount.Because pairing time of 0.01 electrical degree and external crystal-controlled oscillation clock cycle T _CLKRatio may be non-integer, can only realize integral multiple counting and make, so proposed among the present invention with frequency division multiple C in Digital Implementation _IWith interpolation coefficient C _RCharacterize pairing time of 0.01 electrical degree and external crystal-controlled oscillation clock cycle T jointly _CLKThe method of ratio, promptly

$C_I=\mathrm{INT}\left[\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)\right]$

$C_R=\mathrm{INT}[100\×\mathrm{RES}\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)]$

In the following formula, INT is a bracket function, and RES gets the remainder function.

According to above two formulas, power frequency period T ₁, external crystal-controlled oscillation clock cycle T _CLK, frequency division multiple C _IWith interpolation coefficient C _RRelation between coming can be written as

T ₁＝100×C _I×360×T _CLK+C _R×360×T _CLK

If 0.01 degree pairing time of electrical degree was T ₀₀₁, T then ₀₀₁For

$T_{001}=\frac{T_1}{36000}=C_I\×T_{\mathrm{CLK}}+\frac{C_R\×T_{\mathrm{CLK}}}{100}$

Frequency measurement circuit be exactly the input two adjacent rising edges of square wave synchronizing signal between by the counting method obtain frequency division multiple C _IWith interpolation coefficient C _ROutput.According to following formula, concrete implementation is as follows, at first at the rising edge of square wave synchronizing signal with frequency division multiple C _IWith interpolation coefficient C _RAll zero clearings: 360 external crystal-controlled oscillation clock cycle of every then mistake are with C _RIncrease progressively 1; Whenever C _RAfter being incremented to 100, with C _RZero clearing, and with C _IIncrease progressively 1; When the next rising edge of square wave synchronizing signal comes then, with the C of this moment _IAnd C _RLatch and as the output of frequency measurement circuit, and repeat above process simultaneously.

The output frequency division multiple C of frequency measurement circuit _IWith interpolation coefficient C _RTo be used to control the frequency division multiple to outside crystal oscillator clock signal as the input of interpolative divide circuit, be 0.01 electrical degree time pulse signal to produce average period.Because pairing time of 0.01 electrical degree and external crystal-controlled oscillation clock cycle T _CLKBetween multiple may be non-integer, if simply when frequency division adopt the numerical value after rounding will bring, so introduced the notion of interpolative divide among the present invention than mistake as the frequency division multiple.

Obtain the several Control value at first by the following method

C _I1＝C _I

C _I2＝C _I+1

C _R1＝100-C _R

C _R2＝C _R

Then, in per 100 0.01 electrical degree lock-out pulses, preceding C _R1C is adopted in individual pulse _I1As frequency division multiple, then C _R2C is adopted in individual pulse _I2As the frequency division multiple.Shu Chu 0.01 electrical degree lock-out pulse T average period like this ₀₀₁For

$T_{001\_\mathrm{AV}}=\frac{C_{R1}\×C_{I1}\×T_{\mathrm{CLK}}+C_{R2}\×C_{I2}\×T_{\mathrm{CLK}}}{100}=C_I\×T_{\mathrm{CLK}}+\frac{C_R\×T_{\mathrm{CLK}}}{100}$

Promptly

$T_{001\_\mathrm{AV}}=T_{001}=\frac{T_1}{36000}$

The 0.01 electrical degree lock-out pulse that is to say output promptly is 0.01 electrical degree time of power frequency period accurately average period.Adopt this synchronization pulse, resulting digital synchronous phase angle precision can reach the .01 electrical degree.

Adopt the method for interpolative divide to eliminate traditional time error that method is brought that the frequency division multiple is simply rounded.Designed frequency measurement circuit and interpolative divide circuit cooperatively interact, and a shared external crystal-controlled oscillation clock makes measurement result and external crystal-controlled oscillation clock frequency irrelevant, has improved versatility, has also eliminated the influence that the external clock trueness error is brought simultaneously.

In an embodiment who realizes with FPGA of the present invention, the square wave synchronous signal frequency of input is 50.00HZ, i.e. T ₁=20ms, the external crystal-controlled oscillation clock frequency is 50.000MHZ, i.e. T _CLK=20ns, frequency measurement circuit is output as like this

$C_I=\mathrm{INT}\left[\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)\right]=27$

$C_R=\mathrm{INT}[100\×\mathrm{RES}\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)]=78$

Like this in the interpolative divide circuit, as shown in Figure 3, in 100 the 0.01 electrical degree synchronization pulses of every generation, preceding 22 pulsion phases pair are 27 with the frequency division multiple of external clock crystal oscillator signal, then 78 pulsion phases pair are 28 with the frequency division multiple of external clock crystal oscillator signal, the output that so hockets, be the average period of such 0.01 electrical degree lock-out pulse

$T_{001\_\mathrm{AV}}=\frac{22\×27\×T_{\mathrm{CLK}}+78\×28\×T_{\mathrm{CLK}}}{100}=27.78\×T_{\mathrm{CLK}}$

For resulting 0.01 electrical degree synchronization pulse, can be with its synchronous base clock as numerical control system.In the embodiment of the invention as shown in Figure 4,,, triggering synchronous phase angle counter is increased progressively 1 at its rising edge of a pulse with its clock input as the phase angle summation circuit; And the square wave synchronizing signal is imported as the zero clearing of phase angle summation circuit, and its rising edge makes zero triggering synchronous phase angle counter.Such locking phase parallactic angle numeral output to the end, its digital output area is 0～35999, corresponding to actual electrical angle 0.00～359.99 degree, can be with one 16 data representation.

Claims (1)

1, a kind of digital tracking method of synchronous phase angle is characterized in that, it realizes that in a digital private integrated circuit (IC)-components it contains following each step successively:

Step 1: the square wave synchronizing signal is input to frequency measurement circuit, obtains the frequency division multiple C of external crystal-controlled oscillation clock signal _IWith interpolation coefficient C _R, described step 1 contains following steps successively:

Step 1.1: described frequency measurement circuit at the rising edge of square wave synchronizing signal with frequency division multiple C _IWith interpolation coefficient C _RAll zero clearings;

Step 1.2: at the described square wave synchronizing signal of step 1.1 rising edge, to described frequency measurement circuit input external crystal-controlled oscillation clock signal, and 360 external crystal-controlled oscillation clock cycle of every mistake are described interpolation coefficient C _RIncrease progressively 1, obtain:

$C_R=\mathrm{INT}[100\×\mathrm{RES}\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)]$

Wherein, T ₁Be described square wave synchronous signal cycle;

T _CLKBe the cycle of described external crystal-controlled oscillation clock;

INT is a bracket function;

RES gets the remainder function

Step 1.3: whenever interpolation coefficient C _RAfter being incremented to 100, described C _RZero clearing, and frequency division multiple C _IIncrease progressively 1, obtain:

$C_I=\mathrm{INT}\left[\left(\frac{T_1/36000}{T_{\mathrm{CLK}}}\right)\right];$

Step 1.4: when the next rising edge of described square wave synchronizing signal arrives, the frequency division multiple C of this moment _IWith interpolation coefficient C _RLatch output as frequency measurement circuit;

Step 1.5: return step 1, enter next square wave synchronizing signal processing procedure;

Step 2: with frequency division multiple C _I, interpolation coefficient C _RAs the frequency division counter controlling value, input interpolation counting frequency dividing circuit described external crystal-controlled oscillation clock division, obtains the pulse signal that the average clock cycle is 0.01 electrical degree, and described step 2 contains following steps again successively:

Step 2.1: described interpolation counting frequency dividing circuit is according to the frequency division multiple C of input _I, interpolation coefficient C _RObtain following counting controlling value:

C _I1＝C _I

C _I2＝C _I+1

C _R1＝100-C _R

C _R2＝C _R

Step 2.2: described interpolation counting frequency dividing circuit carries out C to outside crystal oscillator clock signal _I1Frequency division doubly obtains the output pulse of interpolation counting frequency dividing circuit, until exported C _R1Individual pulse;

Step 2.3: outside crystal oscillator clock signal is carried out C _I2Times frequency division obtains the output pulse signal of interpolation counting frequency dividing circuit, until exported C _R2Individual pulse;

Step 2.4: repeating step 2.2～2.3 obtains the pulse signal that the average clock cycle is 0.01 electrical degree.

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