CN102158205B

CN102158205B - Clock frequency multiplier, device and clock frequency multiplication method

Info

Publication number: CN102158205B
Application number: CN201110060332.5A
Authority: CN
Inventors: 于航; 杨旭
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2011-03-14
Filing date: 2011-03-14
Publication date: 2014-03-12
Anticipated expiration: 2031-03-14
Also published as: CN102158205A

Abstract

The invention discloses a clock frequency multiplier, a clock frequency multiplication device and a clock frequency multiplication method. The clock frequency multiplier comprises a pulse generator, a phase shifter, a phase synthesizer and a frequency divider, wherein the pulse generator is used for regulating an external input clock signal into an equal periodic pulse clock signal; the phase shifter is used for performing phase shifting on the input equal periodic pulse clock signal for different time lengths according to a required frequency multiplication fold and a clock cycle to obtain phase shifted clock signals; the phase synthesizer is used for performing phase synthesis on the equal periodic pulse clock signal and each phase shifted clock signal to obtain a frequency multiplied clock signals; and the frequency divider is used for performing frequency division on the phase-synthesized frequency multiplied clock signal to obtain a frequency multiplied output clock signal, and outputting the frequency multiplied output clock signal. By the clock frequency multiplier, the clock frequency multiplication device and the clock frequency multiplication method, the frequency multiplication of the clock signal is realized under the condition of no phase-locked loops, and/or normal operations can be realized under the condition of radiation exposure.

Description

A kind of clock multiplier and device and clock frequency-doubling method

Technical field

The invention belongs to the integrated circuit of frequency synthesizer class, be specifically related to a kind of clock multiplier and device and clock frequency-doubling method, more specifically, relate to a kind of clock multiplier for anti-irradiation integrated circuit and device and clock frequency-doubling method.

Background technology

At present, clock multiplier is widely used in integrated circuit, in prior art, generally adopt phase-locked loop (PLL) as clock multiplier to increase the frequency of input clock signal.But phase-locked loop structures designs too complexity and poor stability, and the anti-radiation performance of the loop of whole phase-locked loop is poor, under radiation irradiation condition, easily there is mistake.

And existing frequency doubling technology, has adopted counter or shift register etc. as status register mostly, this status register is when running into radiation irradiation, trigger wherein may overturn, and causes logic error, thereby the cycle of final clock output signal is changed.

Summary of the invention

The object of the present invention is to provide a kind of clock multiplier and device and clock frequency-doubling method, in fact do not have now to realize the frequency multiplication of clock signal in the situation of phase-locked loop, and/or can under the condition of radiation irradiation, work.

For realizing object of the present invention, provide a kind of clock multiplier, comprising:

Pulse generator, for becoming isoperimetric phase pulse clock signal by outside input clock signal adjustment;

Phase shifter, for according to required frequency and clock cycle, the cycle pulse clock signal such as described of input being carried out to the phase shift of different time, obtains phase shift clock signal;

Phase synthesizer, for waiting cycle pulse clock signal and carried out phase place by each phase shift clock signal after phase shift and synthesize described, obtains frequency doubling clock signal;

Frequency divider, for the frequency doubling clock signal being carried out after phase place is synthesized is carried out to frequency division, obtains frequency multiplication clock signal output;

Described phase shifter comprises two-divider, clock cycle measuring appliance and digital control delayer;

Two-divider, for using described cycle pulse clock signal such as grade as input signal, processes and obtains the clock signal that a clock high level equated with the cycle of described cycle pulse clock signal such as grade;

Clock cycle measuring appliance, converts digital controlled signal to for the clock signal that two-divider is produced, and is sent to the input of digital control delayer;

Digital control delayer, for the control of the digital controlled signal by obtaining from clock cycle measuring appliance, produce to postpone, and the cycle pulse clock signal such as described is carried out to delay disposal, at output, obtains phase shift clock signal.

More preferably, described pulse generator comprises a plurality of NOT logic doors, two input exclusive or logic gates, two input NAND Logic doors;

In pulse generator inside, there are two clock signal paths:

Article one, clock signal path is that outside input clock signal is transferred to the A input of two input exclusive or logic gates and the A input of two input NAND Logic doors;

Second clock signal path is first a plurality of NOT logic door inputs and output to be joined end to end, and the input after connecting is connected with outside input clock signal end, and output is connected with the B input of two input exclusive or logic gates; The output of two input exclusive or logic gates is connected with the B input of two input NAND Logic doors, and the output of two input NAND Logic doors is to wait cycle pulse clock signal end.

More preferably, described two-divider comprises NOT logic door and D type flip-flop;

The input end of clock CK of D type flip-flop is as the input of two-divider; The input of the output Q NAND Logic door of D type flip-flop is connected;

The output of NOT logic door is connected with the data input pin D of D type flip-flop, and the while is as the output of two-divider.

More preferably, described clock cycle measuring appliance is composed in series by a plurality of clock cycle measuring units;

The IN input of first clock cycle measuring unit is connected with two-divider;

The OUT output of last clock cycle measuring unit is unsettled.

More preferably, described clock cycle measuring unit, comprises 4 two input NAND Logic doors, 1 NOT logic door and 1 D type flip-flop;

The A input of first two inputs NAND Logic door is as the IN input of described clock cycle measuring unit, and B input is connected with high level, and output is connected with the A input of second two input NAND Logic door;

The B input of second two input NAND Logic door is connected with high level, and output is connected with the A input of the 3rd two input NAND Logic door;

The B input of the 3rd two input NAND Logic door is connected with high level, and output is connected with the A input of the 4th two input NAND Logic door;

The B input of the 4th two input NAND Logic door is connected with the CK input of described clock cycle measuring unit, and output is connected with the D input of D type flip-flop, and the while is as the OUT output of this clock cycle measuring unit;

The input of NOT logic door is as the CK input of described clock cycle measuring unit, and output is connected with the CK input of D type flip-flop;

The Q output of D type flip-flop is as the Q output of this clock cycle measuring unit.

More preferably, described digital control delayer is comprised of a plurality of digital control delay cell;

The control input end of wherein said digital control delay cell is Qn, and the clock signal input terminal of described digital control delay cell is LI and RI, and the clock signal output terminal of described digital control delay cell is LO and RO;

Described digital control delay cell is divided into three groups, one group of each behavior, and the connected mode of each group is identical;

For every a line, first digit control lag unit R O output is connected with second digit control lag unit LI input, and first digit control lag unit R I input is connected with second digit control lag unit LO output;

Second digit control lag unit R O output is connected with third digit control lag unit LI input, and second digit control lag unit R I input is connected with third digit control lag unit LO output; By that analogy;

Last digital control delay cell RO output is connected with the RI input of self.

More preferably, described digital control delay cell is comprised of 3 two input NAND Logic doors and 1 NOT logic door;

The input of NOT logic door, as the Q input of described digital control delay cell, is connected with the B input of the one or two input NAND Logic door simultaneously; The output of NOT logic door is connected with the B input of the two or two input NAND Logic door;

The A input of the one or two input NAND Logic door is connected with the A input of the two or two input NAND Logic door, and the while is as the LI input of described digital control delay cell; The output of the one or two input NAND Logic door is as the RO output of described digital control delay cell;

The output of the two or two input NAND Logic door is connected with the B input of the three or two input NAND Logic door; The A input of the three or two input NAND Logic door is as the RI input of described digital control delay cell; The output of the three or two input NAND Logic door is as the LO output of described digital control delay cell.

More preferably, described phase synthesizer 3 comprises a plurality of two input NOR-logic doors, and two input NAND Logic doors;

The A input of described two input NOR-logic doors is as the input of phase shift clock signal, and B input is as the input of another clock signal, and output is connected with the A input of two input NAND Logic doors;

The output of two input NAND Logic doors is as the output of frequency doubling clock signal.

For realizing the object of the invention, also provide a kind of clock cycle measuring unit, comprise 4 two input NAND Logic doors, 1 NOT logic door, 3 D type flip-flop and 1 three input NAND Logic door;

The B input of the 4th two input NAND Logic door is connected with the CK input of described clock cycle measuring unit, and the output while is connected with the D input of three D type flip-flop, and as the OUT output of described clock cycle measuring unit;

The input of NOT logic door is as the CK input of described clock cycle measuring unit, and output is connected with the CK input of three D type flip-flop simultaneously;

The Q output of three D type flip-flop is connected through A, B, the C input of a NOT logic Men Yusan input NAND Logic door respectively;

Three input NAND Logic doors are as the Q output of this clock cycle measuring unit.

For realizing the object of the invention, also provide a kind of two input NAND Logic gate means, by 4 N type field-effect transistors and 4 P type field-effect transistors, formed;

N type field effect transistor substrate meets VSS, and P type field effect transistor substrate meets VDD;

The grid of P type field effect transistor M 1 and M7, the grid of N type field effect transistor M 2 and M3 is connected with A input signal jointly;

The grid of P type field effect transistor M 5 and M8, the grid of N type field effect transistor M 4 and M6 is connected with B input signal jointly;

The source electrode of P type field effect transistor M 1 is connected with VDD, and drain electrode is connected with the source electrode of N type field effect transistor M 3 with the drain electrode of N type field-effect transistor W2.

More preferably, the source electrode of described N type field effect transistor M 2 is connected with VSS, and the drain electrode of N type field effect transistor M 3 is connected with the source electrode of N type field effect transistor M 4;

The drain electrode of described N type field effect transistor M 4 is connected with the drain electrode of P type field effect transistor M 5, the source electrode of N type field effect transistor M 6;

The source electrode of P type field-effect transistor W5 is connected with VDD;

The drain electrode of N type field effect transistor M 6 is connected with the drain electrode of P type field effect transistor M 7 and M8, as output;

The source electrode of P type field effect transistor M 7 and M8 is connected with VDD.

For realizing the object of the invention, also provide a kind of NOT logic gate means, by 2 N type field-effect transistors and 2 P type field-effect transistors, formed;

Described N type field effect transistor substrate meets VSS, and P type field effect transistor substrate meets VDD, and the grid of all field-effect transistors is connected with IN input signal.

More preferably, the source electrode of described P type field effect transistor M 1 is connected with VDD, and drain electrode is connected with the source electrode of N type field effect transistor M 4 with the drain electrode of N type field effect transistor M 2;

The source electrode of described N type field effect transistor M 2 is connected with VSS;

The source electrode of described P type field effect transistor M 3 is connected with VDD, and drain electrode is connected with OUT output signal with the drain electrode of N type field effect transistor M 4.

For realizing the object of the invention, also provide a kind of N type field-effect transistor, the grid of described N type field-effect transistor is ring-shaped gate.

For realizing the object of the invention, more provide a kind of clock multiplier method, comprising:

Outside input clock signal adjustment is become to the step of isoperimetric phase pulse clock signal;

Phase shifter carries out the phase shift of different time according to required frequency and clock cycle to the cycle pulse clock signal such as described of input, obtains the step of phase shift clock signal;

By described, wait cycle pulse clock signal and by each phase shift clock signal after phase shift, carried out phase place and synthesize, obtaining the step of frequency doubling clock signal;

The frequency doubling clock signal being carried out after phase place is synthesized is carried out to frequency division, obtain the step of frequency multiplication clock signal output;

More preferably, described outside input clock signal adjustment is become to isoperimetric phase pulse clock signal, comprise the steps:

Outside input clock signal, from the input input of pulse generator, produces by pulse generator waiting cycle pulse clock signal and being sent to phase shifter of equating with input clock signal frequency.

More preferably, the described cycle pulse clock signal that waits to input carries out the phase shift of different time, comprises the steps:

Phase shifter carries out phase shifts to the described cycle pulse clock signal that waits, producing with the described phase difference that waits cycle pulse clock signal is respectively four phase shift clock signal: CK_0, CK_90, CK_180 and CK_270 of 0 °, 90 °, 180 ° and 270 °, and is sent to phase synthesizer.

More preferably, described by waiting cycle pulse clock signal and being carried out phase place by each phase shift clock signal after phase shift and synthesize, comprise the steps:

Phase synthesizer synthesizes a quadruple clock signal C K_4T by inputted phase shift clock signal CK_0, CK_90, CK_180 and CK_270, and sends it to frequency divider; The frequency of described quadruple clock signal C K_4T is described four times of waiting cycle pulse clock signal frequency.

More preferably, the described frequency doubling clock signal that quilt is carried out after phase place is synthesized carries out frequency division, comprises the steps:

Frequency divider 4 carries out respectively 4 frequency divisions and 2 frequency divisions by described quadruple clock signal C K_4T, produces frequency multiplication clock signal CK_OUT1 and CK_OUT2, and finally exports it to microprocessor.

The invention has the beneficial effects as follows: clock multiplier of the present invention and clock multiplier method can realize the frequency multiplication of clock signal in the situation that there is no phase-locked loop, and can access the frequency-doubled signal of 50% duty ratio.There is not feedback loop in this circuit, increase dynamic sampling Redundancy Design simultaneously, and the probability making a mistake under the condition of radiation irradiation is less, can work.

Accompanying drawing explanation

Fig. 1 is the structural representation of the clock multiplier of a specific embodiment of the present invention;

Fig. 2 is each clock signal sequential chart of clock multiplier of the embodiment of the present invention in Fig. 1;

Fig. 3 is pulse clock generator electrical block diagram in Fig. 1;

Fig. 4 is pulse clock generator internal node sequential chart in Fig. 3;

Fig. 5 is phase shifter circuit structural representation in Fig. 1;

Fig. 6 is two-divider electrical block diagram in Fig. 5;

Fig. 7 is clock cycle measuring appliance electrical block diagram in Fig. 5;

Fig. 8 is clock cycle measuring unit electrical block diagram in Fig. 7;

Fig. 9 is the sequential chart of clock cycle measuring appliance in Fig. 7;

Figure 10 is digital control delayer electrical block diagram in Fig. 5;

Figure 11 is digital control delay unit circuit structural representation in Figure 10;

Figure 12 is the phase synthesizer electrical block diagram in Fig. 1;

Figure 13 is a kind of improved clock cycle measuring unit electrical block diagram of the embodiment of the present invention two;

Figure 14 is a kind of NOT logic gate means electrical block diagram of the invention process three;

Figure 15 is a kind of two input NAND Logic gate means electrical block diagrams of the embodiment of the present invention three;

Figure 16 is a kind of N type field-effect transistor structure schematic diagram of the embodiment of the present invention four.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, clock multiplier of the present invention and device and clock frequency-doubling method are further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention rather than limitation of the present invention.

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Embodiment mono-: a kind of clock multiplier

As a kind of preferably embodiment, because memory cell and the computing unit of some microprocessor adopts different clock zones, the clock source that therefore needs to comprise clock multiplier on a sheet produces the good clock signal of duty ratio of different frequency.Therefore, in embodiments of the present invention, with the clock multiplier of the embodiment of the present invention and device and clock frequency-doubling method to be applied in No. 1 microprocessor of Godson, external crystal-controlled oscillation signal provides the clock signal of frequency 50 ~ 100MHz for circuit, simultaneously duty ratio is not desirable 50%, after process of frequency multiplication, producing two frequency doubling clock signals is that example is elaborated.

But, should be noted that, clock multiplier of the present invention and device and clock frequency-doubling method, also can be applicable in other various large scale integrated circuits, the input pulse signal of the hateful different frequency providing according to outside, different duty, through process of frequency multiplication produce four times, six times, octuple ... the clock signal of different frequencys multiplication.It will be understood by those skilled in the art that the embodiment of the present invention is not limitation of the present invention, also just in order to make those skilled in the art understand better the present invention, the scope that the scope that the present invention asks for protection should limit with claims is determined.

A kind of clock multiplier of the embodiment of the present invention, as a kind of embodiment, as shown in Figure 1, comprising:

Pulse generator 1, for adjusting the input clock signal CLK_IN of external crystal-controlled oscillation (not shown) to become isoperimetric phase pulse clock signal CLK_P;

Phase shifter 2; for the cycle pulse clock signal CLK_P such as described of input being carried out to the phase shift of different time according to required frequency N and clock period T; obtain phase shift clock signal, the differing of phase shift clock signal be respectively T/2N, 2*T/2N ..., (2N-1) T/2N;

Preferably, the pulse duration of described cycle pulse clock signal CLK_P such as grade is T/4N-T/8N.

Phase synthesizer 3, for waiting cycle pulse clock signal CLK_P and carried out phase place by each pulse clock signal after phase shift synthetic by described;

Frequency divider 4, for the pulse clock signal being carried out after phase place is synthesized is carried out to frequency division, obtains the clock multiplier output signal of different frequencys multiplication.

As a kind of embodiment, the clock multiplier of the embodiment of the present invention, comprises pulse generator 1, phase shifter 2, phase synthesizer 3 and frequency divider 4;

Wherein the left end of above each module device is input, and right-hand member is output; The output of pulse generator 1 is connected with the input of phase shifter 2; The output of phase shifter 2 is connected with the input of phase synthesizer 3; The output of phase synthesizer 3 is connected with the input of frequency divider 4.

As a kind of embodiment; the input clock signal CK_IN that external crystal-controlled oscillation (not shown) provides, from the input input of pulse generator 1, produces by pulse generator 1 waiting cycle pulse clock signal CLK_P and being sent to phase shifter 2 of equating with input clock signal CK_IN frequency;

2 couples of described cycle pulse clock signal CLK_P that wait of phase shifter carry out phase shifts; produce phase difference with the described cycle pulse clock signal CLK_P of grade and be respectively four phase shift clock signal: CK_0, CK_90, CK_180 and CK_270 of 0 °, 90 °, 180 ° and 270 °, and be sent to phase synthesizer 3;

Phase synthesizer 3 synthesizes a quadruple clock signal C K_4T by inputted phase shift clock signal CK_0, CK_90, CK_180 and CK_270, and sends it to frequency divider 4; The frequency of described quadruple clock signal C K_4T is four times of described frequency such as the cycle pulse clock signal CLK_P of grade;

Frequency divider 4 carries out respectively 4 frequency divisions and 2 frequency divisions by described quadruple clock signal C K_4T, produces frequency multiplication clock signal CK_OUT1 and CK_OUT2, and finally exports them other module (not shown) of microprocessor internal to.1 times of the input clock signal CK_IN frequency that the frequency of wherein said frequency multiplication clock signal CK_OUT1 is described external crystal-controlled oscillation, 2 times of the input clock signal CK_IN frequency that the frequency of described frequency multiplication clock signal CK_OUT2 is described external crystal-controlled oscillation, the duty ratio of described clock signal C K_OUT1 and CK_OUT2 is 50% simultaneously.

The clock multiplier of the embodiment of the present invention, the impact that can produce integrated circuit for radiation environment, thereby affect stability and the correctness problem of circuit working, adopted digital loop free design, reduce its probability making a mistake in practical work process.

In the clock multiplier of the embodiment of the present invention shown in Fig. 1, the sequential chart of each signal as shown in Figure 2.

Wherein, the input signal that input clock signal CK_IN shakes and provides for outer component.

It Deng cycle pulse clock signal CLK_P, is the narrower clock signal of width being produced by pulse generator 1.The input signal CK_IN that its frequency provides with external crystal-controlled oscillation with phase place is identical.

Phase shift clock signal CK_0, CK_90, CK_180 and CK_270 produce the clock signal of sitting by phase shifter 2.The input clock signal CK_IN that its frequency provides with external crystal-controlled oscillation and by pulse generator 1, produced etc. cycle pulse clock signal CLK_P identical; Simultaneously the phase place of phase shift clock signal CK_0 and outer component shake the input clock signal CK_IN that provides and 1 generation of mountain pulse generator etc. cycle pulse clock signal CLK_P identical; The phase place of phase shift clock signal CK_90 is delayed 90 ° than the phase place of phase shift clock signal CK_0; The phase place of phase shift clock signal CK_180 is delayed 180 ° than the phase place of phase shift clock signal CK_0; The phase place of phase shift clock signal CK_270 is delayed 270 ° than the phase place of phase shift clock signal CK_0.

Quadruple clock signal C K_4T is the clock signal being produced by phase synthesizer 3.Its frequency be the input clock signal CK_IN that provides of external crystal-controlled oscillation and by pulse generator 1, produced etc. four times of cycle pulse clock signal CLK_P.

Frequency multiplication clock signal CK_OUT1 and CK_OUT2 are the final clock signals being produced by frequency divider 4.Wherein frequency multiplication clock signal CK_OUT1 and outer component shake the input clock signal CK_IN that provides and by pulse generator 1, produced etc. frequency and the phase place of cycle pulse clock signal CLK_P identical, and the frequency that duty ratio is 50 friend's frequency multiplication clock signal CK_OUT2 be the input clock signal CK_IN that provides of external crystal-controlled oscillation and by pulse generator 1, produced etc. 2 times of cycle pulse clock signal CLK_P, and duty ratio is 50%.

Describe the pulse generator 1 in Fig. 1 of the embodiment of the present invention below in detail

As a kind of embodiment, preferably, as shown in Figure 1, described pulse generator 1, for input clock signal CLK_IN is postponed, then signal and described input clock signal CLK_IN after postponing are entered to horizontal phasing control, thereby obtain waiting cycle pulse clock signal CLK_P.

As a kind of embodiment, the pulse generator 1 of the embodiment of the present invention, needs the cycles such as generation to have the pulse of certain width, as shown in Figure 3, as a kind of embodiment, is the circuit structure diagram of the pulse generator in Fig. 1 of the embodiment of the present invention.

As a kind of embodiment, in the embodiment of the present invention, described pulse generator 1 comprises three kinds of basic digital logic gate components, is respectively: a plurality of NOT logic doors 11, and two input exclusive or logic gate 12, two input NAND Logic doors 13.Pulse generator first postpones the default time input signal CLK_IN, the pulse signal high level width that the time of its delay equals to wish to get, then the signal after postponing and the first XOR of original signal, rear and non-, just can obtain waiting cycle pulse clock signal CLK_P.

Wherein above-mentioned each

gate

11,12,13 left ends are input, and right-hand member is output.In pulse generator inside, have two clock signal paths, article one clock signal path is that the input clock signal CK_IN directly external crystal-controlled oscillation being provided is transferred to the A input of two input exclusive or logic gates 12 and the A input of two input NAND Logic doors 13.Second clock signal path is first a plurality of NOT logic every inputs and output to be joined end to end; the input clock signal CK_IN end that input after connecting provides with external crystal-controlled oscillation is connected, and output is connected with the B input of two input exclusive or logic gates 12; The output of two input exclusive or logic gates 12 is connected with the B input of two input NAND Logic doors 13, and the output of two input NAND Logic doors 13 is to wait cycle pulse clock signal CLK_P end.

Below in conjunction with the sequential chart of Fig. 4, further describe the specific works process of the pulse generator 1 shown in Fig. 3.

As shown in Figure 4, the input clock signal CK_IN being provided by external crystal-controlled oscillation enters after pulse generator 1, first through a plurality of inputs and output, join end to end and produce the delay Td of a period of time after NOT logic door 11, through the clock signal postponing, be input to the A input of two input exclusive or logic gates 12, carry out xor operation with the original outer component input clock signal CK_IN providing that shakes, output at two input exclusive or logic gates 12 obtains the B input that an each cycle has the clock signal of two pulses and sends to two input NAND Logic doors 13, carry out NOT-AND operation with the original outer component input clock signal CK_IN providing that shakes, that the different pulse of input clock signal CK_IN phase place providing from original external crystal-controlled oscillation is provided above-mentioned each cycle and is had in the clock signal of two pulses, finally at the output of two input NAND Logic doors 13, obtain and the original outer component all cycle pulse clock signal CLK_P such as identical of the input clock signal CK_IN frequency that provides and phase place that shake.

In the pulse generator 1 of the embodiment of the present invention, end to end NOT logic door 11 sequences of input and output have determined the pulse duration of the pulse clock signal that finally obtains, and pulse duration is clock signal through the delay of NOT logic door sequence.The frequency that in NOT logic door sequence, the number of NOT logic door 11 finally need to obtain according to reality is determined, need to guarantee that pulse duration is enough wide, to guarantee the gate in subsequent conditioning circuit, correctly work, pulse duration can not be wide simultaneously, when phase place is synthetic, make a mistake avoiding, in embodiments of the present invention, real input signal frequency is 50 ~ 100MHz, be to be 10 ~ 20ns the clock cycle, cycle after quadruple is 2,5 ~ 5ns, pulse duration is set to 800 ~ 1000ps, be about maximum frequency-doubled signal minimum clock cycle 1/3 ~ 1/2.

Describe the phase shifter 2 of the embodiment of the present invention below in detail.

As shown in Figure 5, described phase shifter 2 for according to required frequency N and clock period T, the cycle pulse clock signal CLK_P such as described of input is carried out to the phase shift of different time, differs being respectively T/2N, 2*TDN ..., (2N-l) T/2N.

As a kind of embodiment, in order to make those skilled in the art can understand the present invention, in embodiments of the present invention, the phase shift that input pulse signal is realized to 1/4 cycle, 1/2 cycle and 3/4 cycle with phase shifter describes, but should be understood that, it is not the restriction to phase shifter of the present invention.The phase shifter of the embodiment of the present invention can be according to actual needs, differ be respectively T/2N, 2*T/2N ..., (2N-1) T/2N phase shift, and be not limited to the phase shift in 1/4 cycle, 1/2 cycle and 3/4 cycle.

As a kind of embodiment, the circuit structure of the phase shifter 2 shown in Fig. 1 as shown in Figure 5.

As shown in Figure 5, described phase shifter 2 comprises three parts, is respectively two-divider 21, clock cycle measuring appliance 22 and digital control delayer 23.

Wherein, the output of two-divider 21 is connected with the input of clock cycle measuring appliance 22, and the output of clock cycle measuring appliance 22 is connected with the input of digital control delayer 23 respectively.

Two-divider 21, for waiting cycle pulse clock signal CLK_P as input signal, processes and obtains the clock signal that a clock high level equated with the cycle of waiting cycle pulse clock signal CK_P.

Clock cycle measuring appliance 22, converts digital controlled signal to for the cycle pulse clock signal that waits that two-divider is produced, and is sent to the input of digital control delayer 23.

Digital control delayer 23, control for the digital controlled signal by obtaining from clock cycle measuring appliance 22, produce to postpone, and the cycle pulse clock signal CK_P such as described is carried out to delay disposal, at output, obtain phase shift clock signal CK_0, CK_90, CK_180 and CK_270.

The cycle pulse clock signal CLK_P that waits being produced by pulse generator 1 inputs to the input of two-divider 21 as input signal, input to the left input of digital control delayer 23 as input signal simultaneously.At the output of two-divider 21, obtaining cycle of waiting cycle pulse clock signal CK_P that a clock high level width produces with pulse generator 1 is the original outer component clock signal that cycle of the input clock signal CK_IN that provides equates of shaking.Clock cycle measuring appliance 22 converts described clock width and the original outer component cycle pulse clock signal that waits that cycle of the input clock signal CK_IN that provides equates that shakes to digital controlled signal, and is sent to the input of digital control delayer 23.Digital control delayer 23 is by the control of the digital controlled signal that obtains from clock cycle measuring appliance 22, produce and postpone, and the cycle pulse clock signal CK_P such as described is carried out to delay disposal, at output, obtain phase shift clock signal CK_0, CK_90, CK_180 and CK_270.Wherein, the input clock signal CK_IN that the phase place of phase shift clock signal CK_0 provides with external crystal-controlled oscillation and by pulse generator 1, produced etc. cycle pulse clock signal CK_P identical; The phase place of phase shift clock signal CK_90 is delayed 90 ° than the phase place of phase shift clock signal CK_0; The phase place of phase shift clock signal CK_180 is delayed 180 ° than the phase place of phase shift clock signal CK_0; The wooden order of phase shift clock signal CK_270 vertical than the phase place of phase shift clock signal CK_0, delay 270 °.

Describe respectively three parts of embodiment of the present invention phase shifter 2 below in detail.

(1) two-divider 21

As a kind of embodiment, the circuit structure diagram of the two-divider 21 shown in Fig. 5 as shown in Figure 6.

Two-divider 21 is comprised of two basic digital logic elements, is respectively: NOT logic door 11 and D type flip-flop 24, and wherein each logic element left end is input, right-hand member is output.

The input end of clock CK of D type flip-flop 24 is as the input of two-divider; The input of the output Q NAND Logic door 11 of D type flip-flop 24 is connected; The output of NOT logic door 11 is connected with the data input pin D of D type flip-flop 24, and the while is as the output of two-divider.

Due to D type flip-flop 24, the output valve Q in each input clock cycle remains unchanged, through 11 couples of Q of NOT logic door, be worth rhetorical question operation, make the output of 24 every adjacent two clock cycle of D type flip-flop contrary, therefore can realize the divide-by-two operations to input clock signal, can guarantee that duty ratio is 50% simultaneously.

(2) clock cycle measuring appliance 22

As a kind of embodiment, the circuit structure diagram of the clock cycle measuring appliance 22 shown in Fig. 5 as shown in Figure 7.

Clock cycle measuring appliance 22 is composed in series by a plurality of clock cycle measuring units 25, and wherein left end is input, and right-hand member is output.The IN input of first clock cycle measuring unit 25 is as the data input pin that is sampled of clock cycle measuring appliance, 2 times of the cycle of the input clock signal CK_IN that the clock cycle producing with previous stage two-divider 21 provides for original crystal oscillator, the clock signal terminal that duty ratio is 50% is connected.The OUT output of first clock cycle measuring unit 25 is connected with the IN input of second clock cycle measuring unit 25, the OUT output of second clock cycle measuring unit 25 is connected with the IN input of the 3rd clock cycle measuring unit 25, by that analogy, the OUT output of last clock cycle measuring unit (25) is unsettled.

The CK input of each clock cycle measuring unit 25 is as sampling clock input, 2 times of the cycle of the input clock signal CK_IN that the clock cycle producing with previous stage two-divider 21 provides for original external crystal-controlled oscillation, the clock signal that duty ratio is 50% is connected.The Q output of each clock cycle measuring unit 25 is as sampled result output, and output digital sampled signal is with control figure control lag device 23.

Preferably, as a kind of embodiment, the circuit structure of described clock cycle measuring unit as shown in Figure 8.

As shown in Figure 8, described each clock cycle measuring unit 25 comprises 4 two input 13,1 NOT logic doors 11 of NAND Logic door and 1 D type flip-flop 24, and wherein each logic element left end is input, and right-hand member is output.The A input of first left two input NAND Logic doors 13 is as the IN input of this clock cycle measuring unit, and B input is connected with high level, and output is connected with the A input of second left two input NAND Logic doors 13.The B input of second left two input NAND Logic doors 13 is connected with high level, and output is connected with the A input of third left two input NAND Logic doors 13.The B input of third left two input NAND Logic doors 13 is connected with high level, and output is connected with the A input of fourth left two input NAND Logic doors 13.The B input of fourth left two input NAND Logic doors 13 is connected with the CK input of this clock cycle measuring unit 25, and output is connected with the D input of D type flip-flop 24, and the while is as the OUT output of this clock cycle measuring unit 25.The input of NOT logic door 11 is as the CK input of this clock cycle measuring unit, and output is connected with the CK input of D type flip-flop 24.The Q output of D type flip-flop 24 is as the Q output of this clock cycle measuring unit.

Clock cycle measuring unit is when work, and the B input of first, second and third two inputs NAND Logic door 13 of the left side is all connected with high level, and its logic function NAND Logic door is identical, in circuit, as delay cell, uses.Fourth left two 13 pairs, input NAND Logic doors utilize CK clock signal to intercept input signal IN, only retain the intersection of high level in above-mentioned two signals.NOT logic door 11 is for inputted clock signal is asked in reply, and as the CK input signal of D type flip-flop 24.The D input that is D type flip-flop 24 at clock cycle measuring unit OUT output obtains a signal through postponing and intercepting, and utilizes the trailing edge of input clock signal to sample to it simultaneously, obtains the Q value of an output.If be there is a high level width by the signal after intercepting, the Q value of output is 1 so, if be there is no high level by the signal after intercepting, only has low level, and the Q value of output is 0 so.

In conjunction with the above-mentioned functional description to clock cycle measuring unit 25, obtain the sequential chart of each point in Fig. 7, as shown in Figure 9.

(3) digital control delayer 23

As a kind of embodiment, the circuit structure diagram of the digital control delayer 23 shown in Fig. 5 as shown in figure 10.

As shown in figure 10, wherein, digital control delayer 23 is comprised of a plurality of digital control delay cell 26.Wherein Qn is the control input end of this digital control delay cell 26, and LI and RI are the clock signal input terminal of this digital control delay cell 26, and LO and RO are the clock signal output terminal of this digital control delay cell 26.

Preferably, as shown in Figure 7, in each digital control delayer 23, the number of digital delay control unit 26 is 3/2 times of number of clock cycle measuring unit 25 in clock cycle measuring appliance 22.

As shown in figure 10, digital control delay cell 26 is divided into three groups, one group of each behavior, the connected mode of each group is identical.For the first row, the digital control delay cell 26R0 output of first left is connected with the digital control delay cell 26L1 input of second left, and the digital control delay cell 26RI input of first left is connected with the digital control delay cell 26L0 output of second left.By that analogy, the digital control delay cell 26R0 output of second right is connected with first digit control lag unit, the right 26L1 input, and the digital control delay cell 26RI input of second right is connected with first digit control lag unit, the right 26L0 output.Finally, the right first digit control lag unit 26R0 output is connected with the RI input of self.

The input clock signal CK_IN frequency that the digital control delay cell 26LI input of the first row first left crystal oscillator that produce with original with described pulse generator 1 provides and the phase place all identical cycle pulse clock signal CK_P that waits are connected; clock signal input terminal as this digital control delayer 23; simultaneously as CK_0 output, the phase shift clock signal CK_0 that output frequency is identical with the isopulse clock signal C K_P being produced by pulse generator 1 with phase place;

The digital control delay cell 26L0 output of the first row first left is connected with the digital control delay cell 26L1 input of the second row first left; simultaneously as CK_90 output; output frequency is identical with the cycle pulse clock signal CK_P such as grade being produced by pulse generator 1, the phase shift clock signal CK_90 that phase delay is 90 °;

The digital control delay cell 26L0 output of the second row first left is connected with the digital control delay cell 26L1 input of the third line first left; simultaneously as CK_180 output; output frequency is identical with the cycle pulse clock signal CK_P such as grade being produced by pulse generator 1, the phase shift clock signal CK_180 that phase delay is 180 °;

The digital control delay cell 26L0 output of the third line first left is as CK_270 output, and output frequency is identical with the cycle pulse clock signal CK_P such as grade being produced by pulse generator 1, the phase shift clock signal CK_270 that phase delay is 270 °.

For the Q input of the digital control delay cell 26 of every a line, from left to right according to indicating, be connected with the Q output signal of clock cycle measuring appliance in Fig. 7 successively, for example Q1 is connected with Q1, and Q2 is connected with Q2 ... Qn is connected with Qn.

More preferably, as a kind of embodiment, the circuit structure of described digital control delay cell 26 as shown in figure 11.

Wherein, described digital control delay cell 26 is comprised of 3 two input

NAND Logic doors

13 and 1 NOT logic door 11.The input of NOT logic door 11, as the Q input of this digital control delay cell, is connected with the B input of upper right side two input NAND Logic doors 13 simultaneously; The output of NOT logic door 11 is connected with the B input of two input NAND Logic doors 13 of centre.The A input of top-right two input NAND Logic doors 13 is connected with the A input of two input NAND Logic doors 13 of centre, and the while is as the LI input of this digital control delay cell 26; The output of top-right two input NAND Logic doors 13 is as the R0 output of this digital control delay cell 26.The output of two middle input NAND Logic doors 13 is connected with the B input of two input NAND Logic doors 13 of lower left.The A input of two input NAND Logic doors 13 of lower left is as the RI input of this digital control delay cell 26; The output of two input NAND Logic doors 13 of lower left is as the LO output of this digital control delay cell 26.

As a kind of embodiment; when input control signal Q is 1; two middle input NAND Logic door 13 output signal perseverances are 1, and top-right two input NAND Logic doors 13 are equivalent to a NOT logic door, therefore from the clock signal of LI input input from the output of RO end; When input control signal Q is 0, top-right two input NAND Logic door 13 output perseverances are 1, and two middle input NAND Logic doors 13 are equivalent to a NOT logic door, and the clock signal of LI input is exported from LO section.

Known in conjunction with Figure 10 and Figure 11, by different Q input controls, can control inputs wait the ad-hoc location of cycle pulse clock signal CK_P in digital control delayer 23 to turn to return.

Below in conjunction with the concrete structure of above-mentioned phase shifter, further describe the course of work of the phase shifter 2 of the embodiment of the present invention.

Make the input of two in digital control delay cell 26 NAND Logic door 13 take identical structure with the input of two in clock cycle measuring unit NAND Logic door 13 simultaneously, can be achieved as follows function so: in clock cycle measuring appliance 22, recording the clock cycle equals the delay of 4X two input NAND Logic doors 13, in digital control delayer 23, three groups of every groups of postponing all equal the delays of X two input NAND Logic doors 13, therefore can realize the phase shift of 90 °, 180 ° and 270 °.

In embodiments of the present invention, need to carry out two frequencys multiplication to clock, in clock cycle measuring unit 25, use 4 two input NAND Logic doors 13; In digital control delayer 23, the number of digital control delay cell 26 is the number of the clock cycle measuring unit of 3/2 times, and is divided into three groups, and each number of organizing digital control delay cell 26 is the number of 1/2 times of clock cycle measuring unit; If the control signal of clock cycle measuring appliance 22 outputs is followed successively by Q1, Q2, Q3, Q4 ... Qn-1, Qn, connected mode for digital controlled signal, first group and the 3rd group of digital control delay cell 26 control signals can be expressed as Q1, Q3, Q5 in order ... Qn-3, Qn-1, second group of digital control delay cell 26 control signal can be expressed as Q2, Q4, Q6 in order ... Qn-2, Qn.

Preferably, if clock is carried out to N frequency multiplication, in digital control delayer 23, the number of digital control delay cell 26 is the number of the clock cycle measuring unit of (2N-1)/2 times, and be divided into (2N-1) group, each number of organizing digital control delay cell 26 is the number of 1/2 times of clock cycle measuring unit 25, if the control signal of clock cycle measuring appliance 22 outputs is followed successively by Q1, Q2, Q3, Q4 ... Qn-1, Qn, connected mode for digital controlled signal, the 1st group and (N+1) organize digital control delay cell 26 control signals and can be expressed as in order Q1, Q (N+1), Q (2N+1), Q (3N+1) the 2nd group and (N+2) organize digital control delay cell 26 control signals and can be expressed as in order Q2, Q (N+2), Q (2N+2), Q (3N+2) the 3rd group and (N+3) organize digital control delay cell 26 control signals and can be expressed as in order Q3, Q (N+3), Q (2N+3), Q (3N+3) a (a < N) group and (N+a) organize digital control delay cell 26 control signals and can be expressed as in order Qa, Q (N+a), Q (2N+a), Q (3N+a)

Describe the phase synthesizer 3 of the embodiment of the present invention below in detail.

Phase synthesizer 3 as known in the sequential chart of Fig. 2 need to concentrate on the pulse of all input signals in a clock signal, exactly all clock signals is done to "or" logical operation.Therefore, by derivation, obtain formula (1):

Y = A + B + C + D = \overset{&OverBar;}{\overset{&OverBar;}{(A + B)} \cdot \overset{&OverBar;}{(C + D)}} - - - (1)

As a kind of embodiment, the circuit structure of phase synthesizer 3 in Fig. 1, as shown in figure 12, in Figure 12, the logical expression of phase synthesizer is formula (1).

Wherein, described phase synthesizer 3 comprises two kinds of basic digital logic gate components, is respectively: two input NOR-logic doors 14 and two input NAND Logic doors 13, and wherein each gate left end is input, right-hand member is output.

The A input of two input NOR-logic doors 14 is above as the input of phase shift clock signal CK_0, and B input is as the input of phase shift clock signal CK_90, and output is connected with the A input of two input NAND Logic doors 13.The A input of two input NOR-logic doors 14 is below as the input of phase shift clock signal CK_180, and B input is as the input of phase shift clock signal CK_270, and output is connected with the B input of two input NAND Logic doors 13.The output of two input NAND Logic doors 13 is as the output of quadruple clock signal C K_4T.

Describe frequency divider 4 of the present invention below in detail.

Frequency divider is a kind of prior art, only as a kind of instrument, uses in embodiments of the present invention.Signal after the structure of frequency divider 4 can be synthesized phase place according to the actual requirements carries out multiple frequency division, and its divider ratio is not limited to two divided-frequency and four frequency divisions.

In embodiments of the present invention, as a kind of embodiment, signal after synthetic to phase place has carried out respectively four frequency divisions and two divided-frequency, and the fraction frequency device that two divided-frequency is used can be used the two-divider structure shown in Fig. 6, and four frequency divisions only need to be used two two-divider series connection.

Further, the clock multiplier of the embodiment of the present invention, consideration is in more intense radiation, as the radiation environment of space can produce more serious impact to integrated circuit, thereby more affect stability and the correctness of circuit working, more reduce it in the situation that the probability making a mistake in practical work process, the embodiment of the present invention is improved further the part component device in clock multiplier.

In more intense radiation, as irradiation space in this case, although the clock multiplier of the embodiment of the present invention, oneself is through having certain capability of resistance to radiation, intense radiation, as irradiation space irradiates the certain influence that also can produce integrated circuit, comprises following aspect:

1) digital latch state transition;

2) the downward drift of N type field-effect transistor threshold voltage;

3) thus the gate edge of N type field-effect transistor can produce leakage current conducting source electrode and drain electrode, change circuit working state.

More preferably, for more these three kinds of impacts of intense radiation, in the embodiment of the present invention, the components and parts of clock multiplier also further improve as follows:

Embodiment bis-: a kind of improved clock cycle measuring unit

In the embodiment of the present invention, D type flip-flop can adopt D type of transistor to realize as sampling instrument, its Output rusults is to follow some 0 continuous signals after some 1 continuous signals, when 0 signal generation latch mode saltus step, from 0 signal, become 1 signal, only otherwise at the intersection of 1 signal and 0 signal, to circuit be do not have influential.But if 1 signal generation latch mode saltus step becomes 0 signal from 1 signal, will change the size postponing in digital control delayer 23, thereby make a mistake.

Therefore,, in the embodiment of the present invention, as another kind of embodiment, the embodiment of the present invention provides a kind of clock cycle measuring unit, as shown in figure 13.

As another kind of embodiment, a kind of clock cycle measuring unit of the embodiment of the present invention, comprises 4 two input

NAND Logic doors

13,1 NOT logic door 11,3 D type flip-

flop

24 and 1 three input NAND Logic door 15, wherein each logic element left end is input, right-hand member is output.

The A input of first left two input NAND Logic doors 13 is as the IN input of this clock cycle measuring unit, and B input is connected with high level, and output is connected with the A input of second left two input NAND Logic doors 13.The B input of second left two input NAND Logic doors 13 is connected with high level, and output is connected with the A input of third left two input NAND Logic doors 13.The B input of third left two input NAND Logic doors 13 is connected with high level, and output is connected with the A input of fourth left two input NAND Logic doors 13.The B input of fourth left two input NAND Logic doors 13 is connected with the CK input of this clock cycle measuring unit, and the output while is connected with the D input of three D type flip-flop 24, and as the OUT output of this clock cycle measuring unit.The input of NOT logic door 11 is as the CK input of this clock cycle measuring unit, and output is connected with the CK input of three D type flip-flop 24 simultaneously.The Q output of three D type flip-flop 24 is connected with A, B, the C input of three input NAND Logic doors 15 by 1 NOT logic door 11 respectively, and order arbitrarily.Three input NAND Logic doors 15 are as the Q output of this clock cycle measuring unit.

A kind of clock cycle measuring unit of the embodiment of the present invention after this improvement, its circuit is identical with the function of former clock cycle measuring unit circuit, but introduces latch mode voting mechanism.When correct latch mode is 1 signal, in QA, QB and QC there is 1 signal to the saltus step of 0 signal in any one or two signals, NOT"function" through NOT logic door 11, become 1 signal, the output valve of three input NAND Logic doors 15 will can not be had influence on, thereby guaranteed the stability of circuit, can greatly reduce the probability that circuit is made mistakes.

Embodiment tri-: a kind of improvement two input NAND Logic gate means, and a kind of improved NOT logic gate means

When there is downward drift in N type field-effect transistor threshold voltage; N type field-effect transistor in logic gates will be easy to conducting; thereby change the operating state of circuit; therefore; in the embodiment of the present invention; as another kind of embodiment, provide a kind of two input NAND Logic gate means, as shown in figure 15; And a kind of NOT logic gate means, as shown in figure 14.

In the embodiment of the present invention, as another kind of embodiment, as shown in figure 14, the NOT logic gate means 16 of the embodiment of the present invention, is comprised of 2 N type field-effect transistors and 2 P type field-effect transistors.

N type field effect transistor substrate meets VSS, and P type field effect transistor substrate meets VDD, and the grid of all field-effect transistors is connected with IN input signal.The source electrode of P type field effect transistor M 1 is connected with VDD, and drain electrode is connected with the source electrode of N type field effect transistor M 4 with the drain electrode of N type field effect transistor M 2.The source electrode of N type field effect transistor M 2 is connected with VSS.The source electrode of P type field effect transistor M 3 is connected with VDD, and drain electrode is connected with OUT output signal with the drain electrode of N type field effect transistor M 4.

If there is intense radiation, as irradiation space irradiates, there is downward drift in N type field-effect transistor threshold voltage, and the N type field-effect transistor in conventional NOT logic door may, with regard to conducting when input voltage is very low, make output signal become 0.

The NOT logic gate means of the lower surface analysis embodiment of the present invention.

At work, if do not have irradiation space to irradiate, during input signal IN=1, N type field effect transistor M 2 and M4 conducting, P type field effect transistor M 1 and M3 are closed, output signal OUT=0; During input signal IN=0, N type field effect transistor M 2 and M4 are closed, P type field effect transistor M 1 and M3 conducting, output signal OUT=0.

If have intense radiation, irradiate as irradiation space, during input signal IN=1, the private M4 conducting of N type field effect transistor M 2, P type field effect transistor M 1 and M3 are closed, output signal OUT=0; When input signal IN voltage is lower, P type field effect transistor M 1 and M3 conducting, if N type field effect transistor M 2 is own through conducting, now the source voltage of N type field effect transistor M 4 is more high than VSS, thereby N type field effect transistor M 4 conducting voltage are raise, M4 is closed, output signal OUT=0.

In the embodiment of the present invention, as another kind of embodiment, as shown in figure 15, a kind of two input NAND Logic gate means 17 of the embodiment of the present invention, are comprised of 4 N type field-effect transistors and 4 P type field-effect transistors.

N type field effect transistor substrate meets VSS, and P type field effect transistor substrate meets VDD.The grid of the grid of P type field effect transistor M 1 and M7, N type field effect transistor M 2 and M3 is connected with A input signal jointly, and the grid of the grid of P type field effect transistor M 5 and M8, N type field effect transistor M 4 and M6 is connected with B input signal jointly.The source electrode of P type field effect transistor M 1 is connected with VDD, and drain electrode is connected with the source electrode of N type field effect transistor M 3 with the drain electrode of N type field effect transistor M 2.The source electrode of N type field effect transistor M 2 is connected with VSS.The drain electrode of N type field effect transistor M 3 is connected with the source electrode of N type field effect transistor M 4.The drain electrode of N type field effect transistor M 4 is connected with the drain electrode of P type field effect transistor M 5, the source electrode of N type field effect transistor M 6.The source electrode of P type field effect transistor M 5 is connected with VDD.The drain electrode of N type field effect transistor M 6 is connected with the drain electrode of P type field effect transistor M 7 and M8, as output.The source electrode of P type field-effect transistor W7 and M8 is connected with VDD.

The analysis classes of NAND Logic door seemingly; a kind of two input NAND Logic gate means for the embodiment of the present invention; at work; if there is no intense radiation, irradiate as irradiation space; when input signal A=1, B=1; N type field effect transistor M 1, M3, M4 and M6 conducting, P type field effect transistor M 2, M5, M7 and M8 are closed, output signal OUT=0; In input signal A and B, have at least one to be at 0 o'clock, N type field effect transistor M 1, M3, M4 and M6 are closed, P type field effect transistor M 2, M5, M7 and M8 conducting, output signal OUT=1.

When there is intense radiation, while irradiating as irradiation space, when input signal A=1, B=1, N type field effect transistor M 1, M3, M4 and M6 conducting, P type field effect transistor M 2, M5, M7 and M8 are closed, output signal OUT=0; When input signal A and B voltage are when lower, P type field effect transistor M 2, M5, M7 and 2 conductings of M8 conducting N type field effect transistor M, now the source voltage of N type field effect transistor M 3 is more high than VSS, so M3 is closed, output signal OUT=1.Even if M3 is conducting also, the source voltage of N type field-effect transistor N4 is higher than the source voltage of M3, therefore be more difficult for conducting, by parity of reasoning, N type field effect transistor M 6 is to be difficult for conducting most in four N type field-effect transistors, therefore this structure can guarantee, when N type field-effect transistor threshold voltage, downward drift occurs, and the function of gate is still correct.

Embodiment tetra-: a kind of structure of improving N type field-effect transistor

Under intense radiation illuminate condition, thereby the gate edge of N type field-effect transistor can produce leakage current conducting source electrode and drain electrode, changes circuit working state.

For fear of the generation of this kind of situation, as another kind of embodiment, the embodiment of the present invention also provides a kind of N type field-effect transistor, and its grid is ring-shaped gate.

Embodiment of the present invention N type field-effect transistor, changes the straight grid of length of common N type field-effect transistor as ring-shaped gate into, as shown in figure 16.

The N type field-effect transistor of this structure, utilizes ring-shaped gate to break off the leakage current path from source electrode to drain electrode, guarantees that N type field-effect transistor can work, and can not be subject to the impact of the leakage current that produces because of radiation irradiation.

Embodiment five: a kind of clock multiplier method

Correspondingly, the embodiment of the present invention also provides a kind of clock multiplier method, comprises the steps:

Step S100, becomes isoperimetric phase pulse clock signal by outside input clock signal adjustment;

Step S200, carries out the phase shift of different time to the cycle pulse clock signal such as described of input according to required frequency and clock cycle, obtains phase shift clock signal;

Step S300, waits cycle pulse clock signal and by each phase shift clock signal after phase shift, is carried out phase place and synthesize described, obtains frequency doubling clock signal;

Step S400, carries out frequency division to the frequency doubling clock signal being carried out after phase place is synthesized, and obtains frequency multiplication clock signal output.

As a kind of embodiment, outside input clock signal, from the input input of pulse generator, produces by pulse generator waiting cycle pulse clock signal and being sent to phase shifter of equating with input clock signal frequency.

The clock multiplier method of the embodiment of the present invention, completes the work of each step with the identical procedure of the course of work with the corresponding clock multiplier of the embodiment of the present invention.Therefore, in embodiments of the present invention, be no longer repeated in this description in detail one by one.

The clock multiplier of the embodiment of the present invention and frequency-doubling method, by with digital circuit clock multiplier, solved the instability problem that radiation causes, it realizes the frequency multiplication of clock signal in the situation that there is no phase-locked loop, and can access the frequency-doubled signal of 50% duty ratio, and there is not feedback loop, increase dynamic sampling redundancy simultaneously, the probability making a mistake under the condition of radiation irradiation is less, can work.

Although with reference to preferred embodiment oneself through having described the present invention, those skilled in the art will recognize, can carry out the change in form and details, only otherwise disengaging the spirit and scope of the present invention.The present invention attempts to be not limited to the specific embodiment being disclosed, and as expected for implementing optimal mode of the present invention, on the contrary, the present invention will comprise whole embodiment of the scope that falls into accessory claim.

Claims

1. a clock multiplier, is characterized in that, comprising:

Pulse generator (1), for becoming isoperimetric phase pulse clock signal by outside input clock signal adjustment;

Phase shifter (2), for according to required frequency and clock cycle, the cycle pulse clock signal such as described of input being carried out to the phase shift of different time, obtains phase shift clock signal;

Phase synthesizer (3), for waiting cycle pulse clock signal and carried out phase place by each phase shift clock signal after phase shift and synthesize described, obtains frequency doubling clock signal;

Frequency divider (4), for the frequency doubling clock signal being carried out after phase place is synthesized is carried out to frequency division, obtains frequency multiplication clock signal output;

Described phase shifter (2) comprises two-divider (21), clock cycle measuring appliance (22) and digital control delayer (23);

Two-divider (21), for using described cycle pulse clock signal such as grade as input signal, processes and obtains the clock signal that a clock high level equated with the cycle of described cycle pulse clock signal such as grade;

Clock cycle measuring appliance (22), converts digital controlled signal to for the clock signal that two-divider (21) is produced, and is sent to the input of digital control delayer (23);

Digital control delayer (23), for the control of the digital controlled signal by obtaining from clock cycle measuring appliance (22), produce to postpone, and the cycle pulse clock signal such as described is carried out to delay disposal, at output, obtains phase shift clock signal.

2. clock multiplier according to claim 1, is characterized in that, the differing of described phase shifter (2) phase shift be respectively T/2N, 2*T/2N ..., (2N-1) T/2N;

The pulse duration of described outside input clock signal CLK_IN is T/4N-T/8N;

Wherein, N is required frequency, and it is positive integer; T is the clock cycle.

3. clock multiplier according to claim 1, is characterized in that, described pulse generator (1) comprises a plurality of NOT logic doors (11), two input exclusive or logic gates (12), two input NAND Logic doors (13);

In pulse generator inside, there are two clock signal paths:

Article one, clock signal path is that outside input clock signal is transferred to the A input of two input exclusive or logic gates (12) and the A input of two input NAND Logic doors (13);

Second clock signal path is first a plurality of NOT logic door (11) inputs and output to be joined end to end, input after connecting is connected with outside input clock signal end, and output is connected with the B input of two input exclusive or logic gates (12); The output of two input exclusive or logic gates (12) is connected with the B input of two input NAND Logic doors (13), and the output of two input NAND Logic doors (13) is to wait cycle pulse clock signal end.

4. clock multiplier according to claim 1, is characterized in that, described two-divider (21) comprises NOT logic door (11) and D type flip-flop (24);

The input end of clock CK of D type flip-flop (24) is as the input of two-divider (21); The input of the output Q NAND Logic door (11) of D type flip-flop (24) is connected;

The output of NOT logic door (11) is connected with the data input pin D of D type flip-flop (24), and the while is as the output of two-divider.

5. clock multiplier according to claim 1, is characterized in that, described clock cycle measuring appliance (22) is composed in series by a plurality of clock cycle measuring units (25);

The IN input of first clock cycle measuring unit (25) is connected with two-divider (21);

The OUT output of last clock cycle measuring unit (25) is unsettled.

6. clock multiplier according to claim 5, is characterized in that, described clock cycle measuring unit comprises 4 two input NAND Logic doors (13), 1 NOT logic door (11) and 1 D type flip-flop (24);

The A input of first two input NAND Logic doors (13) is as the IN input of described clock cycle measuring unit, and B input is connected with high level, and output is connected with the A input of second two input NAND Logic door (13);

The B input of second two input NAND Logic door (13) is connected with high level, and output is connected with the A input of the 3rd two input NAND Logic door (13);

The B input of the 3rd two input NAND Logic door (13) is connected with high level, and output is connected with the A input of the 4th two input NAND Logic door (13);

The B input of the 4th two input NAND Logic door (13) is connected with the CK input of described clock cycle measuring unit (25), output is connected with the D input of D type flip-flop (24), and the while is as the OUT output of this clock cycle measuring unit (25);

The input of NOT logic door (11) is as the CK input of described clock cycle measuring unit, and output is connected with the CK input of D type flip-flop (24);

The Q output of D type flip-flop (24) is as the Q output of this clock cycle measuring unit.

7. clock multiplier according to claim 6, it is characterized in that described clock cycle measuring unit comprises 4 two input NAND Logic doors (13), 1 NOT logic door (11), 3 D type flip-flop (24) and 1 three input NAND Logic door (15);

The B input of the 4th two input NAND Logic door (13) is connected with the CK input of described clock cycle measuring unit, output is connected with the D input of three D type flip-flop (24) simultaneously, and as the OUT output of described clock cycle measuring unit;

The input of NOT logic door (11) is as the CK input of described clock cycle measuring unit, and output is connected with the CK input of three D type flip-flop (24) simultaneously;

The Q output of three D type flip-flop (24) is connected with A, B, the C input of three input NAND Logic doors (15) through a NOT logic door (11) respectively;

Three input NAND Logic doors (15) are as the Q output of this clock cycle measuring unit.

8. clock multiplier according to claim 5, is characterized in that, described digital control delayer (23) is comprised of a plurality of digital control delay cells (26);

The control input end of wherein said digital control delay cell (26) is Qn, and the clock signal input terminal of described digital control delay cell (26) is LI and RI, and the clock signal output terminal of described digital control delay cell (26) is LO and RO;

Described digital control delay cell (26) is divided into three groups, one group of each behavior, and the connected mode of each group is identical;

For every a line, first digit control lag unit (26) RO output is connected with second digit control lag unit (26) LI input, and first digit control lag unit (26) RI input is connected with second digit control lag unit (26) LO output;

Second digit control lag unit (26) RO output is connected with third digit control lag unit (26) LI input, and second digit control lag unit (26) RI input is connected with third digit control lag unit (26) LO output; By that analogy;

Last digital control delay cell (26) RO output is connected with the RI input of self.

9. clock multiplier according to claim 8, is characterized in that, described digital control delay cell (26) is comprised of 3 two input NAND Logic doors (13) and 1 NOT logic door (11);

The input of NOT logic door (11), as the Q input of described digital control delay cell, is connected with the B input of the one or two input NAND Logic door (13) simultaneously; The output of NOT logic door (11) is connected with the B input of the two or two input NAND Logic door (13);

The A input of the one or two input NAND Logic door (13) is connected with the A input of the two or two input NAND Logic door (13), and the while is as the LI input of described digital control delay cell (26); The output of the one or two input NAND Logic door (13) is as the RO output of described digital control delay cell (26);

The output of the two or two input NAND Logic door (13) is connected with the B input of the three or two input NAND Logic door (13); The A input of the three or two input NAND Logic door (13) is as the RI input of described digital control delay cell (26); The output of the three or two input NAND Logic door (13) is as the LO output of described digital control delay cell (26).

10. clock multiplier according to claim 8, it is characterized in that, the number of digital delay control unit (26) is 3/2 times of number of clock cycle measuring unit (25) in clock cycle measuring appliance (22) in described digital control delayer (23).

11. clock multipliers according to claim 8, it is characterized in that, if clock is carried out to N frequency multiplication, in digital control delayer (23), the number of digital control delay cell (26) is the number of the clock cycle measuring unit of (2N-1)/2 times; And be divided into (2N-1) group, each number of organizing digital control delay cell (26) is the number of 1/2 times of clock cycle measuring unit (25);

Wherein, N is positive integer.

12. clock multipliers according to claim 1, is characterized in that, described phase synthesizer 3 comprises a plurality of two input NOR-logic doors (14), and two input NAND Logic doors (13);

The A input of described two input NOR-logic doors (14) is as the input of phase shift clock signal, and B input is as the input of another clock signal, and output is connected with the A input of two input NAND Logic doors (13);

The output of two input NAND Logic doors (13) is as the output of frequency doubling clock signal.

13. according to the clock multiplier described in any one in claim 3,6,7,9,10, it is characterized in that, described two input NAND Logic doors, are comprised of 4 N type field-effect transistors and 4 P type field-effect transistors;

The source electrode of P type field effect transistor M 1 is connected with VDD, and drain electrode is connected with the source electrode of N type field effect transistor M 3 with the drain electrode of N type field effect transistor M 2.

14. clock multipliers according to claim 13, is characterized in that, the source electrode of described N type field effect transistor M 2 is connected with VSS, and the drain electrode of N type field effect transistor M 3 is connected with the source electrode of N type field effect transistor M 4;

The source electrode of P type field effect transistor M 5 is connected with VDD;

15. according to the clock multiplier described in any one in claim 3,6,7,9,10, it is characterized in that, described NOT logic door is comprised of 2 N type field-effect transistors and 2 P type field-effect transistors;

16. clock multipliers according to claim 15, is characterized in that, the source electrode of P type field effect transistor M 1 is connected with VDD, and drain electrode is connected with the source electrode of N type field effect transistor M 4 with the drain electrode of N type field effect transistor M 2;

The source electrode of P type field effect transistor M 3 is connected with VDD, and drain electrode is connected with OUT output signal with the drain electrode of N type field effect transistor M 4.

17. clock multipliers according to claim 13, is characterized in that, the grid of described N type field-effect transistor is ring-shaped gate.

18. 1 kinds of clock multiplier methods, is characterized in that, comprising:

Phase shifter (2) carries out the phase shift of different time according to required frequency and clock cycle to the cycle pulse clock signal such as described of input, obtains the step of phase shift clock signal;

19. clock multiplier methods according to claim 18, is characterized in that, described outside input clock signal adjustment are become to isoperimetric phase pulse clock signal, comprise the steps:

20. clock multiplier methods according to claim 19, is characterized in that, the described cycle pulse clock signal that waits to input carries out the phase shift of different time, comprises the steps:

Phase shifter carries out phase shifts to the described cycle pulse clock signal that waits, producing with the described phase difference that waits cycle pulse clock signal is respectively four phase shift clock signal: CK_0, CK_90, CK_180 and CK_270 of O °, 90 °, 180 ° and 270 °, and is sent to phase synthesizer.

21. clock multiplier methods according to claim 19, is characterized in that, described by waiting cycle pulse clock signal and being carried out phase place by each phase shift clock signal after phase shift and synthesize, and comprise the steps:

22. clock multiplier methods according to claim 21, is characterized in that, the described frequency doubling clock signal that quilt is carried out after phase place is synthesized carries out frequency division, comprises the steps: