CN112782561A - Chip interface test probe card and test method - Google Patents
Chip interface test probe card and test method Download PDFInfo
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- CN112782561A CN112782561A CN202011643868.5A CN202011643868A CN112782561A CN 112782561 A CN112782561 A CN 112782561A CN 202011643868 A CN202011643868 A CN 202011643868A CN 112782561 A CN112782561 A CN 112782561A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention discloses a chip interface test probe card and a test method, relates to the technical field of chip test, and is convenient for testing a high-speed IO interface of a chip. The probe card comprises a printed circuit board, a first surface of the printed circuit board is provided with a test needle point, a second surface of the printed circuit board is provided with a substrate, a loopback circuit is arranged on the substrate, an installation part for installing a probe is further arranged on the substrate, the loopback circuit comprises an input end and an output end, and the input end and the output end are respectively connected with the installation part. The method is suitable for the wafer-level chip interface test scene, in particular to the high-speed IO interface test occasion.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a probe card for testing a chip interface and a testing method.
Background
As an important link for ensuring good product in chip manufacturing, integrated circuit chip testing is generally performed on a wafer level to identify a Die (Die) used for packaging a chip in order to reduce chip testing and packaging costs. At present, in the semiconductor industry, an automatic tester ate (automatic Test equipment) is often used in conjunction with a probe card to perform a wafer-level chip (i.e., die) reliability Test.
In testing a high-speed signal interface of an integrated circuit chip (generally, when a clock frequency exceeds 100MHz or a rising edge is less than 1ns, which is called a high-frequency field or a high-speed field), a loop-back (Loopback) test is a very important test technology, and a spontaneous self-test form of the Loopback test can help to test a physical link of the integrated circuit chip. The Loopback test is divided into Internal Loopback and External Loopback, and the External Loopback has a wider test range and is more comprehensive than the Internal Loopback.
In some hardware implementation schemes for the outer loop test, the loop circuit is often arranged on a probe card multi-layer circuit board (also called a printed circuit board, commonly called a PCB) to perform the external loop test, which is easily affected by other wiring on the circuit board, and has signal integrity problems such as reflection, crosstalk, noise, and the like, so that it is difficult to achieve a high-speed IO (Input & Output) interface test speed, and it is inconvenient to test a chip high-speed IO interface.
Disclosure of Invention
In view of this, embodiments of the present invention provide a probe card for testing a chip interface and a testing method, which are convenient for testing a high-speed IO interface of a chip.
In order to achieve the purpose of the invention, the following technical scheme is adopted:
in a first aspect, an embodiment of the present invention provides a probe card for testing a chip interface, including a printed circuit board, where a first surface of the printed circuit board has test probe points, a second surface of the printed circuit board is provided with a substrate, the substrate is provided with a loopback circuit, the substrate is further provided with an installation portion for installing probes, the loopback circuit includes an input end and an output end, and the input end and the output end are respectively connected to the installation portion.
With reference to the first aspect, in a first implementation manner of the first aspect, the loopback circuit is a differential loopback circuit.
With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the differential loopback circuit is an RC differential loopback circuit or an LC differential loopback circuit.
With reference to the first or second implementation manner of the first aspect, in a third implementation manner of the first aspect, the differential loopback circuit includes a first differential signal line and a second differential signal line that are arranged in parallel on the substrate, a first coupling capacitor is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line.
With reference to any one of the first to third implementation manners of the first aspect, in a fourth implementation manner of the first aspect, when the differential loopback circuit is an RC differential loopback circuit, the differential loopback circuit further includes a third differential signal line and a fourth differential signal line that are arranged in parallel on the substrate, the third differential signal line includes a first pre-stage signal line and a first post-stage signal line, the first pre-stage signal line is connected to the first end of the first coupling capacitor, the first post-stage signal line is connected to the second end of the first coupling capacitor, a first resistor is disposed on the first pre-stage signal line, and a second resistor is disposed on the first post-stage signal line;
the fourth differential signal line comprises a second pre-stage signal line and a second post-stage signal line, the second pre-stage signal line is connected to the first end of the second coupling capacitor, the second post-stage signal line is connected to the second end of the second coupling capacitor, a third resistor is arranged on the second pre-stage signal line, and a fourth resistor is arranged on the second post-stage signal line;
when the differential loopback circuit is an LC differential loopback circuit, the resistor in the RC differential loopback circuit is replaced by an inductor.
In a second aspect, an embodiment of the present invention provides a chip interface testing method, which is implemented based on any one of the probe cards of the first aspect, wherein the probe card is connected to a device for triggering a test through a test probe on a first surface, a probe is installed in an installation portion on a substrate of the probe card, an end of the probe is in contact with an interface of a die to be tested on a wafer, and the die to be tested on the wafer is an unpackaged chip;
the method comprises the following steps:
after a test instruction is triggered, a chip sending end sends a loopback test packet to enter a loopback circuit input end on a probe card substrate through a probe;
the loopback test packet entering the loopback circuit is looped back to the chip receiving end through the loopback circuit output end;
and determining the state of the corresponding interface of the chip based on the test packet looped back by the receiving end of the chip.
With reference to the second aspect, in a first embodiment of the second aspect, the test packet is a pseudo random code;
the chip sending end sends a loopback test packet to enter the loopback circuit input end on the probe card substrate through the probe, and the loopback test packet comprises: the chip sending end sends a pseudo-random code to the input end of the loopback circuit;
the loopback test packet entering the loopback circuit is looped back to the chip receiving end through the loopback circuit output end, and the loopback test packet comprises: and the loopback circuit transmits the pseudo-random code by differential signals and returns the pseudo-random code to the receiving end of the chip through the output end of the loopback circuit.
With reference to the first implementation manner of the second aspect, in a second implementation manner of the second aspect, the loopback circuit transmitting the pseudo random code in a differential signal and looping back to a chip receiving end via a loopback circuit output ring includes:
the loop-back circuit transmits pseudo-random code differential signals through a first differential signal circuit and a second differential signal circuit;
the first coupling capacitor is used for carrying out alternating current coupling on the pseudo random code differential signal in the first differential signal circuit, filtering out a direct current component in the pseudo random code differential signal and then outputting a first differential signal to a chip receiving end;
the second coupling capacitor is used for carrying out alternating current coupling on the pseudo random code differential signal in the second differential signal circuit, filtering out a direct current component in the pseudo random code differential signal and outputting a second differential signal to a chip receiving end;
the determining the state of the corresponding interface of the chip by the test packet based on the loopback of the receiving end of the chip comprises the following steps:
determining a pseudo-random code level value sent by a chip sending end according to the difference value of the first differential signal and the second differential signal;
and comparing the determined pseudo-random code level value with a preset expected value to determine the state of the corresponding interface of the chip.
With reference to the first or second embodiment of the second aspect, in a third embodiment of the second aspect,
the equipment for triggering the test is an automatic tester;
the method further comprises the following steps: respectively connecting a first front-stage signal wire and a first rear-stage signal wire of the third differential signal circuit and a second front-stage signal wire and a second rear-stage signal wire of the fourth differential signal circuit to a direct current test channel of the automatic tester, and respectively connecting the first differential signal wire and the second differential signal wire with corresponding interfaces of the chip through probes;
by utilizing the direct-current open circuit characteristics of the first coupling capacitor and the second coupling capacitor, the loopback test loop is disconnected and switched into four direct-current test loops;
and testing the direct current characteristics of the chip interface based on each direct current test loop.
With reference to any one of the first to third embodiments of the second aspect, in a fourth embodiment of the second aspect, after the dc characteristic test of the chip interface is finished, the method further includes:
after receiving a loopback test instruction, switching to a dynamic characteristic test environment;
in a dynamic characteristic testing environment, a first resistor, a second resistor, a third resistor and a fourth resistor block signal transmission between a chip transmitting end or a chip receiving end and a direct current channel of an automatic tester;
meanwhile, the loopback test circuit is conducted based on the characteristic that the first coupling capacitor and the second coupling capacitor are isolated from direct current and alternating current.
According to the chip interface test probe card and the test method provided by the embodiment of the invention, the probe card is improved, the loop circuit is arranged on the substrate, so that the loop circuit is far away from other electronic elements and wiring on the printed circuit board, and the distance of the interconnection line in the loop test circuit formed between the transmitting end and the receiving end of the chip interface is shorter, so that the signal integrity problems of signal reflection, crosstalk, noise and the like in the existing loop test scheme of the probe card can be improved, the high-speed IO (Input & Output) interface test speed can be conveniently realized, and the high-speed IO interface of the chip can be conveniently tested.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a probe card according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an embodiment of a hardware testing environment for wafer level integrated circuit chip testing constructed based on a probe card according to the present invention;
FIG. 3 is a schematic circuit topology diagram of an embodiment of a loopback circuit on a probe card substrate according to the present invention;
FIG. 4 is a schematic layout diagram of a loopback circuit on a probe card substrate according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating simulation results of an embodiment of a chip interface external loopback test performed based on a probe card according to the present invention;
FIG. 6 is a flowchart illustrating a method for testing a chip interface according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The probe card provided by the embodiment of the invention is suitable for a wafer-level chip (namely a DIE) interface test scene, in particular to a test occasion of a high-speed IO interface; the outer loop circuit test of the high-speed interface hardware is convenient to realize, and the direct current DC characteristic test of the high-speed interface hardware can also be realized.
FIG. 1 is a schematic structural diagram of a probe card according to an embodiment of the present invention; referring to fig. 1, the Probe card (Probe card) includes a Printed circuit board (PCB, but commonly referred to in the art as PCB board, and hereinafter also referred to as PCB board for convenience of description, which is a generic term for PCB board), having on a first surface thereof test pins for interconnection with external test equipment (including physical interconnections and signal interconnections) in some test scenarios, such as automatic test equipment ATE; a Substrate (SUB) is arranged on the second surface of the printed circuit board, and the Substrate is also called a Multi-Layered Organic (MLO); the substrate is different from a PCB (printed circuit board), and is thin. The probe installing structure is characterized in that a loopback circuit is arranged on the substrate, an installing part for installing a probe is further arranged on the substrate, the loopback circuit comprises an input end and an output end, and the input end and the output end are respectively connected to the installing part.
In a specific loopback test scenario, an input end and an output end of the loopback circuit correspond to a transmitting end and a receiving end of the signal source, which are sometimes referred to as a transmitting end (source end) and a receiving end (sink end).
During testing, after the probe is installed on the installation part, the loopback circuit is interconnected with the IO interface of the DIE through the probe, and then loopback testing can be carried out.
Of course, in some embodiments, the probe card itself is equipped with probes.
It can be understood that, currently, the reliability test of the IO interface is performed by using a test mode of External loop Loopback External Loopback. In the hardware implementation manner, because the loopback circuit is arranged on the PCB, the loopback is generally performed from the chip, the probe of the probe card, the substrate to the multilayer PCB, and then from the multilayer PCB to the chip via the substrate and the probe. The External loopback is carried out based on the loopback mode, and because electronic elements and wiring on the PCB are numerous, loopback test signals are easily influenced by the nearby electronic elements and wiring; in addition, the loopback is carried out on the PCB, and the physical link is longer; signal integrity problems such as reflections, crosstalk, noise, etc. are prone to occur. Even if the interconnection line maintains the perfect precise circuit board layout with the required specific distance and the specific impedance matching, the signal frequency attenuation caused by the signal integrity problems of reflection, crosstalk, noise and the like can only basically reach the IO interface test speed of about 10 Gbps.
The external loopback test routing performed by the probe card according to the embodiment is as follows: the signal is sent from the chip, goes through the probe to the substrate, and then is looped back to the chip receiving end through the probe by the substrate, and the loop-back path is shorter than the loop-back scheme of the existing probe card.
Therefore, the probe card for testing the chip interface provided by the embodiment of the invention has the advantages that the probe card is improved, the loop circuit is arranged on the substrate, the loop circuit is far away from other electronic elements and wiring on the printed circuit board, the distance of the interconnection line in the loop test circuit formed between the transmitting end and the receiving end of the chip interface is shorter, the signal integrity problems of signal reflection, crosstalk, noise and the like in the existing loop test scheme of the probe card can be improved, the high-speed IO interface test speed can be conveniently realized, and the high-speed IO interface of the chip can be conveniently tested.
As shown in fig. 5, some simulation test results prove that the probe card provided by the embodiment of the present invention can achieve a high-speed IO interface hardware test speed of more than 25Gpbs, so as to facilitate the outer loop test of the high-speed IO interface, and improve the reliability of the test.
In this embodiment, as an optional embodiment, the loopback circuit is a differential loopback circuit. The differential loopback circuit is adopted to transmit the high-speed signal to complete the loopback test of the wafer level chip interface, so that the test noise can be reduced, and the electromagnetic interference (EMC and EMI) can be reduced, thereby reducing the error rate and further improving the transmission rate.
Specifically, the differential loopback circuit is an RC (mainly composed of a resistor and a capacitor) differential loopback circuit or an LC (mainly composed of an inductor and a capacitor) differential loopback circuit.
In this embodiment, the loopback test transmitted in the form of differential signals includes a loopback test of a chip interface, and the RC or LC differential loopback circuit is used to suppress common-mode signals, which is helpful to reduce noise and interference.
Referring to fig. 3 and 4, in some embodiments, the differential loopback circuit includes a first differential signal line and a second differential signal line arranged in parallel on a substrate, a first coupling capacitor C1 is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line.
The first differential signal line comprises differential signal lines L2, L9, L11 and L14, and the first coupling capacitor C1 is arranged between the differential signal lines L9 and L11.
The second differential signal line comprises differential signal lines L1, L5, L7 and L13, and the second coupling capacitor C2 is arranged between the differential signal lines L5 and L7.
During loopback test, a pseudo-random code generator inside a chip generates pseudo-random codes, a transmitting end (source end) transmits the pseudo-random codes through a first differential signal line and a second differential signal line in a high-speed differential signal, a first coupling capacitor C1 on the first differential signal line and a first coupling capacitor C2 on the second differential signal line are subjected to Alternating Current (AC) coupling, a direct current component in the differential signal is isolated, the first differential signal and the second differential signal are looped back to a chip receiving end through an output end of a loopback circuit and a probe, and the chip judges whether the data transmitted by a data transmitting end is high level or low level, namely 1 or 0, by comparing the difference value between a first differential signal P and a second differential signal N; and comparing the level value obtained by judgment with a preset expected value, and giving out whether the test result is Pass or Fail based on the comparison result.
In other alternative embodiments, the level value received by the receiving end may be compared with the original pseudorandom code level value transmitted by the transmitting end to determine the bit error rate, and the test result is Pass or Fail based on the bit error rate.
In some conventional probe cards, the chip sending end and the chip receiving end are connected to a probe card substrate in an External short circuit manner to perform Loopback, and the External Loopback test of more than 25Gbps can also be completed. However, it cannot perform a DC characteristic parameter test for high-speed IO at the same time. If DC characteristic parameter testing is required for high-speed IO, a probe card with different functions needs to be designed to complete the testing. Therefore, the test of different functions of the same chip requires the cooperation of two different probe cards to complete the complete reliability test of the loopback test and the DC characteristic test of the high-speed IO interface.
The problem that the chip complete reliability test can be carried out only by designing two probe cards at present is solved. Referring to fig. 3, in this embodiment, as an optional embodiment, when the differential loopback circuit is an RC differential loopback circuit, the differential loopback circuit further includes a third differential signal line and a fourth differential signal line which are arranged in parallel on the substrate, where the third differential signal line includes a first prestage signal line and a first postage signal line, the first prestage signal line is connected to the first end of the first coupling capacitor C1, and the first prestage signal line includes signal lines L3, L10, and L9(L9 and L10 may be combined into one line); the first post-stage signal line is connected to a second end of the first coupling capacitor C1, and comprises signal lines L11, L12 and L16; the first pre-stage signal line is provided with a first resistor R1, and the first post-stage signal line is provided with a second resistor R3.
The fourth differential signal line comprises a second pre-stage signal line and a second post-stage signal line, the second pre-stage signal line is connected to the first end of the second coupling capacitor C2, the second post-stage signal line is connected to the second end of the second coupling capacitor C2, a third resistor R2 is arranged on the second pre-stage signal line, and a fourth resistor R4 is arranged on the second post-stage signal line.
The second front-stage signal line includes signal lines L4, L6, and L5(L5 and L6 may be combined into one line), and the second rear-stage signal line includes signal lines L7, L8, and L15(L7 and L8 may be combined into one line).
When the chip interface DC characteristic parameter test is carried out, an automatic tester ATE is connected to one ends of resistors of a front-stage signal line and a rear-stage signal line of a third differential line and a fourth differential line on a probe card substrate through a test channel corresponding to an interface signal to be tested and a corresponding interconnection line of a probe card PCB, wherein four connecting terminals in a corresponding diagram are TX _ P-CH, RX _ P-CH, TX _ N-CH and RX _ N-CH, signals of TX _ P-CH and TX _ N-CH terminals are a pair (also called a group) of differential signals, and signals of RX _ P-CH and RX _ N-CH terminals are a pair of differential signals; in a direct current test environment, the front-stage signal line and the rear-stage signal line are separated by a coupling capacitor to form four direct current test channels in a switching mode, and each direct current test channel passes through a resistor and then reaches a signal pad end (namely a wafer-level chip end) through a probe to complete interconnection of channels of the DC test environment.
The dc test environment is also referred to as a static parametric test environment. It is understood that in the chip interface testing technology, the chip interface testing is generally divided into static characteristic testing and dynamic characteristic testing, wherein the static characteristic testing is performed in a dc testing environment, and the dynamic characteristic testing is performed in an ac testing environment, which is also referred to as a dynamic characteristic testing environment, because the dynamic characteristic testing needs to test the change of the digital signal.
In fig. 3, for convenience of description, reference numerals are given to signal lines L9 and L10, and signal lines L11 and L12, respectively, and signal lines L9 and L10 are used as a single line for wiring. In some embodiments, the signal lines L9 and L10 are wired in one line; in addition, L5 and L6, L7 and L8, and L11 and L12 are similarly wired, and only one line is wired, respectively.
As shown in FIG. 3, the ATE passes through the TX _ P-CH channel, and through L3, the resistors R1 and L2 reach the TX _ P pad terminal of the chip. The ATE passes through the RX _ P-CH channel, and reaches the RX _ P pad terminal of the chip through L16, resistors R3 and L14. ATE passes through the TX _ N-CH channel, and reaches the TX _ N pad terminal of the chip through L4, resistors R2 and L1. ATE passes through RX _ N-CH channel, through L15, resistors R4, L8 and L13 to the RX _ N pad terminal of the chip.
The probe card provided by this embodiment, through the above-mentioned loop-back circuit, can perform a loop-back test, and when a DC characteristic parameter test is required, can switch to four separate direct current test channels under a direct current test environment according to the characteristics of the capacitor direct current open circuit, so as to facilitate the realization of the purpose of individually testing the DC characteristic parameter of each signal by ATE. Therefore, the probe card provided by the embodiment can not only perform high-speed IO loopback test, but also meet DC characteristic parameter test.
The invention can finish the test effect of the two existing probe cards by one probe card, effectively reduces the cost, saves time for later-stage failure debugging and avoids the problem of difficult failure debugging caused by the adoption of the two probe cards in the later stage.
In addition, as an optional implementation manner, when the complete reliability test of the high-speed IO interface of the chip is performed, the DC characteristic test is performed first, and then the loopback test is performed.
In this embodiment, after the DC characteristic test is finished, physical interconnection with the automatic tester ATE does not need to be disconnected, the ATE sets the loopback test mode, and triggers to switch to the ac test environment required by the loopback test, the first coupling capacitor and the second coupling capacitor show the characteristics of blocking direct current and alternating current and blocking low frequency and high frequency in the ac state, and the impedance of the DC test channel of the ATE increases, at this time, the parasitic capacitors (the parasitic capacitors generally refer to the capacitive characteristics of inductors, resistors, chip loopback pins and the like shown in the high frequency situation) of each resistor in fig. 2 are very small, and then the TX/RX end of the chip is disconnected from the signal of the DC test channel of the ATE, so as to automatically switch into the loopback test environment, so as to facilitate the IO interface test at high speed.
FIG. 4 is a schematic layout diagram of a loopback circuit on a probe card substrate according to an embodiment of the present invention; one layout embodiment of a high speed IO reliability test loopback circuit on a probe card substrate is described. As mentioned above, in order to reduce signal integrity problems such as noise and crosstalk, one countermeasure is that the physical link between the hardware in the test environment should be as short as possible and as far as possible from other wiring, which also places high demands on the wiring of the loopback circuit on the substrate. In some embodiments, TX _ N and TX _ P in the first and second differential signal lines are a pair of differential pairs, and RX _ N and RX _ P are a pair of differential pairs. To avoid the effect of signal integrity problems on high speed IO reliability testing, the differential pair uses 100 ohm impedance matching. When designing wiring, the length of the interconnection wires is as short as possible, the interconnection wires and other signal wires keep the wire spacing more than a multiple, the wiring design is optimized, and layers cannot be changed, namely, the wiring is performed on the same layer of the substrate as much as possible (for the convenience of understanding, the PCB wiring is simply explained, namely, a PCB comprises the substrate, and when wiring, a plurality of layers of flat cables are generally arranged).
In terms of wiring materials, materials with smaller dielectric constants are selected to reduce crosstalk and the like. In the aspect of lamination, each lamination is reasonably distributed, and the distance is optimized.
In addition, the wiring to the ATE instrument, i.e., TX _ N-CH, TX _ P-CH, RX _ N-CH, and RX _ P-CH, needs to be strictly controlled.
According to the probe card provided by the embodiment of the invention, based on the loopback circuit arranged on the probe card substrate, one probe card can finish the test effect of two existing probe cards, the test of the loopback circuit outside the high-speed chip interface hardware with the speed of more than 25Gpbs can be realized, and the test of DC characteristic parameters can be simultaneously carried out. The test and later maintenance cost can be reduced to a certain extent. Furthermore, compared with the prior art which adopts a test scheme of two probe cards, the test method at least reduces the test steps of replacing the probe cards, thereby shortening the test time.
Example two
Based on the probe card provided by the first embodiment, the invention further provides a chip interface testing method, which is suitable for testing the chip high-speed interface.
FIG. 2 is a schematic diagram illustrating an embodiment of a hardware testing environment for wafer level integrated circuit chip testing constructed based on a probe card according to the present invention; FIG. 3 is a schematic circuit topology diagram of an embodiment of a loopback circuit on a probe card substrate according to the present invention; FIG. 6 is a flowchart illustrating a method for testing a chip interface according to an embodiment of the present invention.
Referring to fig. 2, 3 and 6, a chip interface testing method provided in an embodiment of the present invention is implemented based on a probe card described in the first embodiment, and as shown in fig. 2, before testing, a hardware testing environment needs to be established, the probe card is connected to a device for triggering testing through a testing probe on a first surface (i.e., an upper surface in fig. 2), in fig. 2, the device for triggering testing is an automatic tester ATE, the ATE is in contact with a testing probe point on an upper surface of a PCB board of the probe card (i.e., a pad above the PCB) through a testing probe, a probe is installed in an installation portion of a probe card substrate, the probe is fixed through a probe chuck, the probe is used for contacting a probe pad of each testing unit (DUT: device under test), i.e., Die, on a wafer, one testing unit, i.e., Die, an end of the probe is in contact with a Die interface (i.e., a pin) to be tested on the, the die to be tested on the wafer is a so-called wafer-level chip, i.e. an unpackaged chip.
The method comprises the following steps:
step S110, after the test instruction is triggered, the chip sending end sends a loopback test packet to enter the loopback circuit input end on the probe card substrate through the probe;
in this embodiment, after the chip receives the test instruction sent by the ATE device, the internal pseudo-random code generator generates a series of pseudo-random code sequences as a loopback test packet, and sends the loopback test packet to the loopback circuit through the probe.
A pseudo-random code is a sequence code that can be repeatedly generated and copied and has some random sequence random characteristic.
Step S120, the loopback test packet entered into the loopback circuit is looped back to the chip receiving end through the loopback circuit output end.
In this embodiment, because the loopback circuit is located on the probe card substrate, the transmission path of the loopback test packet does not need to pass through the PCB, and only loops back to the chip receiving end through the substrate, the transmission path is shortened, and because the loopback test packet does not pass through the PCB, the number of electronic components and wires on the route (path) is relatively small, thereby being beneficial to reducing the signal integrity problems such as signal reflection, crosstalk and noise.
Step S130, determining the state of the corresponding interface of the chip based on the test packet looped back by the chip receiving end.
And if the test packet does not loop back to the chip receiving end, directly judging that the result is Fail. Furthermore, the state of the corresponding interface of the chip can be determined according to the error rate of the test packet. The state of the corresponding interface of the chip can be determined according to the time from the transmission to the reception of the test packet. In order to highlight the gist of the present invention, it is not exhaustive and detailed how to determine the state of the corresponding interface of the chip.
As shown in fig. 3 or 4, in some embodiments, the test packet is a pseudorandom code; in step S110, the step of sending a loopback test packet from a chip sending end to an input end of a loopback circuit on a probe card substrate through a probe includes: a chip sending end TX _ P sends a pseudo-random code to the loop-back circuit input end L2;
in step S120, the looping back of the loopback test packet entering the loopback circuit to the chip receiving end through the loopback circuit output end includes: and the loopback circuit transmits the pseudo-random code by differential signals and returns the pseudo-random code to the receiving end of the chip through the output end of the loopback circuit.
As shown in fig. 3, the pseudo random code is transmitted as a differential signal, passes through the TX _ P pad and is coupled via the capacitor C1 to the RX _ P terminal; the TX _ N signal is coupled through capacitor C2 to the RX _ N terminal.
With continued reference to fig. 3 and 4, in some embodiments, the differential loopback circuit includes a first differential signal line and a second differential signal line arranged in parallel on a substrate, a first coupling capacitor is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line. The loopback circuit transmits the pseudo-random code in a differential signal and is looped back to a chip receiving end through a loopback circuit output end, and the loopback circuit comprises:
the loop-back circuit transmits pseudo-random code differential signals through a first differential signal circuit and a second differential signal circuit. The first coupling capacitor is used for carrying out alternating current coupling on the pseudo random code differential signal in the first differential signal circuit, filtering out direct current components in the pseudo random code differential signal and then outputting the first differential signal to a chip receiving end.
And the second coupling capacitor is used for carrying out alternating current coupling on the pseudo random code differential signal in the second differential signal circuit, filtering out a direct current component in the pseudo random code differential signal and outputting a second differential signal to a chip receiving end.
In step S130, the determining, by the test packet looped back at the chip receiving end, the state of the corresponding interface of the chip includes:
determining a pseudo-random code level value sent by a chip sending end according to the difference value of the first differential signal and the second differential signal; and comparing the determined pseudo-random code level value with a preset expected value to determine the state of the corresponding interface of the chip.
In this embodiment, when performing an external loopback high-speed test, the high-speed differential signal is AC-coupled through the first and second AC coupling capacitors, and the chip receiving end determines whether the level value sent by the chip sending end is a high level or a low level by comparing the difference between the differential signal P and N, and determines the state of the chip interface based on the comparison between the level value and a preset expected value, and provides a test result based on the result, which is Pass or Fail.
In addition, after the pseudo-random sequence is received, the pseudo-random sequence is tested and compared with a pseudo-random code at a transmitting end, the error rate is determined, and the interface state of the chip is judged based on the error rate.
As shown in fig. 3, in some embodiments, the differential loopback circuit further includes a third differential signal line and a fourth differential signal line disposed in parallel on the substrate, and please refer to embodiment 1 for a detailed description of the circuit topology.
In this embodiment, the device for triggering the test is an automatic test equipment ATE; the method further comprises the following steps: and respectively connecting a first front-stage signal wire and a first rear-stage signal wire of the third differential signal circuit, and a second front-stage signal wire and a second rear-stage signal wire of the fourth differential signal circuit to a direct-current test channel of the automatic tester, and respectively connecting the first differential signal wire and the second differential signal wire with corresponding interfaces of the chip through probes. The first front-stage signal line and the second front-stage signal line form a group of differential signal pairs, and the first rear-stage signal line and the second rear-stage signal line form a group of differential signal pairs.
By utilizing the direct-current open circuit characteristics of the first coupling capacitor and the second coupling capacitor, the loopback test loop is disconnected and switched into four direct-current test loops; and testing the direct current characteristics of the chip interface based on each direct current test loop.
The test method provided by this embodiment is based on the probe card described in the first embodiment, and can not only perform a high-speed IO loopback test, but also satisfy a DC characteristic parameter test, and achieve the effect that the one-card is used for multiple test functions.
In other embodiments, after the dc characteristic test of the chip interface is finished, the method further includes: after receiving a loopback test instruction, switching to a dynamic characteristic test environment; in a dynamic characteristic testing environment, a first resistor, a second resistor, a third resistor and a fourth resistor block signal transmission between a chip transmitting end or a chip receiving end and a direct current channel of an automatic tester; meanwhile, the loopback test circuit is conducted based on the characteristic that the first coupling capacitor and the second coupling capacitor are isolated from direct current and alternating current.
In this embodiment, when the DC characteristic test is finished and the loopback test needs to be performed, the selected loopback test mode trigger instruction is received and switched to the dynamic characteristic test environment, the first coupling capacitor and the second coupling capacitor exhibit the characteristics of blocking direct current and alternating current and blocking low-frequency and high-frequency in the alternating current state, the impedance of the DC test channel of the ATE increases, at this time, the parasitic capacitance (the parasitic capacitance generally refers to the capacitance characteristics exhibited by the inductor, the resistor, the chip pin, and the like in the high-frequency state) of each resistor in fig. 2 is very small, and then the TX/RX end of the chip is disconnected from the DC test channel of the ATE, so that the TX/RX end of the chip is automatically switched to the loopback test environment, thereby facilitating the loopback test of the high-speed.
The chip interface testing method provided by the embodiment of the invention is based on the fact that the differential loopback circuit is arranged on the probe card substrate, solves the problem of signal frequency attenuation caused by the signal integrity problem in the external loopback test, and can carry out the DC characteristic parameter test without changing a probe card.
For the embodiments provided by the present invention, since the embodiments are based on the same or corresponding specific technical concepts, the technical solutions and technical effects thereof are substantially the same, and the related parts can be referred to each other, and are not repeated for clarity and brevity of description.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same or similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments.
For convenience of description, the above relay control system is described separately in terms of functional division into various functional units/circuits/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may also be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A chip interface test probe card is characterized by comprising a printed circuit board, wherein a first surface of the printed circuit board is provided with test needle points, a second surface of the printed circuit board is provided with a substrate, a loopback circuit is arranged on the substrate, an installation part for installing probes is further arranged on the substrate, the loopback circuit comprises an input end and an output end, and the input end and the output end are respectively connected with the installation part.
2. The probe card of claim 1, wherein the loopback circuit is a differential loopback circuit.
3. The probe card of claim 2, wherein the differential loopback circuit is an RC differential loopback circuit or an LC differential loopback circuit.
4. The probe card of claim 2, wherein the differential loopback circuit comprises a first differential signal line and a second differential signal line arranged in parallel on a substrate, a first coupling capacitor is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line.
5. The probe card of claim 4, wherein when the differential loopback circuit is an RC differential loopback circuit, the differential loopback circuit further comprises a third differential signal line and a fourth differential signal line arranged in parallel on the substrate, the third differential signal line comprises a first pre-stage signal line and a first post-stage signal line, the first pre-stage signal line is connected to the first end of the first coupling capacitor, the first post-stage signal line is connected to the second end of the first coupling capacitor, a first resistor is arranged on the first pre-stage signal line, and a second resistor is arranged on the first post-stage signal line;
the fourth differential signal line comprises a second pre-stage signal line and a second post-stage signal line, the second pre-stage signal line is connected to the first end of the second coupling capacitor, the second post-stage signal line is connected to the second end of the second coupling capacitor, a third resistor is arranged on the second pre-stage signal line, and a fourth resistor is arranged on the second post-stage signal line;
when the differential loopback circuit is an LC differential loopback circuit, the resistor in the RC differential loopback circuit is replaced by an inductor.
6. A chip interface testing method, which is implemented based on the probe card of any one of claims 1 to 5, wherein the probe card is connected to a device for triggering a test through a testing pin on a first surface, a probe is installed in an installation part on a substrate of the probe card, an end of the probe is in contact with an interface of a die to be tested on a wafer, and the die to be tested on the wafer is an unpackaged chip;
the method comprises the following steps:
after a test instruction is triggered, a chip sending end sends a loopback test packet to enter a loopback circuit input end on a probe card substrate through a probe;
the loopback test packet entering the loopback circuit is looped back to the chip receiving end through the loopback circuit output end;
and determining the state of the corresponding interface of the chip based on the test packet looped back by the receiving end of the chip.
7. The method of claim 6, wherein the test packet is a pseudo random code based on the probe card implementation of any one of claims 2 to 5;
the chip sending end sends a loopback test packet to enter the loopback circuit input end on the probe card substrate through the probe, and the loopback test packet comprises: the chip sending end sends a pseudo-random code to the input end of the loopback circuit;
the loopback test packet entering the loopback circuit is looped back to the chip receiving end through the loopback circuit output end, and the loopback test packet comprises: and the loopback circuit transmits the pseudo-random code by a differential signal line and returns to the receiving end of the chip through the output end of the loopback circuit.
8. The method of claim 7, wherein the loopback circuit transmitting the pseudo random code in a differential signal line and back to a chip receiving end via a loopback circuit output ring based on the probe card implementation of claim 4 comprises:
the loop-back circuit transmits pseudo-random code differential signals through a first differential signal circuit and a second differential signal circuit;
the first coupling capacitor is used for carrying out alternating current coupling on the pseudo random code differential signal in the first differential signal circuit, filtering out a direct current component in the pseudo random code differential signal and then outputting a first differential signal to a chip receiving end;
the second coupling capacitor is used for carrying out alternating current coupling on the pseudo random code differential signal in the second differential signal circuit, filtering out a direct current component in the pseudo random code differential signal and outputting a second differential signal to a chip receiving end;
the determining the state of the corresponding interface of the chip by the test packet based on the loopback of the receiving end of the chip comprises the following steps:
determining a pseudo-random code level value sent by a chip sending end according to the difference value of the first differential signal and the second differential signal;
and comparing the determined pseudo-random code level value with a preset expected value to determine the state of the corresponding interface of the chip.
9. The method of claim 8, wherein the apparatus for triggering a test is an automatic tester, based on the probe card implementation of claim 5;
the method further comprises the following steps: respectively connecting a first front-stage signal wire and a first rear-stage signal wire of a third differential signal circuit, and a second front-stage signal wire and a second rear-stage signal wire of a fourth differential signal circuit to a direct-current test channel of the automatic tester, and respectively connecting the first differential signal wire and the second differential signal wire with corresponding interfaces of the chip through probes;
by utilizing the direct-current open circuit characteristics of the first coupling capacitor and the second coupling capacitor, the loopback test loop is disconnected and switched into four direct-current test loops;
and testing the direct current characteristics of the chip interface based on each direct current test loop.
10. The method of claim 9, wherein after the dc characteristic test of the chip interface is finished, the method further comprises:
after receiving a loopback test instruction, switching to a dynamic characteristic test environment;
in a dynamic characteristic testing environment, a first resistor, a second resistor, a third resistor and a fourth resistor block signal transmission between a chip transmitting end or a chip receiving end and a direct current channel of an automatic tester;
meanwhile, the loopback test circuit is conducted based on the characteristic that the first coupling capacitor and the second coupling capacitor are isolated from direct current and alternating current.
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| CN113740707A (en) * | 2021-08-20 | 2021-12-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Loopback test circuit of chip interface module |
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