WO2023231121A1

WO2023231121A1 - Package structure as well as manufacturing method therefor, and semiconductor device

Info

Publication number: WO2023231121A1
Application number: PCT/CN2022/102504
Authority: WO
Inventors: 田凯; 李红文; 陈亮; 姜伟
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-06-01
Filing date: 2022-06-29
Publication date: 2023-12-07
Also published as: CN117199055A; TW202308097A

Abstract

Provided in the embodiments of the present disclosure are a package structure as well as a manufacturing method therefor, and a semiconductor device. The package structure comprises: an isolation layer with a plurality of via holes, the via holes exposing parts of an interconnection layer, and the interconnection layer being disposed on a surface of a semiconductor functional structure; N first pads, each first pad being formed by the interconnection layer exposed by one via hole, and N being a positive integer greater than 1; N redistribution layers, each redistribution layer covering the isolation layer and being electrically connected to a corresponding first pad amongst the N first pads; and a first insulating layer, covering and exposing a partial area of each redistribution layer. The exposed partial areas of at least some of the redistribution layers comprise second pads and third pads; the center point of each second pad has the same offset direction and offset distance with respect to the center point of the corresponding first pad; the first pads and the second pads are respectively used for testing when the semiconductor functional structure is at different running speeds; the third pads are used for executing a functional interaction corresponding to the content tested by the second pads.

Description

Packaging structure and manufacturing method thereof, semiconductor device

Related cross-references

This disclosure is based on the Chinese patent application with the application number 202210620813.5, the filing date is June 1, 2022, and the invention name is "Packaging Structure and Manufacturing Method, Semiconductor Device", and claims the priority of the Chinese patent application. The entire contents of the patent application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a packaging structure and a manufacturing method thereof, and a semiconductor device.

Background technique

With the rapid increase in the popularity of electronic equipment and the booming development of the electronic equipment market, electronic products are increasingly required to evolve towards miniaturization and thinness while having high performance, multi-function, high reliability and convenience. Such demand puts forward better, lighter, thinner, higher packaging density, better electrical and thermal performance, higher reliability and higher cost-effectiveness requirements for the packaging of semiconductor devices.

In order to ensure that the performance of semiconductor devices meets corresponding requirements, ports for testing and performing functional interactions need to be prepared on the packaging structure.

Contents of the invention

Based on this, in order to solve one or more of the related technical problems, embodiments of the present disclosure propose a packaging structure, a manufacturing method thereof, and a semiconductor device.

According to an aspect of an embodiment of the present disclosure, a packaging structure is provided, including:

An isolation layer with a plurality of via holes, the isolation layer covers the surface of the interconnection layer, the via holes expose part of the interconnection layer, and the interconnection layer is provided on the surface of the semiconductor functional structure;

N first pads; each first pad is composed of the interconnection layer exposed by one of the via holes; the N is a positive integer greater than 1;

N redistribution layers, each redistribution layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads;

A first insulating layer covers and exposes a partial area of each redistribution layer;

At least part of the exposed partial area of the redistribution layer includes a second pad and a third pad; wherein, the center point of each second pad is relative to the center point of the corresponding first pad. The offset direction and offset distance are equal; the first pad and the second pad are respectively used for testing when the semiconductor functional structure is at different operating speeds, and the third pad is used to perform the same operation as the The content of the second liner test corresponds to the functional interaction.

In the above solution, the N first pads are arranged side by side along the first direction close to the first edge of the semiconductor functional structure;

At least part of the second pads and the corresponding third pads are arranged side by side along a second direction, and the second direction is perpendicular to the first direction.

In the above solution, the orthographic projection of the center point of each second pad on the plane where the interconnection layer is located is offset by a first distance in the second direction relative to the center point of the corresponding first pad. .

In the above solution, the shape of the orthographic projection of the redistribution layer on the plane where the interconnection layer is located includes a strip shape.

In the above solution, part of the first pads are arranged side by side along the first direction close to the first edge of the semiconductor functional structure; part of the second pads and the corresponding third pads are arranged along the second direction. The directions are arranged side by side, and the second direction is perpendicular to the first direction;

The remaining portion of the first pads is arranged side by side in the second direction close to the second edge of the semiconductor functional structure. The first edge and the second edge are two opposite sides of the semiconductor functional structure. edge; the remaining second pads corresponding to the first pads and the third pads are arranged side by side along the first direction.

In the above solution, the orthographic projection of the center point of the second pad on the plane of the interconnection layer is offset by a second distance in the third direction relative to the center point of the corresponding first pad. The angle between the three directions relative to the first direction is 45° or 135°.

In the above solution, the shape of each first pad includes a strip shape, the orthographic projection shape of part of the redistribution layer on the plane where the interconnection layer is located includes an L shape, and the shape of another part of the redistribution layer The shape of the orthographic projection on the plane where the interconnection layer is located includes a Z shape.

In the above solution, the second pad is located at an end of the redistribution layer close to the first pad, and the third pad is located at an end of the redistribution layer away from the first pad.

In the above solution, the redistribution layer is in direct contact with the corresponding first pad;

Alternatively, the packaging structure further includes: a conductive pillar located between the redistribution layer and the corresponding first pad, and the redistribution layer is conductively connected to the interconnection layer through the conductive pillar.

In the above solution, the packaging structure includes the conductive pillar, the orthographic projection of the conductive pillar on the plane where the interconnection layer is located overlaps the first pad, and the conductive pillar is on the location where the interconnection layer is located. The orthographic projection of the plane does not overlap with the orthographic projection of the second pad and the third pad on the plane where the interconnection layer is located.

In the above solution, the rewiring layer is in direct contact with the corresponding first pad, and the packaging structure further includes:

A second insulating layer is located in the groove surrounded by each redistribution layer; the hardness of the material of the second insulating layer is smaller than the hardness of the material of the redistribution layer.

According to another aspect of an embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor functional structure and a packaging structure as described in any one of the above embodiments of the present disclosure.

In the above solution, the semiconductor device further includes:

substrate;

A plurality of stacked die; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure;

Each die is electrically connected to the substrate through leads on a third pad in the package structure.

According to another aspect of the embodiments of the present disclosure, a method for manufacturing a packaging structure is provided, including:

Provide a semiconductor functional structure, the surface of the semiconductor functional structure is provided with an interconnection layer;

An isolation layer is formed with a plurality of via holes, the isolation layer covers the surface of the interconnection layer, the via hole exposes a portion of the interconnection layer, and the portion of the interconnection layer exposed by each via hole serves as a first Pads to form N first pads; the first pads are used to perform the first type of test; the N is a positive integer greater than 1;

After completing the first type of test, N rewiring layers are formed on the N first pads and the isolation layer, and each rewiring layer covers the isolation layer and is connected to the N first pads. A corresponding first pad in the pad is electrically connected;

Form a first insulating layer covering and exposing part of the redistribution layer, and the exposed part of the redistribution layer serves as a second pad and a third pad; wherein, the center point of each second pad The offset direction and offset distance relative to the center point of the corresponding first pad are equal; the second pad is used to perform the second type of test, and the third pad is used to perform the same as the The functional interaction corresponding to the content of the second type of test; the running speed of the semiconductor functional structure when performing the first type of test is lower than the running speed when performing the second type of test.

In various embodiments of the present disclosure, N first pads are provided in the top metal layer to perform testing on the semiconductor functional structure at the first operating speed; the test at the first operating speed is completed. Finally, a second pad corresponding to the first pad is provided in the rewiring layer on the first pad for performing testing on the semiconductor functional structure at the second operating speed; wherein, by The center point of each second pad is set to be offset in the same direction and by an equal distance relative to the center point of the corresponding first pad, so that the N first pads and N second pads remain Exactly the same relative position; in this way, the above two tests of different operating speeds can be achieved through the same set of probe cards. Compared with using two sets of probe cards to conduct tests separately, the test cost and test time can be saved, thereby reducing production Cycle time and manufacturing costs.

Description of the drawings

Figure 1 is a schematic cross-sectional view of a packaging structure provided in an embodiment of the present disclosure;

Figure 2a is a schematic cross-sectional view of another packaging structure provided in an embodiment of the present disclosure;

Figure 2b is a schematic cross-sectional view of a packaging structure with conductive pillars provided in an embodiment of the present disclosure;

Figure 3a is a schematic diagram of the relative positions of a single row of first pads and a single row of second pads provided in an embodiment of the present disclosure;

Figure 3b is an enlarged view of part of the area in Figure 3a;

4a-4c are schematic diagrams of the relative positions of a T-shaped arrangement of first pads and a T-shaped arrangement of second pads provided in an embodiment of the present disclosure;

Figure 5 is a schematic flow chart of a manufacturing method of a packaging structure provided in an embodiment of the present disclosure;

6a-6d are schematic diagrams of a manufacturing process of a packaging structure provided in an embodiment of the present disclosure.

Explanation of reference signs

101-Top metal layer; 102-First type liner; 103-Rewiring layer; 104-Second type liner; 105-Third type liner; 200-Semiconductor functional structure; 201-Semiconductor functional layer; 202- Interconnect layer; 203-isolation layer; 204-via hole; 205-first pad; 206-rewiring layer; 207-conductive pillar; 208-first insulating layer; 209-groove; 210-second insulating layer ; 211-second pad; 212-third pad; 600-semiconductor functional structure; 601-semiconductor functional layer; 602-interconnect layer; 603-isolation layer; 604-via; 605-first pad; 606-rewiring layer; 608-first insulating layer; 609-groove; 610-second insulating layer; 611-second pad; 612-third pad.

In the above-described drawings (which are not necessarily to scale), similar reference characters may describe similar components in the different views. Similar reference numbers with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example, and not limitation.

Detailed ways

The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

Various embodiments of the present disclosure are described in more detail by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present disclosure.

It will be understood that the meanings of "on," "over," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" does not only mean its "On" something without intervening features or layers (i.e. directly on something), and also includes being "on" something with intervening features or layers.

In the embodiment of the present disclosure, the term "A and B are connected" includes the situation where A and B are in direct contact, or the situation where A and B are in indirect contact through an intermediate conductive structure.

In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend on the lower or upper surface of the structure and may have an area less than or equal to the surface on which it extends. It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily as long as there is no conflict.

The semiconductor functional structure involved in the embodiments of the present disclosure is a part that will be used in subsequent processes to form the final semiconductor device, and is a core part for realizing the main functions of the semiconductor device. Here, the final semiconductor device may include, but is not limited to, a memory.

In the design of the packaging structure of semiconductor devices such as dynamic random access memory (DRAM, Dynamic Random Access Memory), there are two ways to set the pads (also called pads, expressed in English as PAD): one is The top metal window opening method; the other is the redistribution layer (RDL, Redistribution Layer) window opening method.

The top metal window opening refers to forming a passivation layer (Passivation) or an insulating layer on the top metal layer of the semiconductor functional structure to protect the semiconductor functional structure from being damaged; then, forming a passivation layer or insulating layer on the passivation layer or the insulating layer Window areas to expose part of the top metal layer to form a pad. Among them, probe clamping needle testing can be performed on the pad to test the electrical properties of the semiconductor functional structure; bonding wires can also be drawn out on the pad to test the semiconductor function. Electrical extraction from the structure.

The rewiring layer opening refers to forming a rewiring layer on the top metal layer of the semiconductor functional structure, forming a passivation layer or an insulating layer on the rewiring layer, and then forming an opening on the passivation layer or insulating layer. window area to expose part of the rewiring layer, forming two pads placed side by side. One of the two pads is used for probe clamping pin testing, and the other is used for drawing out bonding wires on the pad. Here, the rewiring layer can play the role of adjusting the pad position in the semiconductor device, and can also play the role of enhancing the power supply network of the power ground.

It is understandable that the top metal layer is relatively thin, and there is a gasket structure underneath, which can support the same windowed metal area. It is first tested by the probe clamping needle, and then the bonding wire is packaged in the packaging factory. Affects the yield of package wiring; the material of the rewiring layer is generally metal. The rewiring layer is thicker than the top metal layer. After the probe pin is stuck, there will be deep and rough needle marks on the surface. This needle mark will affect Yield of package bonding, so the pads in the redistribution layer for testing and for bringing out the bond wires need to be separated. No matter which of the above windowing methods is used in the packaging structure, it will not have much impact on the function of the semiconductor device. Windowing on the rewiring layer will help improve performance, but it will increase the production cycle and production cost.

In the related art, one of the above two window opening methods is generally selected to design the packaging structure according to the actual needs of the semiconductor device. However, in practical applications, in the production process of semiconductor devices, the demand is not single, and there are often multiple demands. Here are some examples of multiple requirements:

For example, before the mass production of semiconductor devices (or "products"), there is a long functional debugging process. During this debugging process, testing is completed when the semiconductor functional structure runs at a low speed. At this time, only the top metal window opening method is needed to complete the packaging and testing of the semiconductor functional structure. After the product's manufacturing process matures, when it is necessary to test the state of the semiconductor functional structure under high-speed operation, the rewiring layer windowing method needs to be used for packaging testing.

For example, when the semiconductor functional structure itself has different functional requirements, the same semiconductor functional structure can be divided into standard level testing and advanced level testing according to different needs. Different testing levels also have different requirements for the windowing method of the semiconductor functional structure. When conducting standard-level testing of semiconductor functional structures, the top metal window can be used for packaging and testing, and the role of the rewiring layer is not obvious; when conducting advanced-level testing of semiconductor functional structures, rewiring layer openings need to be used. Encapsulation and testing are carried out through windows to improve product performance.

Based on this, embodiments of the present disclosure provide a packaging structure. Referring to Figure 1, the packaging structure includes a top metal window opening method and a rewiring layer window opening method; wherein, in the top metal window opening method, in the top metal layer A first type of pad 102 is provided in 101; the first type of pad 102 can be used to perform low-speed testing and lead out bonding wires; in the rewiring layer windowing method, two types of pads are provided in the rewiring layer 103 (Second type pad 104 and third type pad 105), the second type pad 104 is used to perform high-speed testing, and the third type pad 105 is used to lead out bonding wires. In this way, in the embodiments of the present disclosure, a packaging structure compatible with two types of tests (low-speed test and high-speed test) is used to meet the needs of semiconductor functional structures for different types of tests at different process stages, improve the flexibility of testing, and reduce the cost of testing. Production cycle time and manufacturing costs.

Here, when using the first type of pads 102 to perform a low-speed test, the test probe card needs to hit the center points of all the first type of pads 102 at the same time. When using the second type of pads 104 to perform a high-speed test, the test probe card needs to The needle card needs to be hit at the center point of all the second type pads 104 at the same time. However, it can be seen from FIG. 1 that the first type pads 102 and the second pads 104 are in different layers of the packaging structure, and the relative positions of the first type pads 102 and each second pads 104 in different layers are different. In this way, in order to meet the needs of low-speed testing and high-speed testing, two sets of test probe cards have to be made, and making two sets of test probe cards will greatly increase the test cost and test time.

Based on this, embodiments of the present disclosure provide a packaging structure, a manufacturing method thereof, and a semiconductor device, wherein the packaging structure includes: an isolation layer with a plurality of via holes, and the isolation layer covers the surface of the interconnection layer , the via hole exposes part of the interconnection layer, and the interconnection layer is provided on the surface of the semiconductor functional structure; N first pads; each first pad consists of a portion of the interconnection layer exposed by one of the via holes. It is composed of connected layers; the N is a positive integer greater than 1; N rewiring layers, each rewiring layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads. ; The first insulating layer covers and exposes a partial area of each redistribution layer; at least part of the exposed partial area of the redistribution layer includes a second pad and a third pad; wherein, each The offset direction and offset distance of the center point of the second pad relative to the center point of the corresponding first pad are equal; the first pad and the second pad are respectively used for the semiconductor function When the structure is tested at different running speeds, the third pad is used to perform functional interaction corresponding to the content of the second pad test.

Here, referring to Figure 2a, the packaging structure includes:

A substrate (not shown in Figure 2a). The constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (SOI) or germanium on insulator (SOI). Germanium on Insulator, GOI).

Semiconductor functional structure 200, the semiconductor functional structure 200 is located on a substrate; specifically, the semiconductor functional structure 200 includes a semiconductor functional layer 201 and an interconnection layer 202 located on the surface of the semiconductor functional layer 201. According to actual needs, A variety of functional structures can be provided in the semiconductor functional layer 201; accordingly, the interconnection layer 202 is used to extract electrical signals from the functional structures in the semiconductor functional layer 201 to run the functional structures. In some embodiments, the interconnect layer 202 includes a top metal layer, which is used not only to extract electrical signals from the functional structure, but also to support the semiconductor functional structure 200 .

It should be noted that any signals connected to the rewiring layer formed in subsequent processes are connected to the interconnection layer 202 , which ensures that the function of the semiconductor functional structure 200 is complete without the rewiring layer. Figure 2a shows a cross-sectional rendering of a section after the interconnection layer 202 has been partially removed. In practical applications, each part of the interconnection layer is not cut off, but interconnected, that is, in other sections , the parts in the interconnection layer may be continuous.

The isolation layer 203 covers the surface of the interconnection layer 202 and is used to isolate the interconnection layer 202 and the subsequently formed rewiring layer 206 in some areas. A via hole 204 is provided in the isolation layer 203, and the via hole 204 exposes a portion of the interconnection layer 202. The shape of the via hole 204 may be cylindrical, inverted trapezoidal, or any suitable shape; the composition material of the isolation layer 203 includes but is not limited to tetraethylorthosilicate (TEOS).

The first pad 205 is composed of the interconnection layer 202 exposed by one via hole 204; the isolation layer 203 may contain multiple via holes 204, thereby forming a plurality of first pads exposed by the via hole 204. MAT 205. Here, on the one hand, the first pad 205 can be used to perform the first type of test; on the other hand, it can also be used to perform functional interaction corresponding to the content of the first type of test. For example, the first type of tests can be understood as some tests performed on the semiconductor functional structure at a lower operating speed. It should be noted that in memory, the operating speed refers to the read and write speed of the memory. The execution of the functional interaction corresponding to the contents of the first type of test may be understood as drawing out a bonding wire on the first pad. That is to say, when performing the first type of test, the first pad 205 can be used to contact the probe card, and the multiple probes in the probe card correspond to the N first pads in a one-to-one manner to achieve interaction. electrical connections to other test systems.

Referring to Figure 2a, a redistribution layer 206 is located on the surface of the isolation layer 203 and within the via hole 204. Here, the redistribution layer 206 covers the isolation layer 203; and the redistribution layer 206 is in direct contact with the corresponding first pad 205. In other words, each first pad 205 can serve as an area where a corresponding redistribution layer 206 is electrically connected to the interconnection layer 202 .

The constituent material of the redistribution layer 206 includes but is not limited to metal; preferably, the material of the redistribution layer 206 is aluminum (Al).

The redistribution layer 206 and the first pad 205 may be in direct contact (refer to Figure 2a); they may also be in indirect contact, that is, a conductive material layer is provided between the redistribution layer 206 and the first pad 205 (refer to Figure 2b) .

In some embodiments, the redistribution layer is in direct contact with the corresponding first pad; or, the packaging structure further includes: a conductive pillar 207 located between the redistribution layer 206 and the corresponding first pad. Between the pads 205 , the redistribution layer 206 is conductively connected to the interconnection layer 202 through the conductive pillars 207 .

The conductive pillar 207 may be made of the same material as the redistribution layer 206 , or may be different. For example, the conductive pillar 207 is made of aluminum (Al), copper (Cu), etc. It should be noted that the height of the conductive pillar 207 may be less than or equal to the depth of the via hole 204. What is shown in FIG. 2b is the case where the height of the conductive pillar 207 is equal to the depth of the via hole 204.

It should be noted that what is shown in Figure 2b is a cross-sectional rendering after the conductive pillars 207 are filled with the via holes 204. In actual applications, the conductive pillars 207 can also be provided in other shapes or at other positions, or in other words, the conductive pillars 207 can be arranged in other shapes or at other positions. The shape is reciprocal with the shape of the via hole 204 , that is, the conductive pillar 207 fills the via hole 204 .

Here, the orthographic projection of the conductive pillar 207 on the plane where the interconnection layer 202 is located overlaps the first pad 205 .

That is to say, the conductive pillar 207 is located directly above the first pad 205, which is beneficial to the transmission of electrical signals between the semiconductor functional structure 200 and the redistribution layer 206.

In the above embodiment, the number of the conductive pillars 207 in the same via hole 204 may include one or multiple, and adjacent conductive pillars 207 are separated by insulating materials; accordingly, each conductive pillar 207 corresponds to a first pad 205 , that is, when the number of conductive pillars 207 is multiple, the bottom of the same via hole 204 has multiple first pads 205 .

It can be understood that when the number of conductive pillars 207 includes multiple, multiple conductive pillars 207 are connected to the redistribution layer 206 and the interconnection layer 202. In this way, the number of electrical connections between the redistribution layer 206 and the interconnection layer 202 can be increased. reliability. In other words, in a package structure with multiple conductive pillars 207, if a certain conductive pillar fails to electrically connect the redistribution layer 206 and the interconnection layer 202, other remaining conductive pillars can also connect the redistribution layer and the interconnection layer 202. The interconnection layers are connected, thereby improving the reliability of electrical connections between the redistribution layer, the conductive pillars, and the interconnection layers.

It can be understood that by providing multiple first pads 205 while the bottom area of the via hole remains unchanged, it is beneficial to reduce the total area of all first pads 205 at the bottom of the same via hole 204, thereby reducing the third The parasitic capacitance between the pad 205 and the surrounding conductive material is conducive to further optimizing the signal transmission performance.

It can be understood that by directly disposing the redistribution layer 206 in the via hole 204 , that is, the redistribution layer 206 is in direct contact with the first pad 205 , or only forming one conductive pillar 207 in the via hole 204 , the formation of the conductive pillar 207 can be reduced. process flow, thereby improving process efficiency.

Referring to Figure 2a, a first insulating layer 208 is located on the redistribution layer 206.

The first insulating layer 208 covers the surface of the redistribution layer 206. On the one hand, it can be used to isolate the electrical connection between the redistribution layer 206 and other conductive materials. On the other hand, it can be used to protect the redistribution layer 206 from being damaged. The material of the first insulating layer 208 includes but is not limited to polyimide (PI).

It should be noted that the thickness of the redistribution layer 206 on the exposed portion of the interconnection layer 202 and the thickness of the redistribution layer 206 on the surface of the isolation layer 203 may be the same. In some embodiments, when the diameter width of the via hole 204 is greater than twice the thickness of the redistribution layer 206 , the redistribution layer 206 covers the sidewalls and bottom of the via hole 204 , and the redistribution layer 206 is surrounded by a groove 209 .

In some embodiments, referring to FIG. 2a, the redistribution layer is in direct contact with the corresponding first pad. The packaging structure further includes: a second insulating layer 210 located around each redistribution layer. in the groove 209; the hardness of the material of the second insulating layer 210 is less than the hardness of the material of the rewiring layer 206. In this way, on the one hand, the stress of the packaging structure can be reduced and the reliability of the packaging structure can be increased; on the other hand, On the other hand, compared with filling the groove 209 with the redistribution layer 206, filling the groove 209 with the material of the second insulating layer 210 can avoid generating more parasitic capacitance.

In some embodiments, the second insulating layer 210 may be made of the same material as the first insulating layer 208 , or the material of the second insulating layer 210 may have a hardness less than the material of the first insulating layer 208 , thereby further reducing the structure. stress. Exemplarily, the constituent material of the second insulating layer 210 includes but is not limited to polyimide (PI). In some embodiments, the second insulating layer 210 and the first insulating layer 208 may also have an integrated structure.

Referring to FIG. 2a , a partial area of the first insulating layer 208 is removed, so that at least part of the exposed partial area of the N redistribution layers 206 includes the second pad 211 and the third pad. 212.

Here, one second pad 211 and one third pad 212 are provided in each of the N redistribution layers 206; in other words, N second pads 211 and N third pads 212 One-to-one correspondence. The second pad 211 is used to perform a second type of test, and the third pad 212 is used to perform functional interaction corresponding to the content of the second type of test. The second type of tests can be understood as tests performed on semiconductor functional structures at higher operating speeds. The execution of the functional interaction corresponding to the content of the second type of test can be understood as drawing out a bonding wire on the third pad.

In other words, the redistribution layer 206 is used to redistribute the wire paths laid out based on the first pad 205; here, the redistributed wire paths are more conducive to electrical testing and functional interaction of semiconductor devices.

It should be noted that the second liner 211 and the third liner 212 may be continuously arranged, that is, there is no partition wall between the second liner 211 and the third liner 212; they may also be arranged at intervals. , that is, a partition wall is provided between the second pad 211 and the third pad 212 .

Here, when the second pad 211 and the third pad 212 are continuously arranged, during the test process, damage to the probe card caused by the partition wall when the probe is not aimed can be avoided, thus The service life of the probe card is extended; at the same time, the generation of impurities is reduced, thereby improving the test efficiency; in addition, the damage of the probe card to the partition wall is reduced, thereby improving the overall reliability of the packaging structure.

When a partition wall is provided between the second pad 211 and the third pad 212, the recognition accuracy of each pad by the machine can be improved during the test.

In the following embodiments, a partition wall is provided between the second liner 211 and the third liner 212 as an example for description. However, it can be understood that the following description of the partition wall is only used to illustrate the present invention and is not intended to be used. limit the scope of the invention.

In some embodiments, the packaging structure further includes: a conductive pillar, the orthographic projection of the conductive pillar on the plane where the interconnection layer is located is the same as the position of the second pad and the third pad on the plane where the interconnection layer is located. Orthographic projections of planes do not overlap. In this way, the distance between the conductive pillar and the second pad or the third pad can be increased, thereby reducing the stress damage caused by the conductive pillar to the second pad or the third pad.

In some embodiments, the second pad 211 is located at an end of the redistribution layer 206 close to the first pad 205 , and the third pad 212 is located in the redistribution layer 206 away from the first pad 205 . One end of the first pad 205.

Here, when using the same set of probes to perform the first type test and the second type test, setting the position of the second pad relatively close to the corresponding first pad can reduce the number of probe cards of the same set. Moving distance can improve testing efficiency and reduce the probability of errors.

In order to facilitate the probe card to perform the second type of test, each probe in the probe card can correspond to the second pad. In the embodiment of the present disclosure, the center of each second pad 211 is The points are offset in the same direction and by the same distance relative to the center point of the corresponding first pad 205. In this way, the N first pads and the N second pads can maintain exactly the same relative position. In this way, after performing the first type test, the same set of probe cards can be aligned with the center points of all second pads 211 after moving a certain distance from the center point of the first pad 205 in a certain direction. Accurate, that is, the probe card can directly perform the second type test on all the second pads that need to be tested without replacing a new probe card. Hereinafter, the position setting method of the first pad and the second pad will be specifically described through two examples.

In some embodiments, the N first pads 205 are all juxtaposed along the first direction close to the first edge of the semiconductor functional structure; at least part of the second pads are aligned with the corresponding first pads 205 . The three pads are all arranged side by side along a second direction, and the second direction is perpendicular to the first direction.

It should be noted that in this application example, when there are not many points to be tested and the number of corresponding first pads is not too many, all the first pads can be arranged in parallel close to the edge of the semiconductor. , that is, all the first pads are arranged in a single row; accordingly, the rewiring layer is also disposed close to the edge of the semiconductor, which can reduce the length of subsequent bonding wires.

Here and below, the first direction is parallel to the surface of the semiconductor functional structure and the second direction is parallel to the semiconductor functional structure and perpendicular to the first direction. In some embodiments, the first direction may be parallel to the X-axis direction, and the second direction may be parallel to the Y-axis direction. In other embodiments, the first direction may be parallel to the Y-axis direction, and the second direction may be parallel to the X-axis direction. In the following and the accompanying drawings, the description is only given as an example in which the first direction is parallel to the X-axis direction and the second direction is parallel to the Y-axis direction.

Here, the first edge may generally refer to any edge of the semiconductor functional structure.

Exemplarily, with reference to Figure 3a, the left side of the arrow in Figure 3a shows three first pads 205 arranged side by side along the X-axis direction near the first edge of the semiconductor functional structure; the right side of the arrow in Figure 3a It shows that three redistribution layers are arranged side by side in the X-axis direction close to the first edge of the semiconductor functional structure. At the same time, the second pad and the corresponding third pad in the redistribution layer are both arranged in the Y-axis direction. Arranged side by side; the dotted line in Figure 3a shows the straight line where the center points of the three first pads 205 are located.

In some embodiments, the first liner 205, the second liner 211, and the third liner 212 are all strip-shaped, and the width of each first liner 205 along the first direction is consistent with each other. The width of the second liner 211 and the third liner 212 along the first direction is the same, and the length of each first liner 205 along the second direction is the same as that of each of the second liner 211 and the third liner. Pads 212 vary in length along the second direction. In some specific examples, the size of the first liner 205 is 45 μm×60 μm, and the sizes of the second liner 211 and the third liner 212 are both 45 μm×55 μm.

In some embodiments, the orthographic projection of the center point of each second pad on the plane where the interconnection layer is located is offset in the second direction relative to the center point of the corresponding first pad. A distance.

Here, the first distance is the distance that the probe card moves from the center point of the first pad to the center point of the second pad after completing the first type of test.

For example, referring to FIG. 3a , the center point O ₂ of each second pad is offset by a first distance H1 in the Y-axis direction relative to the center point O ₁ of the corresponding first pad.

In some embodiments, the shape of each redistribution layer 206 in the orthographic projection of the plane where the interconnection layer is located includes a strip shape.

For example, referring to FIG. 3b , the shape of each redistribution layer 206 includes a strip shape in the orthographic projection of the plane where the interconnection layer is located. In addition, it can be seen from Figure 3b that when the packaging structure includes the conductive pillar, the orthographic projection of the conductive pillar on the plane where the interconnection layer is located overlaps the first pad, and the conductive pillar is on The orthographic projection of the plane where the interconnection layer is located does not overlap with the orthographic projections of the second pad and the third pad on the plane where the interconnection layer is located.

In other embodiments, part of the first pads are juxtaposed along the first direction close to the first edge of the semiconductor functional structure; part of the second pads and the corresponding third pads Arranged side by side along a second direction, the second direction being perpendicular to the first direction;

It should be noted that in this application example, when there are many points to be tested, the number of corresponding first pads is relatively large. At this time, a single row arrangement may not be able to arrange all the first pads. In this case, the first pads A pad can be arranged like a T-shape.

Here, the first edge 20a and the second edge 20b are two opposite edges of the semiconductor functional structure.

Here, the N first pads are divided into two parts, namely the first part and the second part; wherein the first part includes M1 first pads; the M1 first pads in the first part are along the first The second part includes M2 first pads; the M2 first pads in the second part are arranged side by side along the second direction. A position close to the second edge of the semiconductor functional structure. Here, M1+M2=N.

Correspondingly, the N second pads are divided into two parts, namely a third part and a fourth part; wherein the third part includes M1 second pads; the fourth part includes M2 second pads; The M1 second pads in the third part are arranged side by side in the first direction close to the first edge of the semiconductor functional structure; the M2 second pads in the fourth part are arranged in parallel along the second direction. arranged in parallel at a position close to the second edge of the semiconductor functional structure. Similarly, the N third pads are divided into two parts, namely the fifth part and the sixth part; wherein the fifth part includes M1 third pads; the sixth part includes M2 third pads; M1 third pads and M1 second pads in the fifth part are arranged side by side along the first direction close to the first edge of the semiconductor functional structure; M2 third pads in the sixth part and M2 second pads are arranged side by side along the first direction close to the second edge of the semiconductor functional structure.

Exemplarily, referring to FIG. 4a, the left side of the arrow in FIG. 4a shows three first pads 205 arranged side by side in the X-axis direction close to the first edge of the semiconductor functional structure. At the same time, the two first pads 205 are The pads 205 are juxtaposed along the Y-axis direction near the second edge of the semiconductor functional structure; the right side of the arrow in Figure 4a shows three redistribution layers juxtaposed along the X-axis direction near the first edge of the semiconductor functional structure. At the edge, the second pad and the corresponding third pad in the three redistribution layers are arranged side by side along the Y-axis direction. At the same time, the two rewiring layers are arranged side by side along the Y-axis direction close to the semiconductor function. At the position of the second edge of the structure, the second pads and the corresponding third pads in the two redistribution layers are arranged side by side along the X-axis direction; the dotted line in Figure 3a shows the three first pads 205 The straight line where the center point is.

It can be understood that the second pad disposed close to the second edge of the semiconductor functional structure and the corresponding third pad disposed side by side along the X-axis direction can reduce the risk of the redistribution layer exceeding the second edge.

It should be noted that the first pads arranged parallel to the second edge of the semiconductor functional structure along the Y-axis direction may also be parallel to the first pad arranged close to the first edge of the semiconductor functional structure along the X-axis direction. The shape of the first pad at the position is exactly the same (as shown in Figure 4b), and can also be compared with the shape of the first pad arranged side by side in the X-axis direction close to the first edge of the semiconductor functional structure. The center point is rotated 90° (as shown in 4a).

In some embodiments, the orthographic projection of the center point of the second pad on the plane where the interconnection layer is located is offset by a second distance in the third direction relative to the corresponding center point of the first pad, so The angle between the third direction and the first direction is 45° or 135°. In other embodiments, the angle between the third direction and the first direction is 0° to 45° or 135° to 180°, such as 15°, 30°, 150° and 165°.

Here, the second distance is the distance that the probe card moves from the center point of the first pad to the center point of the second pad after completing the first type of test.

For example, referring to Figure 4a or 4b, the center point _O2 of each second pad is offset by a second distance H2 in three directions relative to the center point _O1 of the corresponding first pad, so The third direction is parallel to the surface of the semiconductor functional structure, and the angle α between it and the first direction is 45° or 135°.

It can be understood that when the angle α between the third direction and the first direction is 45° or 135°, in other embodiments, the angle α between the third direction and the first direction is 0˜45°. Or 135°~180°, such as 15°, 30°, 150° and 165°, which can be compatible with changes in two mutually perpendicular directions at the same time, thereby ensuring that the center point of the second pad arranged in a T-shape is relative to the corresponding position. The offset direction and offset distance of the center point of the first pad are equal.

In some embodiments, the shape of each of the first pads includes a strip shape, the orthographic projection of part of the redistribution layer on the plane of the interconnection layer includes an L shape, and the shape of another part of the redistribution layer includes an L shape. The shape of the orthographic projection of the wiring layer on the plane where the interconnection layer is located includes a Z shape.

For example, referring to FIG. 4c, the shape of the orthographic projection of some of the N redistribution layers on the plane where the interconnection layer is located includes an L shape.

For example, referring to FIG. 4a or 4b, the multiple redistribution layers located close to the second edge 20b of the semiconductor functional structure are all Z-shaped in the orthographic projection of the plane where the interconnection layer is located.

According to another aspect of the embodiments of the disclosure, a semiconductor device is provided, including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the disclosure.

In some embodiments, the semiconductor device further includes: a substrate; a plurality of stacked die; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure; each die passes Leads on the third pad in the package structure are electrically connected to the substrate.

According to another aspect of the embodiment of the present disclosure, a method for manufacturing a packaging structure is provided. As shown in Figure 5, the method of manufacturing a packaging structure provided by the embodiment of the present disclosure includes the following steps:

Step S501: Provide a semiconductor functional structure, the surface of which is provided with an interconnection layer;

Step S502: Form an isolation layer with a plurality of via holes, the isolation layer covers the surface of the interconnect layer, the via holes expose part of the interconnect layer, and the part of the interconnect layer exposed by each via hole serves as One first pad, forming N first pads; the first pads are used to perform the first type of test; the N is a positive integer greater than 1;

Step S503: After completing the first type of test, form N rewiring layers on the N first pads and the isolation layer, and each rewiring layer covers the isolation layer and is connected to the N rewiring layers. One of the first pads is electrically connected to a corresponding first pad;

Step S504: Form a first insulating layer covering and exposing part of the redistribution layer, and the exposed part of the redistribution layer serves as a second pad and a third pad; wherein each of the second pads The offset direction and offset distance of the center point of the corresponding first pad are equal; the second pad is used to perform the second type of test, and the third pad is used to perform Functional interaction corresponding to the content of the second type of test; the operating speed of the semiconductor functional structure when performing the first type of test is lower than the operating speed when performing the second type of test.

It should be understood that the steps shown in Figure 5 are not exclusive, and other steps can also be performed before, after, or between any steps in the operations shown; the order of the steps shown in Figure 5 can be adjusted according to actual needs. 6a to 6d are schematic cross-sectional views of a manufacturing process of a packaging structure provided by an embodiment of the present disclosure. The manufacturing method of the packaging structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 5 and FIG. 6 a to FIG. 6 d.

In step S501, referring to FIG. 6a, a semiconductor functional structure 600 is provided, which includes a semiconductor functional layer 601 and an interconnection layer 602. The providing a semiconductor functional structure 600 includes: providing a substrate (not shown in FIG. 6a), forming a semiconductor functional layer 601 on the substrate, and forming an interconnect layer 602 on the semiconductor functional layer.

Specifically, the semiconductor functional layer 601 includes a single layer or a multi-layer film, and the semiconductor functional layer has a conductive layer and/or a dielectric layer. According to actual needs, a variety of functional structures can be provided in the semiconductor functional layer 601; accordingly , the interconnection layer 602 is used to extract electrical signals from the functional structures in the semiconductor functional layer 601 to run the functional structures. In some embodiments, the interconnect layer 602 includes a top metal layer that is used not only to extract electrical signals from the functional structure but also to support the semiconductor functional structure 600 .

Here, the interconnection can be formed on the semiconductor functional layer by physical vapor deposition (PVD, Physical Vapor Deposition), chemical vapor deposition (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition), etc. layer.

In some embodiments, the method further includes: removing part of the interconnection layer 602 and reducing the area of the interconnection layer to reduce parasitic capacitance generated by the interconnection layer. Figure 6a shows a cross-sectional rendering of a section after the interconnection layer 602 has been partially removed. In practical applications, the parts in the interconnection layer are not cut off, but interconnected, that is, in other sections , the parts in the interconnection layer may be continuous.

In step S502, referring to FIG. 6b, an isolation layer 603 is formed on the interconnection layer 602. The constituent materials of the isolation layer include but are not limited to ethyl orthosilicate. Methods for forming the isolation layer include but are not limited to PVD, CVD, ALD and other processes.

Next, a portion of the isolation layer is removed to form a plurality of via holes 604 . The via hole exposes a portion of the interconnect layer, and each via hole exposes a portion of the interconnect layer as a first pad 605 to form N first pads 605 . Wherein, the via hole 604 may be cylindrical, inverted trapezoidal, or any suitable shape, and the cross-sectional area of the via hole includes the area of the orthographic projection of the via hole on the plane where the interconnected layer is located. , for example, when the via hole is an inverted trapezoid, the cross-sectional area of the first pad is the minimum cross-sectional area of the via hole.

The first pad 605 can be used to perform the first type of test; it can also be used to perform functional interactions corresponding to the contents of the first type of test, such as drawing out bonding wires. The first type of tests can be understood as tests performed on semiconductor functional structures at lower operating speeds. It should be noted that in memory, the operating speed refers to the read and write speed of the memory.

In step S503, referring to FIG. 6c, a rewiring layer 606 is formed in the isolation layer 603 and the via hole 604.

The specific method of forming the redistribution layer 606 on the isolation layer 603 includes: forming a new conductor pattern on the isolation layer by exposure and development, and then using electroplating technology to form a redistribution layer 606 according to the new conductor pattern. A wiring layer, the rewiring layer includes a new wire path, and the new wire path is conductively connected to the interconnection layer. In other embodiments, the redistribution layer 606 can also be formed on the first pad 605 and the isolation layer 603 through a maskless deposition process. The maskless deposition process can be understood as forming a redistribution layer directly on the first pad and isolation layer without forming a mask.

In step S504, referring to FIG. 6d, a first insulating layer 608 is formed on the redistribution layer 606.

Here, the method of forming the first insulating layer 608 includes but is not limited to PVD, CVD, ALD and other processes; the removal process includes but is not limited to etching process.

Next, a portion of the first insulating layer 608 is removed to expose a portion of the redistribution layer 606. Here, the exposed portion of the redistribution layer includes a second pad 611 and a third pad 612, wherein the The second pad 611 is used to perform a second type of test, and the third pad 612 is used to perform functional interactions corresponding to the content of the second type of test. The second type of test can be understood as testing the semiconductor functional structure. Some tests are performed at higher operating speeds. The functional interaction corresponding to the content of the second type of test can be understood as drawing out bonding wires on the third pad. Here, the second pad 611 and the third pad The position of the pad 612 can be selected and set according to actual needs.

It should be noted that in this embodiment, referring to FIG. 6d, the first insulating layer not only exposes part of the redistribution layer to form the second pad and the third pad, but also exposes the redistribution layer located above the first pad. wiring layer to fill the subsequent second insulating layer 610 in the groove 609 formed by the rewiring layer. At this time, the density of the second insulating layer may be less than or equal to the first insulating layer; in other embodiments, the first insulating layer It also covers the bottom surface and sidewalls of the groove 609 formed by the redistribution layer, and subsequently the second insulating layer 610 is formed in the groove 609 formed by the first insulating layer.

It should be noted that the second insulating layer may be made of the same material as the first insulating layer. Correspondingly, the second insulating layer may be formed in the same process step of forming the first insulating layer, and the second insulating layer may be made of the same material as the first insulating layer. One insulation layer is an integrated structure.

In other embodiments, the packaging structure further includes conductive pillars. Correspondingly, the method further includes: after completing the first type of test, forming conductive pillars on the first pad; Forming a redistribution layer on the first pad and the isolation layer includes: forming a redistribution layer on the conductive pillar and the isolation layer, and the redistribution layer is connected to the interconnection through the conductive pillar. The layers are conductively connected, and the method of forming the conductive pillar includes but is not limited to PVD, CVD, ALD and other processes.

It should be noted that the offset direction and offset distance of the center point of each second pad relative to the center point of the corresponding first pad are equal. In this way, the same set of probes can be stuck in After performing the first type of test, the center point of the first pad can be aligned with the center points of all the second pads after moving a certain distance in a certain direction. That is, the probe card can directly test all the second pads. The pad performs Type II testing without the need to replace the probe card with a new one.

In addition, it should be noted that in the above-mentioned embodiments of the present disclosure, a packaging structure compatible with two types of tests is adopted, so that the semiconductor functional structure can undergo different types of tests at different process stages; however, it should be noted that when testing the packaging structure When performing layout design, it is necessary to reserve via holes for the rewiring layer on the top metal layer to ensure that when a rewiring layer needs to be added, there is no need to change the top metal layer or any other photoresist and process.

In the several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined, or can be integrated into another system, or some features can be ignored, or not implemented. In addition, the components shown or discussed are coupled to each other, or directly coupled.

The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Claims

A packaging structure including:

An isolation layer with a plurality of via holes, the isolation layer covers the surface of the interconnection layer, the via holes expose part of the interconnection layer, and the interconnection layer is provided on the surface of the semiconductor functional structure;

N first pads; each first pad is composed of the interconnection layer exposed by one of the via holes; the N is a positive integer greater than 1;

N redistribution layers, each redistribution layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads;

A first insulating layer covers and exposes a partial area of each redistribution layer;

At least part of the exposed partial area of the redistribution layer includes a second pad and a third pad; wherein, the center point of each second pad is relative to the center point of the corresponding first pad. The offset direction and offset distance are equal; the first pad and the second pad are respectively used for testing when the semiconductor functional structure is at different operating speeds, and the third pad is used to perform the same operation as the The content of the second liner test corresponds to the functional interaction.
The packaging structure according to claim 1, wherein,

The N first pads are all juxtaposed along the first direction at a position close to the first edge of the semiconductor functional structure;

At least part of the second pads and the corresponding third pads are arranged side by side along a second direction, and the second direction is perpendicular to the first direction.
The packaging structure according to claim 2, wherein the orthographic projection of the center point of each second pad on the plane of the interconnection layer is directed toward the corresponding center point of the first pad. The second direction is offset by the first distance.
The packaging structure according to claim 3, wherein the shape of the orthographic projection of the redistribution layer on the plane where the interconnection layer is located includes a strip shape.
The packaging structure according to claim 1, wherein,

Part of the first pads are arranged side by side along the first direction close to the first edge of the semiconductor functional structure; part of the second pads and the corresponding third pads are arranged side by side along the second direction, The second direction is perpendicular to the first direction;

The remaining portion of the first pads is arranged side by side in the second direction close to the second edge of the semiconductor functional structure. The first edge and the second edge are two opposite sides of the semiconductor functional structure. edge; the remaining second pads corresponding to the first pads and the third pads are arranged side by side along the first direction.
The packaging structure according to claim 5, wherein the orthographic projection of the center point of the second pad on the plane of the interconnection layer is offset in a third direction relative to the center point of the corresponding first pad. Moving the second distance, the angle between the third direction and the first direction is 45° or 135°.
The packaging structure according to claim 6, wherein the shape of each first pad includes a strip shape, and the orthogonal projection shape of part of the redistribution layer on the plane where the interconnection layer is located includes an L shape. , the shape of the orthographic projection of the other part of the redistribution layer on the plane where the interconnection layer is located includes a Z shape.
The packaging structure according to claim 1, wherein,

The second pad is located at an end of the redistribution layer close to the first pad, and the third pad is located at an end of the redistribution layer away from the first pad.
The packaging structure according to claim 1, wherein,

The redistribution layer is in direct contact with the corresponding first pad;

Alternatively, the packaging structure further includes: a conductive pillar located between the redistribution layer and the corresponding first pad, and the redistribution layer is conductively connected to the interconnection layer through the conductive pillar.
The packaging structure according to claim 9, wherein the packaging structure includes the conductive pillar, the orthographic projection of the conductive pillar on the plane of the interconnection layer overlaps the first pad, and the conductive pillar overlaps the first pad. The orthographic projection of the pillar on the plane of the interconnection layer does not overlap with the orthographic projections of the second pad and the third pad on the plane of the interconnection layer.
The packaging structure according to claim 9, wherein the rewiring layer is in direct contact with the corresponding first pad, and the packaging structure further includes:

A second insulating layer is located in the groove surrounded by each redistribution layer; the hardness of the material of the second insulating layer is smaller than the hardness of the material of the redistribution layer.
A semiconductor device, including: a semiconductor functional structure and a packaging structure as claimed in any one of claims 1 to 11.
The semiconductor device according to claim 12, wherein the semiconductor device further includes:

substrate;

A plurality of stacked die; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure;

Each die is electrically connected to the substrate through leads on a third pad in the package structure.
A method for making a packaging structure, including:

Provide a semiconductor functional structure, the surface of the semiconductor functional structure is provided with an interconnection layer;

An isolation layer is formed with a plurality of via holes, the isolation layer covers the surface of the interconnection layer, the via hole exposes a portion of the interconnection layer, and the portion of the interconnection layer exposed by each via hole serves as a first Pads to form N first pads; the first pads are used to perform the first type of test; the N is a positive integer greater than 1;

After completing the first type of test, N rewiring layers are formed on the N first pads and the isolation layer, and each rewiring layer covers the isolation layer and is connected to the N first pads. A corresponding first pad in the pad is electrically connected;

Form a first insulating layer covering and exposing part of the redistribution layer, and the exposed part of the redistribution layer serves as a second pad and a third pad; wherein, the center point of each second pad The offset direction and offset distance relative to the center point of the corresponding first pad are equal; the second pad is used to perform the second type of test, and the third pad is used to perform the same as the The functional interaction corresponding to the content of the second type of test; the running speed of the semiconductor functional structure when performing the first type of test is lower than the running speed when performing the second type of test.