CN112782561B - Chip interface test probe card and test method - Google Patents
Chip interface test probe card and test method Download PDFInfo
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- CN112782561B CN112782561B CN202011643868.5A CN202011643868A CN112782561B CN 112782561 B CN112782561 B CN 112782561B CN 202011643868 A CN202011643868 A CN 202011643868A CN 112782561 B CN112782561 B CN 112782561B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention discloses a chip interface test probe card and a test method, relates to the technical field of chip test, and is convenient for testing a chip high-speed IO interface. The probe card comprises a printed circuit board, wherein the first surface of the printed circuit board is provided with a test needle point, the second surface of the printed circuit board is provided with a substrate, a loopback circuit is arranged on the substrate, the substrate is also provided with a mounting part for mounting a probe, the loopback circuit comprises an input end and an output end, and the input end and the output end are respectively connected with the mounting part. The invention is suitable for the wafer-level chip interface test scene, in particular to the high-speed IO interface test occasion.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a probe card for testing a chip interface and a testing method thereof.
Background
Integrated circuit chip testing is an important step in chip manufacturing to ensure good yields, and in order to reduce the cost of chip test packaging, die (Die) used to package the chip is typically identified at the wafer level. Currently, an automatic tester ATE (Automatic Test Equipment) is used in the semiconductor industry in combination with a probe card to perform a wafer-level chip (i.e., die) reliability test.
In high-speed signal interface (commonly referred to as high frequency domain or high speed domain) testing of integrated circuit chips when the clock frequency exceeds 100MHz or the rising edge is less than 1ns, loop back (Loopback) testing is a very important test technique that can help test the physical links of the integrated circuit chips in a self-test format. The Loopback test is divided into Internal Loopback (inner loop) and External Loopback (outer loop), and the outer loop has a wider and more comprehensive test range than the inner loop.
In some hardware implementation schemes of external loop-back test, the external loop-back test is performed by arranging loop-back circuits on a multi-layer circuit board (also called a printed circuit board, commonly called a PCB) of a probe card, which is easily affected by other wirings on the circuit board, so that signal integrity problems such as reflection, crosstalk, noise and the like occur, and it is difficult to realize high-speed IO (Input & Output) interface test speed, and it is inconvenient to test a chip high-speed IO interface.
Disclosure of Invention
In view of this, the embodiment of the invention provides a chip interface test probe card and a test method, which are convenient for testing a chip high-speed IO interface.
In order to achieve the aim of the invention, the following technical scheme is adopted:
in a first aspect, an embodiment of the present invention provides a chip interface test probe card, including a printed circuit board, where a first surface of the printed circuit board has test pins, a second surface of the printed circuit board is provided with a substrate, a loopback circuit is disposed on the substrate, and an installation portion for installing a probe is further disposed on the substrate, where the loopback circuit includes an input end and an output end, and the input end and the output end are respectively connected to the installation portion.
With reference to the first aspect, in a first implementation manner of the first aspect, the loopback circuit is a differential loopback circuit.
With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the differential loopback circuit is an RC differential loopback circuit or an LC differential loopback circuit.
With reference to the first or second implementation manner of the first aspect, in a third implementation manner of the first aspect, the differential loopback circuit includes a first differential signal line and a second differential signal line that are arranged on the substrate in parallel, a first coupling capacitor is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line.
With reference to any one of the first to third implementation manners of the first aspect, in a fourth implementation manner of the first aspect, when the differential loopback circuit is an RC differential loopback circuit, the differential loopback circuit further includes a third differential signal line and a fourth differential signal line that are arranged on the substrate in parallel, where the third differential signal line includes a first pre-stage signal line and a first post-stage signal line, the first pre-stage signal line is connected to the first end of the first coupling capacitor, the first post-stage signal line is connected to the second end of the first coupling capacitor, a first resistor is disposed on the first pre-stage signal line, and a second resistor is disposed on the first post-stage signal line;
the fourth differential signal line comprises a second pre-stage signal line and a second post-stage signal line, the second pre-stage signal line is connected to the first end of the second coupling capacitor, the second post-stage signal line is connected to the second end of the second coupling capacitor, a third resistor is arranged on the second pre-stage signal line, and a fourth resistor is arranged on the second post-stage signal line;
when the differential loop-back circuit is an LC differential loop-back circuit, the resistor in the RC differential loop-back circuit is replaced by an inductor.
In a second aspect, an embodiment of the present invention provides a method for testing a chip interface, based on implementation of any one of the probe cards in the first aspect, where the probe card is connected to a device for triggering a test through a test pin point on a first surface, a probe is installed in a mounting portion on a substrate of the probe card, an end portion of the probe is in contact with a die interface to be tested on a wafer, and the die to be tested on the wafer is an unpackaged chip;
the method comprises the following steps:
after triggering the test instruction, the chip sending end sends a loopback test packet to enter a loopback circuit input end on the probe card substrate through the probe;
the loopback test packet entering the loopback circuit is looped back to the chip receiving end through the output end of the loopback circuit;
and determining the state of the corresponding interface of the chip based on the test packet looped back by the chip receiving end.
With reference to the second aspect, in a first implementation manner of the second aspect, the test packet is a pseudo-random code;
the loop-back test packet sent by the chip sending end enters the loop-back circuit input end on the probe card substrate through the probe and comprises the following components: the chip transmitting end transmits the pseudo-random code to the input end of the loopback circuit;
the loop-back test packet entering the loop-back circuit is looped back to the chip receiving end through the loop-back circuit output end, and the loop-back test packet comprises: the loop-back circuit transmits the pseudo-random code in a differential signal, and the pseudo-random code is looped back to the chip receiving end through the loop-back circuit output end.
With reference to the first implementation manner of the second aspect, in a second implementation manner of the second aspect, the loop-back circuit transmits the pseudo-random code in a differential signal, and loops back to the chip receiving end via an output loop of the loop-back circuit includes:
the loop-back circuit transmits pseudo-random code differential signals through a first differential signal line and a second differential signal line;
the first coupling capacitor performs alternating current coupling on the pseudo-random code differential signals in the first differential signal line, filters direct current components in the pseudo-random code differential signals, and outputs the first differential signals to the chip receiving end;
the second coupling capacitor performs alternating current coupling on the pseudo-random code differential signals in the second differential signal line, filters direct current components in the pseudo-random code differential signals, and outputs the second differential signals to the chip receiving end;
the determining the state of the corresponding interface of the chip based on the test packet looped back by the chip receiving end comprises the following steps:
determining a pseudo-random code level value sent by a chip sending end according to the difference value of the first differential signal and the second differential signal;
and comparing the determined pseudo-random code level value with a preset expected value to determine the state of the corresponding interface of the chip.
With reference to the first or second embodiment of the second aspect, in a third embodiment of the second aspect,
the equipment for triggering the test is an automatic tester;
the method further comprises the steps of: the first pre-stage signal wire and the first post-stage signal wire of the third differential signal wire, the second pre-stage signal wire and the second post-stage signal wire of the fourth differential signal wire are respectively connected to a direct current test channel of the automatic tester, and the first differential signal wire and the second differential signal wire are respectively connected with corresponding interfaces of the chip through probes;
the loop-back test loop is disconnected by utilizing the direct current open-circuit characteristic of the first coupling capacitor and the second coupling capacitor, and the loop-back test loop is switched into a four-way direct current test loop;
and testing the direct current characteristics of the chip interface based on each direct current test loop.
With reference to any one of the first to third embodiments of the second aspect, in a fourth embodiment of the second aspect, after the end of the dc characteristic test of the chip interface, the method further includes:
after receiving the loopback test instruction, switching to a dynamic characteristic test environment;
in a dynamic characteristic test environment, the first resistor, the second resistor, the third resistor and the fourth resistor block signal transmission between a transmitting end or a receiving end of the chip and a direct current channel of the automatic tester;
meanwhile, based on the characteristic that the first coupling capacitor and the second coupling capacitor are isolated from direct current and alternating current, the loopback test circuit is conducted.
According to the chip interface test probe card and the test method provided by the embodiment of the invention, the loop-back circuit is arranged on the substrate by improving the probe card, so that the loop-back circuit is far away from other electronic elements and wirings on the printed circuit board, and the distance between interconnection lines in the loop-back test circuit formed between the transmitting end and the receiving end of the chip interface is shorter, so that the signal integrity problems such as signal reflection, crosstalk and noise in the loop-back test scheme of the existing probe card can be improved, and the test speed of a high-speed IO (Input & Output) interface can be realized more conveniently, thereby being convenient for testing the chip high-speed IO interface.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a probe card according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an embodiment of a hardware testing environment for testing wafer level integrated circuit chips constructed based on the probe card of the present invention;
FIG. 3 is a schematic circuit diagram of a loop-back circuit on a probe card substrate according to an embodiment of the present invention;
FIG. 4 is a schematic layout of a loopback circuit on a probe card substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing simulation results of an embodiment of performing external loop-back testing of a chip interface based on a probe card according to the present invention;
FIG. 6 is a flowchart of a chip interface test method according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The probe card provided by the embodiment of the invention is suitable for a wafer-level chip (namely, a DIE) interface test scene, in particular to a test occasion of a high-speed IO interface; the method is convenient for realizing the outer loop circuit test of the high-speed interface hardware, and can also realize the Direct Current (DC) characteristic test of the high-speed interface hardware.
FIG. 1 is a schematic diagram of a probe card according to an embodiment of the invention; referring to fig. 1, a Probe card (Probe card) is shown comprising a printed circuit board (Printed circuit boards, abbreviated PCB, but commonly referred to in the industry as PCB board, hereinafter also referred to by the generic term PCB board) having a first surface with test pins for interconnection (including physical and signal interconnections) with external test equipment, such as automatic tester ATE, in some test scenarios; a Substrate (also called SUB) is arranged on the second surface of the printed circuit board, and the Substrate is also called a Multi-Layered Organic (also called MLO); the substrate is distinguished from a PCB board in that the substrate is thin. The substrate is provided with a loop circuit, the substrate is also provided with a mounting part for mounting the probe, the loop circuit comprises an input end and an output end, and the input end and the output end are respectively connected with the mounting part.
The input end and the output end of the loopback circuit correspond to the transmitting end and the receiving end of the information source in a specific loopback test scene, and are sometimes called a transmitting end (source end) and a receiving end (sink end).
During testing, after the mounting part is provided with the probe, the loopback circuit is connected with the IO interface of the wafer-level chip DIE through the probe, and then the loopback test can be performed.
Of course, in some embodiments, the probe card itself is populated with probes.
It can be appreciated that at present, the reliability test of the IO interface is performed by adopting a test mode of the external loopback External Loopback. In the hardware implementation mode, since the loop-back circuit is arranged on the PCB, the loop-back circuit is generally formed from the chip, the probe of the probe card and the substrate to the multi-layer PCB, and then from the multi-layer PCB to the chip after passing through the substrate and the probe. Based on the loop-back mode External loopback, the loop-back test signal is easily influenced by nearby electronic elements and wiring because the electronic elements and the wiring on the PCB are numerous; in addition, loop back is carried out from the PCB, and the physical link is long; signal integrity problems such as reflections, cross-talk, noise, etc. tend to occur. Even if the interconnection line maintains the required specific spacing and the specific impedance matching of the perfect precise circuit board layout, the signal frequency attenuation caused by the problems of reflection, crosstalk, noise and other signal integrity can only reach the IO interface test speed of about 10Gbps basically.
The external loop test route performed by the probe card according to the present embodiment is as follows: the signal is sent from the chip, the signal is transmitted to the substrate through the probe, and then the signal is looped back to the chip receiving end through the probe by the substrate, and compared with the existing probe snap ring loop scheme, the loop path is shorter.
Therefore, by improving the probe card and arranging the loop circuit on the substrate, the loop circuit is far away from other electronic elements and wirings on the printed circuit board, and the distance between interconnection lines in the loop test circuit formed between the transmitting end and the receiving end of the chip interface is shorter, so that the signal integrity problems of signal reflection, crosstalk, noise and the like in the loop test scheme of the existing probe card can be improved, the high-speed IO interface test speed can be realized more conveniently, and the chip high-speed IO interface can be tested conveniently.
As shown in FIG. 5, some simulation test results prove that the probe card provided by the embodiment of the invention can realize the hardware test speed of the high-speed IO interface above 25Gpbs, is convenient for performing the outer loop test of the high-speed IO interface, and can improve the reliability of the test.
In this embodiment, as an alternative embodiment, the loopback circuit is a differential loopback circuit. The differential loop circuit is adopted to transmit high-speed signals to complete loop test of the wafer-level chip interface, so that test noise can be reduced, electromagnetic interference (EMC and EMI) is reduced, the error rate is reduced, and the transmission rate is further improved.
Specifically, the differential loopback circuit is an RC (mainly composed of resistance and capacitance) differential loopback circuit or an LC (mainly composed of inductance and capacitance) differential loopback circuit.
In this embodiment, the transmission loop-back test in the form of differential signals includes performing a chip interface loop-back test, and since an RC or LC differential loop-back circuit is adopted, common mode signals can be suppressed, which is helpful for reducing noise and interference.
Referring to fig. 3 and 4, in some embodiments, the differential loopback circuit includes a first differential signal line and a second differential signal line that are arranged on a substrate in parallel, a first coupling capacitor C1 is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line.
The first differential signal line includes differential signal lines L2, L9, L11 and L14, and the first coupling capacitor C1 is disposed between the differential signal lines L9 and L11.
The second differential signal line includes differential signal lines L1, L5, L7, and L13, and the second coupling capacitor C2 is disposed between the differential signal lines L5 and L7.
When a loopback test is carried out, a pseudo-random code generator in the chip generates pseudo-random codes, a transmitting end (source end) transmits the pseudo-random codes through a first differential signal line and a second differential signal line in a high-speed differential signal mode, a first coupling capacitor C1 on the first differential signal line and a first coupling capacitor C2 on the second differential signal line are coupled through Alternating Current (AC), direct current components in the differential signals are isolated, the first differential signal and the second differential signal are looped back to a chip receiving end through a loopback circuit output end and a probe, and the chip judges whether the data transmitting end transmits a high level or a low level, namely 1 or 0 by comparing the difference value between the first differential signal P and the second differential signal N; and comparing the level value obtained by judgment with a preset expected value, and giving whether the test result is Pass (representing passing) or Fail (representing failing or failing) based on the comparison result.
In other alternative embodiments, the level value received by the receiving end may be compared with the original pseudo-random code level value transmitted by the transmitting end, so as to determine the error rate, and based on this, the test result is Pass or Fail.
Some existing probe cards have the chip sending end and the chip receiving end connected to the probe card substrate in an external short circuit mode to carry out loop back, and External Loopback tests above 25Gbps can also be completed. However, it cannot perform direct current DC characteristic parameter test of high-speed IO concurrently. If DC characteristic parameter test is required for high-speed IO, the probe card with different functions needs to be designed to complete. Therefore, two different probe cards are required to be matched for different functional tests of the same chip, so that the complete reliability test of loop-back test and DC characteristic test on the high-speed IO interface can be completed.
In order to solve the problem that two probe cards are required to be designed at present to test the integrity and the reliability of a chip. Referring to fig. 3, in this embodiment, as an alternative embodiment, when the differential loopback circuit is an RC differential loopback circuit, the differential loopback circuit further includes a third differential signal line and a fourth differential signal line that are disposed on the substrate in parallel, where the third differential signal line includes a first pre-stage signal line and a first post-stage signal line, the first pre-stage signal line is connected to the first end of the first coupling capacitor C1, and the first pre-stage signal line includes signal lines L3, L10, and L9 (L9 and L10 may be combined into one line); the first post-stage signal line is connected to the second end of the first coupling capacitor C1, and includes signal lines L11, L12 and L16; the first pre-stage signal line is provided with a first resistor R1, and the first post-stage signal line is provided with a second resistor R3.
The fourth differential signal line comprises a second pre-stage signal line and a second post-stage signal line, the second pre-stage signal line is connected to the first end of the second coupling capacitor C2, the second post-stage signal line is connected to the second end of the second coupling capacitor C2, a third resistor R2 is arranged on the second pre-stage signal line, and a fourth resistor R4 is arranged on the second post-stage signal line.
The second pre-stage signal lines include signal lines L4, L6 and L5 (L5 and L6 may be combined into one), and the second post-stage signal lines include signal lines L7, L8 and L15 (L7 and L8 may be combined into one).
When testing DC characteristic parameters of a chip interface, an automatic tester ATE is connected to one ends of resistors of a pre-stage signal line and a post-stage signal line of a third differential line and a fourth differential line on a probe card substrate through a test channel corresponding to an interface signal to be tested and corresponding to the test channel, wherein four wiring terminals in the corresponding diagram are TX_P-CH, RX_P-CH, TX_N-CH and RX_N-CH, signals of the TX_P-CH and the TX_N-CH terminals are a pair (also called a group) of differential signals, and signals of the RX_P-CH and the RX_N-CH terminals are a pair of differential signals; under the direct current test environment, the front stage signal wire and the rear stage signal wire are separated through a coupling capacitor, so that four paths of direct current test channels are formed through switching, and each path of direct current test channel reaches a signal welding pad end (namely a wafer-level chip end) through a probe after passing through a resistor, so that the interconnection of the DC test environment channels is completed.
The direct current test environment is also called a static parameter test environment. It can be understood that in the chip interface test technology, the chip interface test is generally classified into a static characteristic test and a dynamic characteristic test, wherein the static characteristic test is performed under a direct current test environment, and the dynamic characteristic test is performed under an alternating current test environment, which is also called a dynamic characteristic test environment, because the dynamic characteristic test needs to test a change of a digital signal.
In fig. 3, signal lines L9 and L10, L11 and L12 are labeled separately for convenience of description, and one line is used for wiring. In some embodiments, signal lines L9 and L10 employ one line in wiring; in addition, L5 and L6, L7 and L8, and L11 and L12 are similarly wired, and only one line is wired, respectively.
As shown in FIG. 3, ATE passes through the TX_P-CH channel and through L3, resistors R1 and L2 reach the TX_P pad of the chip. The ATE passes through the RX_P-CH channel and reaches the chip RX_P bonding pad end through the L16 and the resistors R3 and L14. The ATE passes through the TX_N-CH channel and reaches the pad end of the chip TX_N through the L4 and the resistors R2 and L1. The ATE passes through the RX_N-CH channel, and reaches the chip RX_N bonding pad end through the L15, the resistors R4, L8 and L13.
According to the probe card provided by the embodiment, through the scheme of the loop-back circuit, not only can the loop-back test be performed, but also four paths of independent direct current test channels can be switched into under a direct current test environment according to the characteristics of a capacitor direct current open circuit when the DC characteristic parameter test is required, so that the purpose of independently testing the DC characteristic parameter of each signal by ATE is realized. Therefore, the probe card provided by the embodiment not only can carry out high-speed IO loopback test, but also can meet DC characteristic parameter test.
The invention can complete the test effect of two existing probe cards by one probe card, effectively reduces the cost, saves the time for the later failure debugging, and avoids the problem of difficult failure debugging caused by adopting two probe cards in the later period.
In addition, as an alternative implementation manner, when the complete reliability test of the high-speed IO interface of the chip is performed, the DC characteristic test is performed first, and then the loopback test is performed.
In this embodiment, after the DC characteristic test is finished, the physical interconnection with the automatic tester ATE is not required to be disconnected, the ATE is set to a loopback test mode, and the ac test environment required for switching to the loopback test is triggered, the first coupling capacitor and the second coupling capacitor show characteristics of blocking direct current and alternating current and blocking low frequency and high frequency in the ac state, the impedance of the DC test channel of the ATE is increased, at this time, the parasitic capacitance (the parasitic capacitance generally refers to the capacitance characteristic of the inductor, the resistor, the chip pin and the like shown in the high frequency condition) of each resistor in fig. 2 is very small, and then the TX/RX end of the chip is disconnected from the signal of the DC test channel of the ATE, so that the first coupling capacitor and the second coupling capacitor automatically switch to the loopback test environment, so as to facilitate the loopback test of the high-speed IO interface.
FIG. 4 is a schematic layout of a loopback circuit on a probe card substrate according to an embodiment of the present invention; one layout implementation of high-speed IO reliability test loop-back circuitry on a probe card substrate is described. As previously mentioned, in order to reduce signal integrity problems such as noise, cross-talk, etc., one countermeasure is that the physical links between hardware in the test environment should be as short as possible and as far as possible from other wiring, which places high demands on the wiring of the loop-back circuit on the substrate. In some embodiments, tx_n and tx_p in the first and second differential signal lines are a pair of differential pairs, and rx_n and rx_p are a pair of differential pairs. To avoid the impact of signal integrity issues on high-speed IO reliability testing, the differential pair employs 100 ohm impedance matching. The length of the interconnection lines is as short as possible when wiring is designed, the line spacing which is more than multiple with other signal lines is kept, the wiring design is optimized, and layers are not replaced, namely the wiring is performed on the same layer of the substrate as much as possible (for facilitating understanding, the wiring of the PCB board is simply described, namely the PCB board comprises the substrate, and a plurality of layers of flat cables are generally arranged when wiring).
In terms of line materials, a material having a small dielectric constant is selected to reduce crosstalk and the like. In the aspect of lamination, each lamination is reasonably distributed, and the spacing is optimized.
In addition, the wiring length and routing problems of the wires to the ATE instrumentation terminals, i.e., TX_N-CH, TX_P-CH, RX_N-CH, and RX_P-CH, are strictly controlled.
The probe card provided by the embodiment of the invention can complete the test effect of two existing probe cards by one probe card based on the arrangement of the loop-back circuit on the probe card substrate, can realize the test of the high-speed chip interface hardware loop-back circuit with the speed greater than 25Gpbs, and can perform the test of DC characteristic parameters. The cost of testing and later maintenance can be reduced to a certain extent. Further, compared with the prior art adopting a two-probe card test scheme, at least the test steps for replacing the probe card are reduced, so that the test duration can be shortened.
Example two
Based on the probe card provided in the first embodiment, the invention also provides a chip interface testing method, which is suitable for testing the chip high-speed interface.
FIG. 2 is a schematic diagram of an embodiment of a hardware testing environment for testing wafer level integrated circuit chips constructed based on the probe card of the present invention; FIG. 3 is a schematic circuit diagram of a loop-back circuit on a probe card substrate according to an embodiment of the present invention; FIG. 6 is a flowchart of a chip interface test method according to an embodiment of the invention.
Referring to fig. 2, 3 and 6, according to the method for testing a chip interface provided by the embodiment of the present invention, the probe card is implemented according to the embodiment, and referring to fig. 2, a hardware testing environment is required to be built before testing, the probe card is connected with a device for triggering testing through a testing needle point on a first surface (i.e. an upper surface in fig. 2), in fig. 2, the device for triggering testing is an automatic tester ATE, the ATE is contacted with a testing needle point on an upper surface of a PCB board of the probe card (i.e. a pad above the PCB) through a testing probe, a probe is mounted in a mounting portion of the substrate of the probe card, the probe is fixed through a probe chuck, and is used for contacting each testing unit (DUT: device under test), i.e. a Die, on a wafer, and one testing unit is a Die, and an end of the probe is contacted with a Die interface (i.e. a pin) to be tested on the wafer, i.e. a so-called wafer-level chip, i.e. an unpackaged chip.
The method comprises the following steps:
step S110, after triggering a test instruction, a chip sending end sends a loopback test packet to enter a loopback circuit input end on a probe card substrate through a probe;
in this embodiment, after the chip receives a test instruction sent by the ATE device, the pseudo-random code generator in the chip generates a series of pseudo-random code sequences as a loopback test packet, and sends the loopback test packet to the loopback circuit through the probe.
Pseudo-random codes are sequence codes that are repeatedly generated and replicated, and have some random sequence random characteristic.
Step S120, the loop-back test packet entering the loop-back circuit is looped back to the chip receiving end through the loop-back circuit output loop.
In this embodiment, since the loopback circuit is located on the probe card substrate, the transmission path of the loopback test packet is looped back to the chip receiving end only through the substrate without passing through the PCB, shortening the transmission path, and since the electronic components and wirings on the route (path) are relatively less without passing through the PCB, it is beneficial to reduce the signal integrity problems such as signal reflection, crosstalk and noise.
Step S130, determining the state of the corresponding interface of the chip based on the test packet looped back by the chip receiving end.
If the test packet does not loop back to the chip receiving end, the direct judgment result is Fail. Further, the state of the corresponding interface of the chip can be determined according to the error rate of the test packet. The status of the corresponding interface of the chip, etc. may also be determined based on the time from transmission to reception of the test packet. In order to highlight the gist of the present invention, it is not necessary to exhaustively describe how to determine the states of the corresponding interfaces of the chip.
As shown in fig. 3 or 4, in some embodiments, the test packet is a pseudo-random code; in the step S110, the sending of the loopback test packet by the chip sending end into the input end of the loopback circuit on the probe card substrate via the probe includes: the chip transmitting end TX_P transmits pseudo-random codes to the loop-back circuit input end L2;
in step S120, the looping test packet entering the looping circuit is looped back to the chip receiving end via the output loop of the looping circuit, including: the loop-back circuit transmits the pseudo-random code in a differential signal, and the pseudo-random code is looped back to the chip receiving end through the loop-back circuit output end.
As shown in fig. 3, the pseudo-random code is transmitted as a differential signal, and coupled through a capacitor C1 after passing through the tx_p pad, to reach the rx_p end; the tx_n signal is coupled via capacitor C2 to the rx_n terminal.
With continued reference to fig. 3 and 4, in some embodiments, the differential loopback circuit includes a first differential signal line and a second differential signal line arranged in parallel on a substrate, a first coupling capacitor is disposed on a node of the first differential signal line, and a second coupling capacitor is disposed on a node of the second differential signal line. The loop-back circuit transmits the pseudo-random code in a differential signal, and loops back to the chip receiving end through the loop-back circuit output end, and the loop-back circuit comprises:
the loop-back circuit transmits pseudo-random code differential signals through the first differential signal line and the second differential signal line. The first coupling capacitor performs alternating current coupling on the pseudo-random code differential signals in the first differential signal line, filters direct current components in the pseudo-random code differential signals, and outputs the first differential signals to the chip receiving end.
And the second coupling capacitor performs alternating current coupling on the pseudo-random code differential signals in the second differential signal line, filters direct current components in the pseudo-random code differential signals, and outputs the second differential signals to the chip receiving end.
In step S130, the determining the state of the corresponding interface of the chip based on the test packet looped back by the chip receiving end includes:
determining a pseudo-random code level value sent by a chip sending end according to the difference value of the first differential signal and the second differential signal; and comparing the determined pseudo-random code level value with a preset expected value to determine the state of the corresponding interface of the chip.
In this embodiment, when the external loopback high-speed test is performed, the high-speed differential signal is AC-coupled through the first and second AC coupling capacitors, and the chip receiving end determines whether the high level or the low level is transmitted by the chip transmitting end by comparing the difference between the differential signals P and N, and determines the state of the chip interface based on the level value and the preset expected value, and gives the test result of Pass or Fail based on the result.
In addition, after receiving the pseudo-random sequence, the pseudo-random sequence is tested and compared with a pseudo-random code of a transmitting end, the error rate is determined, and the chip interface state is judged based on the error rate.
As shown in fig. 3, in some embodiments, the differential loopback circuit further includes a third differential signal line and a fourth differential signal line disposed on the substrate in parallel, and for a specific circuit topology, please refer to embodiment 1 for a description.
In this embodiment, the device for triggering a test is an automatic tester ATE; the method further comprises the steps of: and the first pre-stage signal wire and the first post-stage signal wire of the third differential signal wire, the second pre-stage signal wire and the second post-stage signal wire of the fourth differential signal wire are respectively connected with a direct current test channel of the automatic tester, and the first differential signal wire and the second differential signal wire are respectively connected with corresponding interfaces of the chip through probes. The first pre-stage signal line and the second pre-stage signal line form a group of differential signal pairs, and the first post-stage signal line and the second post-stage signal line form a group of differential signal pairs.
The loop-back test loop is disconnected by utilizing the direct current open-circuit characteristic of the first coupling capacitor and the second coupling capacitor, and the loop-back test loop is switched into a four-way direct current test loop; and testing the direct current characteristics of the chip interface based on each direct current test loop.
The test method provided by the embodiment is based on the probe card of the first embodiment, not only can perform high-speed IO loopback test, but also can meet DC characteristic parameter test, and achieves the effect that the one-card is used for various test functions.
In other embodiments, after the dc characteristic test of the chip interface is finished, the method further includes: after receiving the loopback test instruction, switching to a dynamic characteristic test environment; in a dynamic characteristic test environment, the first resistor, the second resistor, the third resistor and the fourth resistor block signal transmission between a transmitting end or a receiving end of the chip and a direct current channel of the automatic tester; meanwhile, based on the characteristic that the first coupling capacitor and the second coupling capacitor are isolated from direct current and alternating current, the loopback test circuit is conducted.
In this embodiment, when the DC characteristic test is finished and the loopback test is required, a selected loopback test mode trigger instruction is received and switched to the dynamic characteristic test environment, the first coupling capacitor and the second coupling capacitor show characteristics of blocking DC-to-ac and blocking low-frequency-to-high frequency in the ac state, the impedance of the DC test channel of the ATE increases, at this time, the parasitic capacitance (the parasitic capacitance generally refers to the capacitance characteristic of the inductor, the resistor, the chip pin, etc. shown in the high-frequency case) of each resistor in fig. 2 is very small, and then the TX/RX end of the chip is disconnected from the signal of the DC test channel of the ATE, so that the signal is automatically switched to enter the loopback test environment to facilitate the loopback test of the high-speed IO interface.
According to the chip interface testing method provided by the embodiment of the invention, the problem of signal frequency attenuation caused by the signal integrity problem in external loop-back testing is solved based on the arrangement of the differential loop-back circuit on the probe card substrate, and DC characteristic parameter testing can be performed without changing the probe card.
For the embodiments provided in the present invention, since the embodiments are based on the same or corresponding specific technical concepts, the technical solutions and technical effects thereof are basically the same, and the related parts can be referred to each other, and for clarity and brevity, description is omitted.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and the same or similar parts of each embodiment are referred to each other, where each embodiment mainly describes differences from other embodiments.
For convenience of description, the above relay control system is described as being functionally divided into various functional units/circuits/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (4)
1. A method of chip interface testing, the method being implemented based on a chip interface test probe card, the chip interface test probe card comprising: the first surface of the printed circuit board is provided with a test needle point, the second surface of the printed circuit board is provided with a substrate, a loopback circuit is arranged on the substrate, the substrate is also provided with a mounting part for mounting a probe, the loopback circuit comprises an input end and an output end, and the input end and the output end are respectively connected with the mounting part; the loop-back circuit is a differential loop-back circuit, the differential loop-back circuit comprises a first differential signal line and a second differential signal line which are arranged on a substrate in parallel, a node of the first differential signal line is provided with a first coupling capacitor, and a node of the second differential signal line is provided with a second coupling capacitor;
the probe card is connected with equipment for triggering test through a test needle point on the first surface, a probe is arranged in a mounting part on a probe card substrate, the end part of the probe is contacted with a to-be-tested die interface on a wafer, and the to-be-tested die on the wafer is an unpackaged chip;
the method comprises the following steps:
after triggering the test instruction, the chip sending end sends a loopback test packet to enter a loopback circuit input end on the probe card substrate through the probe;
the loopback test packet entering the loopback circuit is looped back to the chip receiving end through the output end of the loopback circuit;
determining the state of a corresponding interface of the chip based on the test packet looped back by the chip receiving end;
the method further comprises the steps of: the loop-back test loop is disconnected by utilizing the direct current open-circuit characteristic of the first coupling capacitor and the second coupling capacitor, and the loop-back test loop is switched into a four-way direct current test loop; testing the direct current characteristics of the chip interface based on each path of direct current test loop;
the differential loop-back circuit is an RC differential loop-back circuit, the differential loop-back circuit also comprises a third differential signal line and a fourth differential signal line which are arranged on the substrate in parallel, the third differential signal line comprises a first pre-stage signal line and a first post-stage signal line, the first pre-stage signal line is connected with a first end of the first coupling capacitor, the first post-stage signal line is connected with a second end of the first coupling capacitor, a first resistor is arranged on the first pre-stage signal line, and a second resistor is arranged on the first post-stage signal line;
the fourth differential signal line comprises a second pre-stage signal line and a second post-stage signal line, the second pre-stage signal line is connected to the first end of the second coupling capacitor, the second post-stage signal line is connected to the second end of the second coupling capacitor, a third resistor is arranged on the second pre-stage signal line, and a fourth resistor is arranged on the second post-stage signal line;
the test packet is a pseudo-random code;
the loop-back test packet sent by the chip sending end enters the loop-back circuit input end on the probe card substrate through the probe and comprises the following components: the chip transmitting end transmits the pseudo-random code to the input end of the loopback circuit;
the loop-back test packet entering the loop-back circuit is looped back to the chip receiving end through the loop-back circuit output end, and the loop-back test packet comprises: the loop-back circuit transmits the pseudo-random code through a differential signal line and loops back to a chip receiving end through a loop-back circuit output end;
the loop-back circuit transmits the pseudo-random code by a differential signal line, and loops back to a chip receiving end through a loop-back circuit output end, and the loop-back circuit comprises:
the loop-back circuit transmits pseudo-random code differential signals through a first differential signal line and a second differential signal line;
the first coupling capacitor performs alternating current coupling on the pseudo-random code differential signals in the first differential signal line, filters direct current components in the pseudo-random code differential signals, and outputs the first differential signals to the chip receiving end;
the second coupling capacitor performs alternating current coupling on the pseudo-random code differential signals in the second differential signal line, filters direct current components in the pseudo-random code differential signals, and outputs the second differential signals to the chip receiving end;
the determining the state of the corresponding interface of the chip based on the test packet looped back by the chip receiving end comprises the following steps:
determining a pseudo-random code level value sent by a chip sending end according to the difference value of the first differential signal and the second differential signal;
and comparing the determined pseudo-random code level value with a preset expected value to determine the state of the corresponding interface of the chip.
2. The method of claim 1, wherein the differential loopback circuit is an LC differential loopback circuit, and wherein when the differential loopback circuit is an LC differential loopback circuit, a resistor in the RC differential loopback circuit is replaced with an inductance.
3. The method of claim 1, wherein the device for triggering a test is an automated tester;
the method further comprises the steps of: the first pre-stage signal wire and the first post-stage signal wire of the third differential signal wire, and the second pre-stage signal wire and the second post-stage signal wire of the fourth differential signal wire are respectively connected to the direct current test channel of the automatic tester, and the first differential signal wire and the second differential signal wire are respectively connected with corresponding interfaces of the chip through probes.
4. The method of claim 1, wherein after the dc characteristic test of the chip interface is completed, the method further comprises:
after receiving the loopback test instruction, switching to a dynamic characteristic test environment;
in a dynamic characteristic test environment, the first resistor, the second resistor, the third resistor and the fourth resistor block signal transmission between a transmitting end or a receiving end of the chip and a direct current channel of the automatic tester;
meanwhile, based on the characteristic that the first coupling capacitor and the second coupling capacitor are isolated from direct current and alternating current, the loopback test circuit is conducted.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113640556B (en) * | 2021-08-11 | 2023-03-03 | 山东大学 | Probe card of probe station |
| CN113740707A (en) * | 2021-08-20 | 2021-12-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Loopback test circuit of chip interface module |
| US20230228794A1 (en) * | 2022-01-18 | 2023-07-20 | Teradyne, Inc. | Probe for a test system |
| CN117199055A (en) * | 2022-06-01 | 2023-12-08 | 长鑫存储技术有限公司 | Packaging structure, manufacturing method thereof and semiconductor device |
| CN117172202A (en) * | 2023-09-05 | 2023-12-05 | 苏州异格技术有限公司 | Core particle self-checking and inter-core particle communication recovery method and device |
| CN117250481B (en) * | 2023-11-15 | 2024-01-23 | 零壹半导体技术(常州)有限公司 | High-density transceiving test circuit for chip test and test circuit board |
| CN117279197B (en) * | 2023-11-23 | 2024-01-23 | 零壹半导体技术(常州)有限公司 | High-frequency bandwidth differential wiring structure for chip test and test circuit board |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567432A (en) * | 1983-06-09 | 1986-01-28 | Texas Instruments Incorporated | Apparatus for testing integrated circuits |
| CN201118597Y (en) * | 2007-11-13 | 2008-09-17 | 青岛海信光电科技股份有限公司 | Electrical signal loop circuit and optical receiving/transmission module with this loop |
| TW200933182A (en) * | 2008-01-30 | 2009-08-01 | Jing-Jou Tang | Breakdown detecting method of probe card |
| CN101782613A (en) * | 2010-01-25 | 2010-07-21 | 中兴通讯股份有限公司 | System, device and method for realizing Ethernet power supply function testing |
| TWM473518U (en) * | 2013-09-18 | 2014-03-01 | Mpi Corp | Probe card |
| CN106841980A (en) * | 2017-01-10 | 2017-06-13 | 芯原微电子(上海)有限公司 | A kind of Bluetooth integrated circuit test system and method for testing |
| CN109037090A (en) * | 2017-06-12 | 2018-12-18 | 马维尔国际贸易有限公司 | More test-types probe cards and corresponding test macro |
| CN109696589A (en) * | 2017-10-23 | 2019-04-30 | 旺矽科技股份有限公司 | Probe card and signal path switching module assembly |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013060361A1 (en) * | 2011-10-25 | 2013-05-02 | Advantest (Singapore) Pte. Ltd. | Automatic test equipment |
-
2020
- 2020-12-30 CN CN202011643868.5A patent/CN112782561B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567432A (en) * | 1983-06-09 | 1986-01-28 | Texas Instruments Incorporated | Apparatus for testing integrated circuits |
| CN201118597Y (en) * | 2007-11-13 | 2008-09-17 | 青岛海信光电科技股份有限公司 | Electrical signal loop circuit and optical receiving/transmission module with this loop |
| TW200933182A (en) * | 2008-01-30 | 2009-08-01 | Jing-Jou Tang | Breakdown detecting method of probe card |
| CN101782613A (en) * | 2010-01-25 | 2010-07-21 | 中兴通讯股份有限公司 | System, device and method for realizing Ethernet power supply function testing |
| TWM473518U (en) * | 2013-09-18 | 2014-03-01 | Mpi Corp | Probe card |
| CN106841980A (en) * | 2017-01-10 | 2017-06-13 | 芯原微电子(上海)有限公司 | A kind of Bluetooth integrated circuit test system and method for testing |
| CN109037090A (en) * | 2017-06-12 | 2018-12-18 | 马维尔国际贸易有限公司 | More test-types probe cards and corresponding test macro |
| CN109696589A (en) * | 2017-10-23 | 2019-04-30 | 旺矽科技股份有限公司 | Probe card and signal path switching module assembly |
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