CN112771674B

CN112771674B - Electronic device substrate, manufacturing method thereof and electronic device

Info

Publication number: CN112771674B
Application number: CN201980001517.3A
Authority: CN
Inventors: 张逵; 卢鹏程; 刘李; 李云龙; 张大成
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-08-27
Filing date: 2019-08-27
Publication date: 2022-02-22
Anticipated expiration: 2039-08-27
Also published as: US11749691B2; US11404451B2; US20210408078A1; EP4024466A1; WO2021035529A1; EP4024466A4; CN112771674A; US20220336503A1

Abstract

An electronic device substrate, a manufacturing method thereof and an electronic device are provided. The electronic device substrate comprises a substrate base plate, a first insulating layer, a plurality of light-emitting photon units, a first conductive component and a second conductive component, wherein the light-emitting photon units, the first conductive component and the second conductive component are arranged on one side, far away from the substrate base plate, of the first insulating layer. The plurality of light-emitting sub-units and the first conductive component are respectively arranged in an array area and a peripheral area of the electronic device substrate, and the second conductive component is arranged between the first conductive component and the array area; the orthographic projection of the first conductive component and the second conductive component on the substrate is arranged at intervals; each of the plurality of light emitting sub-units includes a first driving electrode and a second driving electrode configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer; the peripheral region further includes a second common electrode layer electrically connected to the first conductive member and the first common electrode layer, the second conductive member and the first driving electrode both being in direct contact with the first insulating layer.

Description

Electronic device substrate, manufacturing method thereof and electronic device

Technical Field

The embodiment of the disclosure relates to an electronic device substrate, a manufacturing method thereof and an electronic device.

Background

Organic Light Emitting Diode (OLED) display panels are receiving much attention due to advantages of wide viewing angle, high contrast, fast response speed, higher Light Emitting brightness, lower driving voltage, and the like compared to inorganic Light Emitting display devices. Due to the characteristics, the Organic Light Emitting Diode (OLED) display panel can be suitable for devices with display functions, such as mobile phones, displays, notebook computers, digital cameras, instruments and meters and the like. Silicon-based microdisplays (e.g., silicon-based OLEDs) have smaller pixel sizes and pixel pitches, and thus higher resolution, and are suitable for near-eye display devices (e.g., virtual reality display devices or augmented reality display devices).

Disclosure of Invention

At least one embodiment of the present disclosure provides an electronic device substrate including a substrate base plate, a first insulating layer, a plurality of light emitting sub-units, a first conductive member, and a second conductive member. The plurality of light-emitting sub-units, the first conductive component and the second conductive component are arranged on one side of the first insulating layer far away from the substrate; the plurality of light emitting sub-units are arranged in an array area of the electronic device substrate, the first conductive part is arranged in a peripheral area of the electronic device substrate surrounding the array area, and the second conductive part is arranged between the first conductive part and the array area; the orthographic projection of the first conductive component on the substrate base plate is spaced from the orthographic projection of the second conductive component on the substrate base plate; each of the plurality of light emitting sub-units comprises a first driving electrode and a second driving electrode configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer; the peripheral region further comprises a second common electrode layer, the first conductive part is electrically connected with the second common electrode layer, and the second common electrode layer is electrically connected with the first common electrode layer; and the first conductive member, the second conductive member, and the first drive electrode are all in direct contact with the first insulating layer.

For example, in at least one example of the electronic device substrate, the first conductive component and the second conductive component overlap the second common electrode layer; the first conductive part, the second conductive part and the first driving electrode are positioned in the same conductive structure layer; the orthographic projection of the first conductive component on the substrate base plate, the orthographic projection of the second conductive component on the substrate base plate and the orthographic projection of the first driving electrode on the substrate base plate are arranged at intervals; and the second common electrode layer is integrated with the first common electrode layer to form a common electrode layer.

For example, in at least one example of the electronic device substrate, the second conductive component is in direct electrical connection with the second common electrode layer.

For example, in at least one example of the electronic device substrate, the second conductive member includes a plurality of first electrode patterns provided at intervals, the plurality of first electrode patterns being arranged in a ring shape as a whole.

For example, in at least one example of the electronic device substrate, the first conductive member is a continuous first ring-shaped structure.

For example, in at least one example of the electronic device substrate, the first conductive member includes a plurality of second electrode patterns provided at intervals, and the plurality of second electrode patterns are arranged in a ring shape as a whole.

For example, in at least one example of the electronic device substrate, a shape of the second electrode pattern, a shape of the first electrode pattern, and a shape of the first driving electrode are substantially the same.

For example, in at least one example of the electronic device substrate, a size of the second electrode pattern, a size of the first electrode pattern, and a size of the first driving electrode are substantially equal.

For example, in at least one example of the electronic device substrate, the first conductive member is a continuous first ring-shaped structure and the second conductive member is a continuous second ring-shaped structure.

For example, in at least one example of the electronic device substrate, the second conductive component is not directly electrically connected to the first conductive component.

For example, in at least one example of the electronic device substrate, a loop width of the second conductive member is smaller than a loop width of the first conductive member in a direction from the array region toward the peripheral region.

For example, in at least one example of the electronic device substrate, a pitch between the first conductive member and the second conductive member is equal to a pitch between the first driving electrodes of adjacent light emitting sub-units in a direction pointing from the array region to the peripheral region.

For example, in at least one example of the electronic device substrate, the electronic device substrate further includes a third conductive component. The third conductive part is arranged on one side of the first insulating layer far away from the substrate base plate; the third conductive component is arranged around the array region and is positioned in the same conductive structure layer, and the second conductive component is arranged around the third conductive component; each of the plurality of light emitting sub-units includes a light emitting layer, the light emitting layers of the plurality of light emitting sub-units being integrated to form a light emitting material layer; and the layer of light emitting material extends onto and at least partially overlaps the third conductive member.

For example, in at least one example of the electronic device substrate, a pitch between the second conductive member and the third conductive member is equal to a pitch between the second conductive member and the first conductive member, and a loop width of the second conductive member is equal to a loop width of the third conductive member in a direction from the array region toward the peripheral region.

For example, in at least one example of the electronic device substrate, the first drive electrode is an anode, the second drive electrode is a cathode, and the first conductive member is a cathode ring; the orthographic projection of the second common electrode layer on the plane where the first driving electrode is located is a continuous plane; and the orthographic projection of the second common electrode layer on the plane of the first driving electrode completely covers the first conductive part.

For example, in at least one example of the electronic device substrate, the peripheral region further includes a fourth conductive member surrounding the first conductive member; the fourth conductive part is arranged on one side of the first insulating layer far away from the substrate base plate; and the fourth conductive part is overlapped with the second common electrode layer and is electrically connected with the second common electrode layer.

For example, in at least one example of the electronic device substrate, the first insulating layer includes a recess; the recessed portion is located on one side of the first insulating layer close to the first conductive member and located between an orthographic projection of the first conductive member on the first insulating layer and an orthographic projection of the first driving electrode on the first insulating layer; and an orthographic projection of the recessed portion on the base substrate, an orthographic projection of the first conductive member on the base substrate, an orthographic projection of the second conductive member on the base substrate, and an orthographic projection of the first drive electrode on the base substrate do not overlap.

For example, in at least one example of the electronic device substrate, the electronic device substrate further includes an intermediate conductive layer. The first insulating layer comprises a first via and a second via; the middle conducting layer is positioned on one side of the first insulating layer far away from the first driving electrode and comprises a first conducting structure and a second conducting structure; the first drive electrode is electrically connected to the first conductive structure via the first via, the second drive electrode is electrically connected to the second conductive structure via the first conductive feature and the second via, and the second conductive feature and the intermediate conductive layer are not directly electrically connected.

For example, in at least one example of the electronic device substrate, an orthographic projection of the second conductive member on the substrate, an orthographic projection of the first conductive structure on the substrate, and an orthographic projection of the second conductive structure on the substrate are spaced apart.

For example, in at least one example of the electronic device substrate, the electronic device substrate further includes a second insulating layer and a drive backplane disposed on a side of the intermediate conductive layer distal from the first drive electrode; the driving back plate comprises the substrate base plate; the second insulating layer is arranged between the middle conducting layer and the driving back plate; the second insulating layer comprises a third via and a fourth via; and the first driving electrode is electrically connected with the first area of the driving backboard through the first via hole, the first conductive structure and the third via hole, the second driving electrode is electrically connected with the second area of the driving backboard through the first conductive part, the second via hole, the second conductive structure and the fourth via hole, and the second conductive part and the driving backboard are not directly electrically connected.

For example, in at least one example of the electronic device substrate, the second conductive component does not directly receive a signal provided by the driving backplane.

For example, in at least one example of the electronic device substrate, the second conductive member is floating.

For example, in at least one example of the electronic device substrate, the first conductive member is a continuous first ring-shaped structure and the second conductive member is a continuous second ring-shaped structure; the peripheral region further comprises an electrical connection portion disposed between the first conductive component and the second conductive component and located in the same conductive structure layer; and the second conductive member is connected to the first conductive member through the electrical connection portion.

At least one embodiment of the present disclosure also provides an electronic device including any one of the electronic device substrates provided by at least one embodiment of the present disclosure.

At least one embodiment of the present disclosure provides a method of manufacturing an electronic device substrate, including: providing a substrate base plate; forming the first insulating layer on the base substrate; and forming a plurality of light emitting sub-units, a first conductive member and a second conductive member on a side of the first insulating layer away from the substrate base plate. The plurality of light emitting sub-units are arranged in an array area of the electronic device substrate, the first conductive part is arranged in a peripheral area of the electronic device substrate surrounding the array area, and the second conductive part is arranged between the first conductive part and the array area; the orthographic projection of the first conductive component on the substrate base plate is spaced from the orthographic projection of the second conductive component on the substrate base plate; each of the light emitting sub-units includes a first driving electrode and a second driving electrode stacked on each other, the first driving electrode and the second driving electrode being configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer; the peripheral region further comprises a second common electrode layer, the first conductive part is electrically connected with the second common electrode layer, and the second common electrode layer is electrically connected with the first common electrode layer; and the first conductive member, the second conductive member, and the first drive electrode are all in direct contact with the first insulating layer.

For example, in at least one example of the method of manufacturing the electronic device substrate, forming a plurality of light emitting sub-units, a first conductive member, and a second conductive member on a side of the first insulating layer remote from the substrate includes: forming a first conductive layer; patterning the first conductive layer to form a first drive electrode, the first conductive component, and the second conductive component of the plurality of light emitting sub-units; and forming a common electrode layer on the first driving electrode, the first conductive member, and the second conductive member, wherein the common electrode layer includes the first common electrode layer and the second common electrode layer integrated.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic plan view of an electronic device substrate;

FIG. 1B is a schematic cross-sectional view of the electronic device substrate taken along line AA' shown in FIG. 1A;

fig. 2A is a schematic plan view of an electronic device substrate according to at least one embodiment of the present disclosure;

FIG. 2B is a schematic cross-sectional view of the electronic device substrate shown in FIG. 2A;

FIG. 2C is a portion of the electronic device substrate shown in FIG. 2A;

fig. 3A is a schematic plan view of another electronic device substrate provided by at least one embodiment of the present disclosure;

fig. 3B is a schematic plan view of yet another electronic device substrate provided in at least one embodiment of the present disclosure;

fig. 4A is a schematic plan view of yet another electronic device substrate provided in at least one embodiment of the present disclosure;

FIG. 4B is a schematic cross-sectional view of the electronic device substrate shown in FIG. 4A;

FIG. 4C is a portion of the electronic device substrate shown in FIG. 4A;

fig. 5A is a schematic plan view of yet another electronic device substrate provided in at least one embodiment of the present disclosure;

FIG. 5B is a schematic cross-sectional view of the electronic device substrate shown in FIG. 5A;

FIG. 5C is a portion of the electronic device substrate shown in FIG. 5A;

fig. 6A is a schematic plan view of yet another electronic device substrate provided in at least one embodiment of the present disclosure;

FIG. 6B is a schematic cross-sectional view of the electronic device substrate shown in FIG. 6A;

FIG. 6C is a portion of the electronic device substrate shown in FIG. 6A;

fig. 7 is a schematic cross-sectional view of yet another electronic device substrate provided in at least one embodiment of the present disclosure;

fig. 8 is an exemplary block diagram of an electronic device provided by at least one embodiment of the present disclosure;

fig. 9 is a drive backplane of an electronic device provided by at least one embodiment of the present disclosure;

FIG. 10 illustrates a recess provided by at least one embodiment of the present disclosure; and

fig. 11 is a schematic cross-sectional view of another electronic device substrate provided in at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The inventors of the present disclosure note that the PPI (number of pixels per inch) of a microdisplay (e.g., a silicon-based microdisplay) is larger, and correspondingly, the sub-pixel size of the microdisplay (e.g., a silicon-based microdisplay) is smaller. For example, for microdisplays less than 0.5 inches in size and with resolutions above 5000 (e.g., silicon-based microdisplays), the sub-pixel size is as low as about 1.5 microns and the spacing between sub-pixels is as low as about 0.8 microns.

The inventors of the present disclosure have noted in their research that smaller sub-pixel sizes and sub-pixel pitches increase the difficulty of the development and etching processes of the microdisplay, reducing the uniformity of the microdisplay. The following is an exemplary description with reference to fig. 1A and 1B.

FIG. 1A shows a schematic plan view of an electronic device substrate 500; fig. 1B shows a schematic cross-sectional view of the electronic device substrate 500 taken along line AA' shown in fig. 1A. For example, the electronic device substrate 500 may be implemented as a display substrate (e.g., a display panel, an organic light emitting diode display panel), a light emitting substrate (e.g., a backlight), or the like.

As shown in fig. 1A, the electronic device substrate 500 includes an array region 501 and a peripheral region 502 surrounding the array region 501. The array region 501 includes a plurality of light emitting sub-units 510, and the peripheral region 502 includes a conductive member 521 (e.g., a cathode conductive member or a cathode adapter member) disposed around the array region 501.

As shown in fig. 1B, each of the plurality of light emitting sub-units 510 includes a first driving electrode 511, a second driving electrode 512, and a light emitting layer 513 interposed between the first driving electrode 511 and the second driving electrode 512. For example, the first and

second driving electrodes

511 and 512 are configured to apply a light emission driving voltage (apply a light emission driving voltage to the light emitting layer 513) so that the light emitting layer 513 emits light, and the intensity of the light corresponds to the value of the light emission driving voltage.

For example, as shown in fig. 1B, the first driving electrode 511 and the second driving electrode 512 are an anode and a cathode, respectively. For example, the first drive electrode 511 and the conductive member 521 are located in the same structural layer. For example, the first driving electrode 511 and the conductive member 521 may be obtained by patterning the same conductive layer (e.g., a single conductive layer) using the same patterning process.

For example, as shown in fig. 1A and 1B, the second drive electrodes 512 of the plurality of light emitting sub-units 510 are integrated to form a common electrode layer 516 (e.g., cathode layer); the common electrode layer 516 extends from the array region 501 to the peripheral region 502, and overlaps and is directly electrically connected to the conductive member 521.

For example, as shown in fig. 1B, the electronic device substrate 500 further includes a first insulating layer 531, an intermediate conductive layer 532, a second insulating layer 533, and a driving back plate 534. For example, as shown in fig. 1B, the first insulating layer 531, the intermediate conductive layer 532, the second insulating layer 533, and the driving backplate 534 are sequentially disposed in a direction perpendicular to the driving backplate 534, and the first insulating layer 531 is closer to the first driving electrode 511 than the driving backplate 534.

For example, as shown in fig. 1B, the first insulating layer 531 includes a first via 5311 and a second via 5312, and the intermediate conductive layer 532 includes a first conductive structure 5321 and a second conductive structure 5322; the first driving electrode 511 is electrically connected to the first conductive structure 5321 through the first via 5311, and the second driving electrode 512 is electrically connected to the second conductive structure 5322 through the first conductive component 521 and the second via 5312.

For example, as shown in fig. 1B, the second insulating layer 533 includes a third via 5331 and a fourth via 5332, the first driving electrode 511 is electrically connected to the first region 5341 of the driving backplane 534 via the first via 5311, the first conductive structure 5321 and the third via 5331, and the second driving electrode 512 (the common electrode layer 516) is electrically connected to the second region 5342 of the driving backplane 534 via the first conductive component 521, the second via 5312, the second conductive structure 5322 and the fourth via 5332. For example, the first region 5341 of the driving backplate 534 is configured to provide a first signal (e.g., a first voltage, an anode voltage) to the first driving electrode 511, and the second region 5342 of the driving backplate 534 is configured to provide a second signal (e.g., a second voltage, a cathode voltage) to the second driving electrode 512, the first voltage being greater than the second voltage, for example.

For example, by providing the conductive member 521, the electrical connection performance of the common electrode layer 516 (e.g., cathode layer) and the second conductive structure 5322 can be improved.

The inventors of the present disclosure noted in their studies that the portion of the common electrode layer 516 is disposed in the gap between the conductive member 521 and the first driving electrode 511, which reduces the flatness of the common electrode layer 516, increases the risk of breakage of the common electrode layer 516 (i.e., increases the risk of disconnection), and reduces the degree of uniformity of the electrical signal on the common electrode layer 516. For example, the inventors of the present disclosure also noticed in the research that the side of the first insulating layer 531 close to the conductive member 521 may have a recess (not shown in the figure) between the orthographic projection of the first driving electrode 511 on the first insulating layer 531 and the orthographic projection of the conductive member 521 on the first insulating layer 531, in which case the flatness of the common electrode layer 516 is further reduced and the risk of breaking the common electrode layer 516 is further increased.

The inventors of the present disclosure also noticed in the research that the uniformity of the developing process and the etching process is poor in the process of patterning the same conductive layer using the same patterning process to obtain the first driving electrode 511 and the conductive member 521.

The following is an exemplary description of the etching process. As shown in fig. 1B, since the distance between the adjacent first driving electrodes 511 is smaller than the distance between the adjacent first driving electrodes 511 and the conductive member 521, the amount of the etching liquid or the etching gas between the adjacent first driving electrodes 511 is smaller than the amount of the etching liquid or the etching gas between the adjacent first driving electrodes 511 and the conductive member 521 during the etching process; in this case, the time required to obtain the conductive members 521 by etching is shorter than the time required to obtain the first drive electrodes 511 by etching, and, for the first drive electrodes 511 adjacent to the conductive members 521, the time required to obtain the sides of the first drive electrodes 511 adjacent to the conductive members 521 by etching is shorter than the time required to obtain the sides of the first drive electrodes 511 remote from the conductive members 521 by etching, that is, there is non-uniformity in etching. The above etching non-uniformity causes that the sizes and the central positions of the conductive member 521 and the first driving electrode 511 which are actually obtained may be shifted from the design values of the sizes and the central positions of the conductive member 521 and the first driving electrode 511, thereby possibly degrading the performance of the electronic device substrate 500.

The inventors of the present disclosure also noted in the research that the conductive members 521 are disposed only on three sides of the electronic device substrate 500, in which case the degree of uniformity of the electrical signal on the common electrode layer 516 (e.g., cathode layer) is further deteriorated and the uniformity of the developing process and the etching process is further deteriorated.

At least one embodiment of the disclosure provides an electronic device substrate, a manufacturing method thereof and an electronic device. The electronic device substrate includes a substrate base plate, a first insulating layer, a plurality of light emitting sub-units, a first conductive member, and a second conductive member. The plurality of light-emitting sub-units, the first conductive component and the second conductive component are arranged on one side of the first insulating layer, which is far away from the substrate base plate; the plurality of light emitting sub-units are arranged in an array area of the electronic device substrate, the first conductive component is arranged in a peripheral area of the electronic device substrate surrounding the array area, and the second conductive component is arranged between the first conductive component and the array area; the orthographic projection of the first conductive component on the substrate base plate is spaced from the orthographic projection of the second conductive component on the substrate base plate; each of the plurality of light emitting sub-units includes a first driving electrode and a second driving electrode configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer; the peripheral area further comprises a second common electrode layer, the first conductive part is electrically connected with the second common electrode layer, and the second common electrode layer is electrically connected with the first common electrode layer; and the first conductive part, the second conductive part and the first driving electrode are all in direct contact with the first insulating layer.

It should be noted that, in some examples or embodiments of the present disclosure, the first conductive component and the second conductive component are ring-shaped structures, and the ring-shaped structures refer to conductive structures having ring-shaped profiles, and do not limit whether the ring-shaped structures are continuous or not. For example, the ring structure may be a continuous ring structure or a discontinuous ring structure formed by an arrangement of conductive patterns. For example, the ring structure may be referred to as a conductive ring (e.g., a cathode ring).

For example, in some examples or embodiments of the present disclosure, the electronic device substrate further includes at least one of a third conductive component and a fourth conductive component, and the third conductive component and the fourth conductive component are ring-shaped structures.

It should be noted that, in some examples or embodiments of the present disclosure, the a component and the B component are located in the same structural layer (e.g., the same conductive structural layer), which means that the a component and the B component are both located on the same side of the C component and are both in direct contact with the C component, and the orthographic projection of the a component on the electronic device substrate and the orthographic projection of the B component on the electronic device substrate are spaced apart. For example, the a component and the B component are located in the same structural layer may also mean that the a component and the B component are obtained by patterning the same film layer (e.g., conductive layer) using the same patterning process.

For example, the electronic device substrate provided by at least one embodiment of the present disclosure may be implemented as a display substrate (e.g., a display panel, an organic light emitting diode display panel) or a light emitting substrate (e.g., a backlight), etc.

In the following, non-limiting description of the electronic device substrate provided by the embodiments of the disclosure is provided by several examples or embodiments, and as described below, different features of these specific examples or embodiments may be combined with each other without mutual conflict, so as to obtain new examples or embodiments, and these new examples or embodiments also belong to the protection scope of the disclosure.

Fig. 2A illustrates a schematic plan view of an electronic device substrate 100 provided by at least one embodiment of the present disclosure. Fig. 2B illustrates a schematic cross-sectional view of the electronic device substrate 100 illustrated in fig. 2A. Fig. 2C shows a portion of the electronic device substrate 100 shown in fig. 2A (the common electrode layer or cathode layer is not shown).

As shown in fig. 2A and 2C, the electronic device substrate 100 includes an array region 101 and a peripheral region 102 surrounding the array region 101.

As shown in fig. 2A and 2C, the array region 101 includes a plurality of light emitting sub-units 110 (e.g., display sub-pixels), and the plurality of light emitting sub-units 110 are arranged in, for example, a plurality of rows and a plurality of columns (i.e., an array arrangement). It should be noted that, for the sake of clarity, the electronic device substrate 100 illustrated in fig. 2A only shows six light-emitting subunits, but the embodiments of the disclosure are not limited thereto, and the light-emitting subunits included in the electronic device substrate 100 may be set according to practical application requirements. For example, the electronic device substrate 100 may include 1920 × 1080 light emitting subunits.

As shown in fig. 2B, each of the plurality of light emitting sub-units 110 includes a first driving electrode 111, a second driving electrode 112, and a light emitting layer 113 interposed between the first driving electrode 111 and the second driving electrode 112. For example, the first driving electrode 111 and the second driving electrode 112 are configured to apply a light emission driving voltage (apply a light emission driving voltage to the light emitting layer 113) so that the light emitting layer 113 emits light, and the intensity of the light emitted by the light emitting layer 113 corresponds to the value of the light emission driving voltage. For example, the light emission driving voltage is a difference between the voltage of the first driving electrode 111 and the voltage of the second driving electrode 112.

For example, the first driving electrode 111 and the second driving electrode 112 are an anode and a cathode, respectively. For example, the light emitting layers 113 of the plurality of light emitting sub-units 110 are integrally formed into the light emitting material layer 1131. For example, the light emitting layers 113 of the plurality of light emitting sub-units 110 are located in the same structural layer and connected to each other. For example, the light emitting layers 113 of the plurality of light emitting sub-units 110 are made of the same material and emit light of the same color (e.g., white light or blue light); in this case, the electronic device substrate 100 further includes a color film layer or a wavelength conversion layer (not shown) disposed on the light emitting side of the light emitting sub-units 110, the color film layer includes a plurality of filters (e.g., filters of different colors), and the plurality of filters correspond to the plurality of light emitting sub-units 110 one-to-one. In other examples, the light emitting layers 113 of different light emitting sub-units 110 (e.g., different light emitting sub-units 110 in the same pixel) are made of different materials and configured to emit different colors, in which case the electronic device substrate 100 may not be provided with a color film layer.

As shown in fig. 2A and 2C, the peripheral region 102 includes a first conductive member 121 disposed around the array region 101 and a second conductive member 122 disposed between the first conductive member 121 and the array region 101. For example, as shown in fig. 2A and 2C, the peripheral region 102 further includes other regions 103 (e.g., bonding regions) located outside the first conductive members 121.

For example, as shown in fig. 2A and 2C, the electronic device substrate 100 further includes a third conductive member 123, the third conductive member 123 being disposed around the array region 101, and the second conductive member 122 being disposed around the third conductive member 123. As shown in FIG. 2B, light emitting material layer 1131 extends onto third conductive feature 123 and at least partially overlaps (e.g., partially overlaps) third conductive feature 123. For example, as shown in fig. 2B, the light emitting layer 113 of the light emitting sub-unit 110 adjacent to the third conductive member 123 extends onto the third conductive member 123 and at least partially overlaps (e.g., partially overlaps) the third conductive member 123.

As shown in fig. 2B, the electronic device substrate 100 further includes a first insulating layer 131 and a substrate 1340. The plurality of light emitting sub-units 110, the first conductive parts 121, the second conductive parts 122 and the third conductive parts 123 are all arranged on one side of the first insulating layer 131 far away from the substrate base 1340; first conductive feature 121, second conductive feature 122, and third conductive feature 123 are all in direct contact with first insulating layer 131.

For example, as shown in fig. 2A and 2C, first conductive member 121, second conductive member 122, and third conductive member 123 are ring-shaped structures. For example, the ring structure may be referred to as a conductive ring (e.g., a cathode ring).

For example, an orthogonal projection of the first conductive member 121 on the substrate base of the electronic device base plate (see the substrate base 1340 of fig. 2B and 9) is spaced apart from an orthogonal projection of the second conductive member 122 on the substrate base plate.

For example, as shown in fig. 2A and 2C, second conductive member 122 is not directly electrically connected to first conductive member 121, and third conductive member 123 is not directly electrically connected to second conductive member 122. It should be noted that in some examples and embodiments of the present disclosure, that two conductive components are not directly electrically connected means that the two conductive components are electrically isolated from each other without the aid of other conductive structures; in the case where the other conductive structure is electrically connected to both conductive members at the same time, both conductive members are electrically connected. For example, the second conductive member 122 and the first conductive member 121 are not directly electrically connected without the second common electrode layer 115.

It should be noted that, for the electronic device substrate 100 shown in fig. 2A and 2B and the electronic device substrate 100 provided in other examples and embodiments of the present disclosure, the third conductive component 123 may not be provided, and is not described again. For example, other suitable numbers (e.g., two) of second conductive members 122 may be disposed between the first conductive members 121 and the array region 101 according to practical application requirements.

For example, as shown in fig. 2B, the second driving electrodes 112 of the plurality of light emitting sub-units 110 are integrated to form a first common electrode layer 114; for example, there is no interface between the second driving electrodes 112 of the adjacent light emitting sub-units 110.

For example, as shown in fig. 2B, the peripheral region 102 further includes a second common electrode layer 115, and the first conductive component 121, the second conductive component 122 and the third conductive component 123 are all electrically connected to the second common electrode layer 115; the second common electrode layer 115 is electrically connected to the first common electrode layer 114. For example, the first conductive part 121, the second conductive part 122, and the third conductive part 123 are all overlapped with the second common electrode layer 115 and are respectively and directly electrically connected with the second common electrode layer 115.

In some embodiments, the first conductive part 121 is electrically connected to the second common electrode layer 115, and the second conductive part 122 and the third conductive part 123 are not electrically connected to the second common electrode layer 115, in which case the second conductive part 122 (and the third conductive part 123) and the second common electrode layer 115 are provided with an insulating layer (e.g., the intermediate insulating layer 191 in fig. 11).

For example, as shown in fig. 2B, first drive electrode 111, first conductive feature 121, second conductive feature 122, and third conductive feature 123 are located in the same structural layer; for example, the same patterning process may be used to pattern the same conductive layer (single conductive layer) to obtain the first drive electrode 111, the first conductive part 121, the second conductive part 122, and the third conductive part 123.

For example, as shown in fig. 2B, the second common electrode layer 115 is integrated with the first common electrode layer 114 to form a common electrode layer 116 (e.g., a cathode layer). For example, as shown in fig. 2A, the common electrode layer 116 extends from the array region to the peripheral region and overlaps with the first conductive member; as shown in fig. 2A, the common electrode layer 116 is a continuous structure; there is no interface between the second common electrode layer 115 and the first common electrode layer 114; in this case, the second driving electrode 112 is a portion of the common electrode layer 116 corresponding to the first driving electrode 111, and the second common electrode layer 115 is a portion of the common electrode layer 116 corresponding to the conductive members (e.g., the first conductive member 121, the second conductive member 122, and the third conductive member 123).

For example, by making the first conductive part 121 have a ring structure, the uniformity of the electrical signal on the common electrode layer 116 (e.g., cathode layer) can be improved. For example, by making the first conductive part 121 a ring structure, the etching uniformity may also be improved.

For example, as shown in fig. 2A and 2C, by providing the second conductive part 122 and the third conductive part 123, the risk of breaking the common electrode layer 116 (e.g., reducing the length of different regions of the common electrode layer 116 extending in a direction perpendicular to the panel surface of the electronic device substrate) may be reduced, the flatness of the common electrode layer 116 (e.g., avoiding portions of the common electrode layer 116 falling into the gap between the adjacent first conductive part 121 and the first driving electrode 111) and the uniformity of the electrical signal on the common electrode layer 116 may be improved, and the developing and etching uniformity may be improved, that is, the uniformity of the product may be improved while ensuring the process success rate.

For example, by providing the second conductive member 122 and the third conductive member 123, the amount of etching liquid (or etching gas) around the first conductive member 121 can also be reduced in the etching process, and therefore, the time required to obtain the first conductive member 121 (cathode ring) by etching can be made closer to the time required to obtain the first drive electrode 111 by etching, whereby the etching uniformity can be improved.

For example, the spacing between the first conductive part 121 and the second conductive part 122 is equal to the spacing between the first driving electrodes 111 of the adjacent light emitting sub-units 110; in this case, the amount of the etching liquid (or etching gas) around the first conductive member 121 may be made the same as or close to the amount of the etching liquid (or etching gas) around the first driving electrode 111, whereby the developing and etching uniformity may be further improved. For example, by making the interval between the first conductive part 121 and the second conductive part 122 equal to the interval between the first driving electrodes 111 of the adjacent light emitting sub-units 110, it is also possible to avoid that a portion of the common electrode layer 116 falls into the gap between the first conductive part 121 and the second conductive part 122, thereby further improving the uniformity of the electrical signal on the common electrode layer 116.

For example, the spacing between the first conductive part 121 and the second conductive part 122, the spacing between the third conductive part 123 and the light emitting sub-unit 110 adjacent thereto, and the spacing between the first driving electrodes 111 of the adjacent light emitting sub-units 110 are equal to each other, whereby the uniformity of the electrical signal on the common electrode layer 116 may be further improved, and the developing and etching uniformity may be further improved. For example, the spacing between the second conductive part 122 and the third conductive part 123 may also be equal to the spacing between the first driving electrodes 111 of the adjacent light emitting sub-units 110.

For example, as shown in fig. 2C, the pitch between adjacent conductive members (e.g., the pitch between the first conductive member 121 and the second conductive member 122) refers to a pitch in a direction pointing from the array region 101 (e.g., the center of the array region 101) to the peripheral region 102. For example, as shown in fig. 2C, the direction pointing from the array region 101 to the peripheral region 102 may be at least one of the first direction D1 and the second direction D2 shown in fig. 2C, that is, the pitch between adjacent conductive members refers to the pitch of adjacent conductive members in the first direction D1, the pitch of adjacent conductive members in the second direction D2, or the pitch of adjacent conductive members in the first direction D1 and the pitch of the second direction D2. For example, the direction pointing from the array region 101 to the peripheral region 102 is perpendicular to the extending direction of the corresponding region of the conductive member. The first direction D1 and the second direction D2 intersect (e.g., are perpendicular).

For example, as shown in FIGS. 2A-2C, the ring width of second conductive feature 122 is smaller than the ring width of first conductive feature 121. For example, by making the loop width of the first conductive part 121 larger than the loop width of the second conductive part 122, the contact area of the common electrode layer 116 and the first conductive part 121 (cathode loop) can be increased, whereby the contact resistance between the common electrode layer 116 and the first conductive part 121 can be reduced, the flatness of the common electrode layer 116 can be further increased, and the risk of disconnection can be further reduced.

For example, as shown in FIGS. 2A-2C, the loop width of second conductive feature 122 is equal to the loop width of third conductive feature 123. For example, the loop width of second conductive feature 122 and the loop width of third conductive feature 123 are both equal to the width of first drive electrode 111. For example, by making the loop width of the second conductive part 122 equal to that of the third conductive part 123, the conductive pattern distribution of the structural layer where the conductive part and the first driving electrode 111 are located can be made more uniform, thereby further improving the developing and etching uniformity.

For example, the loop width of the conductive member refers to a width in a direction (e.g., at least one of the first direction D1 and the second direction D2) directed from the array region 101 to the peripheral region 102, and the width (or size) of the first drive electrode 111 refers to a width (or size) of the first drive electrode 111 in a direction (e.g., at least one of the first direction D1 and the second direction D2) directed from the array region 101 to the peripheral region 102. For example, the fact that the loop width of the conductive member is equal to the width of the electrode means that the loop width of the conductive member in the first direction is equal to the dimension of the electrode in the first direction and/or the loop width of the conductive member in the second direction is equal to the dimension of the electrode in the second direction.

For example, as shown in fig. 2A and 2C, the orthogonal projection of the second common electrode layer 115 on the plane of the first driving electrode 111 is a continuous plane; the orthographic projection of the second common electrode layer 115 (or the common electrode layer 116) on the plane of the first driving electrode 111 completely covers the first conductive member 121. For example, by making the orthogonal projection of the second common electrode layer 115 (or the common electrode layer 116) on the plane of the first driving electrode 111 completely cover the first conductive member 121, the contact area between the common electrode layer 116 and the first conductive member 121 (cathode ring) can be increased, thereby further reducing the contact resistance between the common electrode layer 116 and the first conductive member 121, and reducing the requirements for the manufacturing accuracy and alignment accuracy of the first conductive member 121 (cathode ring). It should be noted that the continuous plane refers to a plane without a hollow structure or an opening.

For example, as shown in fig. 2B, the electronic device substrate 100 further includes an intermediate conductive layer 132, a second insulating layer 133, and a driving back plate 134. For example, as shown in fig. 2B, the driving back plate 134, the second insulating layer 133, the intermediate conductive layer 132, and the first insulating layer 131 are sequentially disposed along the third direction D3, and as shown in fig. 2B, the first insulating layer 131 is closer to the first driving electrode 111 than the driving back plate 134. For example, the first direction D1, the second direction D2, and the third direction D3 intersect each other (e.g., are perpendicular to each other). As shown in fig. 9, the driving back plate 134 includes a substrate base 1340 and driving elements (not shown in the figure, such as thin film transistors, capacitors, etc.) disposed on the substrate base 1340, and the substrate base 1340 is located on a side of the driving elements away from the first insulating layer 131.

For example, as shown in fig. 2B, first insulating layer 131 includes first via 1311 and second via 1312, first via 1311 and second via 1312 are filled with a conductive material (e.g., a metal material), and intermediate conductive layer 132 includes first conductive structure 1321 and second conductive structure 1322; first drive electrode 111 is electrically connected to first electrically conductive structure 1321 via first via 1311 (the electrically conductive material in first via 1311), second drive electrode 112 is electrically connected to second electrically conductive structure 1322 via first electrically conductive member 121 and second via 1312 (the electrically conductive material in second via 1312), and second electrically conductive member 122 and intermediate electrically conductive layer 132 are not directly electrically connected.

For example, the orthographic projection of second conductive member 122 on the substrate base plate, the orthographic projection of first conductive structure 1321 on the substrate base plate, and the orthographic projection of second conductive structure 1322 on the substrate base plate are spaced apart such that second conductive member 122 and intermediate conductive layer 132 are not directly electrically connected.

For example, as shown in fig. 2B, the second insulating layer 133 includes a third via 1331 and a fourth via 1332, the third via 1331 and the fourth via 1332 are filled with a conductive material (e.g., a metal material), the first driving electrode 111 is electrically connected to the first region 1341 of the driving back plate 134 via the first via 1311 (the conductive material in the first via 1311), the first conductive structure 1321 and the third via 1331 (the conductive material in the third via 1331), the second driving electrode 112 is electrically connected to the second region 1342 of the driving back plate 134 via the first conductive member 121, the second via 1312 (the conductive material in the second via 1312), the second conductive structure 1322 and the fourth via 1332 (the conductive material in the fourth via 1332), and the second conductive member 122 and the driving back plate 134 are not directly electrically connected. For example, the first region 1341 of the driving back plate 134 is configured to provide a first signal (e.g., a first voltage, an anode voltage) to the first driving electrode 111, and the second region 1342 of the driving back plate 134 is configured to provide a second signal (e.g., a second voltage, a cathode voltage) to the second driving electrode 112, the first voltage being greater than the second voltage, for example. For example, the first signals provided by the first region 1341 to the first driving electrodes 111 of the plurality of light emitting sub-units may be set according to practical application requirements (e.g., different from each other). For example, the second signals provided by the second region 1342 to the second driving electrodes 112 of the plurality of light emitting sub-units may be equal to each other. For example, the first signal may be referred to as a pixel driving signal. For example, the second signal may be referred to as a power supply signal.

For example, the second conductive member 122 and the driving backplane 134 are not electrically connected, meaning that the second conductive member 122 does not directly receive the signal provided by the driving backplane 134. For example, as shown in fig. 2B, the regions of the first and second insulating

layers

131 and 133 corresponding to the second conductive member 122 (i.e., the region of the first insulating layer 131 overlapping the orthographic projection of the second conductive member 122 on the first insulating layer 131 and the region of the second insulating layer 133 overlapping the orthographic projection of the second conductive member 122 on the second insulating layer 133) are not provided with a via, and thus, the second conductive member 122 cannot directly receive the signal provided by the driving backplane 134 via the vias in the first and second insulating

layers

131 and 133. For example, in the case where the second conductive member 122 is not electrically connected to the second common electrode layer, the second conductive member 122 is in a floating state. For example, when the second conductive part 122 is electrically connected to the second common electrode layer, the second conductive part 122 may receive a signal provided by the driving backplane 134 via the second common electrode layer.

For example, as shown in fig. 2B, the number of the first driving electrodes 111, the number of the first vias 1311, the number of the first conductive structures 1321, and the number of the third vias 1331 are equal to each other. For example, the first insulating layer 131 includes a plurality of second vias 1312 therein; in this case, the plurality of second vias 1312 are arranged in a ring shape on the entire orthographic projection of the second insulating layer 133, and the common electrode layer 116 (the second driving electrode 112) is electrically connected to the second conductive structure 1322 and the second region 1342 of the driving back plate 134 via the first conductive member 121 and the plurality of second vias 1312. For example, by including the plurality of second vias 1312 in the first insulating layer 131, the resistance-capacitance delay can be reduced, and the uniformity of the signal on the common electrode layer 116 (the second driving electrode 112) can be improved. For example, the common electrode layer 116 is a monolithic electrode.

For example, second electrically conductive structures 1322 may be continuous annular structures, in which case, the number of second electrically conductive structures 1322 is one; for another example, the second conductive structure 1322 may also be a discontinuous ring-shaped structure formed by arranging a plurality of conductive patterns; in this case, the number of the conductive patterns of the second conductive structure 1322 is equal to the number of the second vias 1312.

For example, the electronic device substrate 100 further includes a first encapsulation layer, a color film layer, and a second encapsulation layer (not shown in the figure) sequentially disposed on the common electrode layer 116 along the third direction D3, where the second encapsulation layer is located on a side of the first encapsulation layer away from the common electrode layer 116. For example, the first encapsulation layer and the second encapsulation layer can both protect the light-emitting layer 113, and the protection capability of the second encapsulation layer for the light-emitting layer 113 is better than that of the first encapsulation layer for the light-emitting layer 113.

For example, as shown in fig. 2A and 2C, first conductive part 121, second conductive part 122, and third conductive part 123 are implemented as rectangular rings, but embodiments of the present disclosure are not limited thereto, e.g., first conductive part 121, second conductive part 122, and third conductive part 123 may also be implemented as circular rings or rings having other suitable shapes.

For example, as shown in fig. 2A and 2C, each of first conductive member 121, second conductive member 122, and third conductive member 123 is a continuous ring structure, for example, first conductive member 121 is a continuous first ring structure, second conductive member 122 is a continuous second ring structure, and third conductive member 123 is a continuous third ring structure, but the embodiment of the present disclosure is not limited thereto.

For example, one or more of the first conductive member 121, the second conductive member 122, and the third conductive member 123 may further include a plurality of electrode patterns disposed at intervals.

For example, by making one or more of the first conductive part 121, the second conductive part 122, and the third conductive part 123 further include a plurality of electrode patterns disposed at intervals, the developing and etching uniformity may be further improved, and thus the performance of the electronic device substrate 100 may be further improved. For example, by making one or more of the first conductive part 121, the second conductive part 122, and the third conductive part 123 further include a plurality of electrode patterns disposed at intervals, it is possible to make the etching liquid (or the etching gas) flow through gaps between the plurality of electrode patterns, and thus it is possible to reduce the time required to make the etching liquid (or the etching gas) stably distributed (e.g., stably and uniformly distributed).

The following is an exemplary description with reference to fig. 3A and 3B. Fig. 3A is a schematic plan view of another electronic device substrate 100 provided by at least one embodiment of the present disclosure; fig. 3B is a schematic plan view of another electronic device substrate 100 according to at least one embodiment of the disclosure. For clarity, the common electrode layer is not shown in both fig. 3A and 3B.

In one example, as shown in fig. 3A, each of the first conductive part 121 and the second conductive part 122 is a continuous ring-shaped structure, the third conductive part 123 includes a plurality of third electrode patterns 1231 disposed at intervals, and the plurality of third electrode patterns 1231 are arranged in a ring shape as a whole.

For example, as shown in fig. 3A, the third electrode pattern 1231 has the same shape and size as the first driving electrode 111, in which case, the developing and etching uniformity and the performance of the electronic device substrate 100 may be further improved. For example, by making the third electrode pattern 1231 have the same shape and size as the first driving electrode 111, the third electrode pattern 1231 and the first driving electrode 111 can be made to have the same blocking capability against the etching liquid (or etching gas), and thus the time required to make the etching liquid (or etching gas) stably distributed (e.g., stably uniformly distributed) can be further reduced.

For example, as shown in fig. 3A, the interval between the adjacent third electrode patterns 1231 is equal to the interval between the adjacent first driving electrodes 111. For example, the spacing between the adjacent third electrode patterns 1231 in the first direction D1 is equal to the spacing between the adjacent first driving electrodes 111 in the first direction D1, and/or the spacing between the adjacent third electrode patterns 1231 in the second direction D2 is equal to the spacing between the adjacent first driving electrodes 111 in the second direction D2; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved.

In another example, as shown in FIG. 3B, the first conductive feature 121 is a continuous ring-like structure; the second conductive member 122 includes a plurality of first electrode patterns 1221 arranged at intervals, the plurality of first electrode patterns 1221 being arranged in a ring shape as a whole; the third conductive member 123 includes a plurality of third electrode patterns 1231 arranged at intervals, and the plurality of third electrode patterns 1231 are arranged in a ring shape as a whole. For example, as shown in fig. 3B, the third electrode patterns 1231, the first electrode patterns 1221, and the first driving electrodes 111 all have the same shape and size.

For example, as shown in fig. 3B, the pitch between the adjacent third electrode patterns 1231, the pitch between the adjacent first electrode patterns 1221, and the pitch between the adjacent first driving electrodes 111 are equal to each other; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. For example, as shown in fig. 3B, in a direction (e.g., the first direction D1 and/or the second direction D2) directed from the array region 101 to the peripheral region 102, a spacing between adjacent first electrode patterns 1221 and the first conductive members 121, a spacing between adjacent third electrode patterns 1231 and the first driving electrodes 111, and a spacing between adjacent first driving electrodes 111 are equal to each other; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. For example, the spacing between the adjacent third electrode patterns 1231 and the first electrode patterns 1221 may also be equal to the spacing between the adjacent first driving electrodes 111.

Fig. 4A illustrates a schematic plan view of yet another electronic device substrate 100 provided by at least one embodiment of the present disclosure. Fig. 4B illustrates a cross-sectional schematic view of the electronic device substrate 100 illustrated in fig. 4A. Fig. 4C shows a portion of the electronic device substrate 100 shown in fig. 4A (the common electrode layer or cathode layer is not shown). The electronic device substrate 100 shown in fig. 4A and 4B is similar to the electronic device substrate 100 shown in fig. 2A and 2B, and only the differences therebetween are described herein, and the description of the same parts is omitted.

As shown in fig. 4A-4C, the electronic device substrate 100 shown in fig. 4A-4C has the following differences compared to the electronic device substrate 100 shown in fig. 2A and 2B: (1) the ring width of the first conductive member 121 of the electronic device substrate 100 shown in fig. 4A and 4B is equal to the ring width of the second conductive member 122; (2) each of the first conductive member 121, the second conductive member 122, and the third conductive member 123 includes a plurality of electrode patterns arranged at intervals.

For example, by making the loop width of the first conductive part 121 equal to the loop width of the second conductive part 122, the development and etching uniformity and the performance of the electronic device substrate 100 may be further improved.

For example, as shown in fig. 4A and 4C, the first conductive member 121 includes a plurality of second electrode patterns 1211 disposed at intervals, the plurality of second electrode patterns 1211 being arranged in a ring shape as a whole; the second conductive member 122 includes a plurality of first electrode patterns 1221 arranged at intervals, the plurality of first electrode patterns 1221 being arranged in a ring shape as a whole; the third conductive member 123 includes a plurality of third electrode patterns 1231 arranged at intervals, the plurality of third electrode patterns 1231 being arranged in a ring shape as a whole; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. For example, as shown in fig. 4C, the third electrode pattern 1231, the second electrode pattern 1211, the first electrode pattern 1221, and the first driving electrode 111 have substantially the same (e.g., the same) shape and size; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. The substantially same shape means substantially the same shape, for example, the third electrode pattern 1231, the second electrode pattern 1211, the first electrode pattern 1221, and the first driving electrode 111 may be triangular, quadrangular, hexagonal, etc.; having substantially the same size means that the sizes are substantially the same, allowing an error range of within 10% for any two of the third electrode pattern 1231, the second electrode pattern 1211, the first electrode pattern 1221, and the first driving electrode 111; for example, the third electrode pattern 1231, the second electrode pattern 1211, the first electrode pattern 1221, and the first driving electrode 111 have substantially the same (e.g., the same) area. For example, having substantially the same area means that the areas are substantially the same, allowing an error range of within 10% for any two of the third electrode pattern 1231, the second electrode pattern 1211, the first electrode pattern 1221, and the first driving electrode 111. For example, as shown in fig. 4A, in a direction (e.g., the first direction D1 and/or the second direction D2) pointing from the array region 101 to the peripheral region 102, a spacing between adjacent first electrode patterns 1221 and second electrode patterns 1211, a spacing between adjacent third electrode patterns 1231 and first driving electrodes 111, and a spacing between adjacent first driving electrodes 111 are substantially equal (e.g., equal); in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. For example, the spacing between the adjacent third electrode patterns 1231 and the first electrode patterns 1221 may also be equal to the spacing between the adjacent first driving electrodes 111. The fact that the a parameter and the B parameter are substantially equal means that the difference between the a parameter and the B parameter is less than 10% × (average value of the a parameter and the B parameter).

For example, as shown in fig. 4A and 4C, a plurality of electrode patterns (the third electrode pattern 1231, the second electrode pattern 1211, and the first electrode pattern 1221) are arranged in a plurality of rows and columns (i.e., an array arrangement). For example, as shown in fig. 4A and 4C, adjacent electrode patterns of the plurality of electrode patterns are not directly electrically connected; for example, a gap exists between adjacent electrode patterns of the plurality of electrode patterns.

For example, as shown in FIG. 4C, the peripheral region 102 also includes other regions 103 (e.g., bonded regions) that are located outside the first conductive features 121. For example, the peripheral region 102 further includes a lead 1031, the lead 1031 extending from the driving circuit located in the other region 103 (e.g., the bonding region) to the second electrode pattern 1211 of the first conductive member 121.

Fig. 5A illustrates a schematic plan view of yet another electronic device substrate 100 provided by at least one embodiment of the present disclosure. Fig. 5B illustrates a cross-sectional schematic view of the electronic device substrate 100 illustrated in fig. 5A. Fig. 5C shows a portion of the electronic device substrate 100 shown in fig. 5A (the common electrode layer or cathode layer is not shown). The electronic device substrate 100 shown in fig. 5A and 5B is similar to the electronic device substrate 100 shown in fig. 4A to 4C, and only the differences therebetween are described herein, and the description of the same parts is omitted.

As shown in fig. 5A to 5C, compared to the electronic device substrate 100 shown in fig. 4A to 4C, the peripheral region 102 of the electronic device substrate 100 shown in fig. 5A to 5C further includes a fourth conductive component 124 surrounding the first conductive component 121, and the fourth conductive component 124 overlaps the second common electrode layer 115 and is electrically connected to the second common electrode layer 115. The fourth conductive member 124 is disposed on a side of the first insulating layer 131 away from the base substrate 1340 and is in direct contact with the first insulating layer 131.

For example, by making the peripheral region 102 of the electronic device substrate 100 shown in fig. 5A-5C further include the fourth conductive part 124 surrounding the first conductive part 121, the development and etching uniformity and the performance of the electronic device substrate 100 may be further improved. For example, by providing the fourth conductive member 124, the effective time required to obtain the first conductive member 121 (the outer ring of the first conductive member 121) by etching can be increased, whereby the effective time required to obtain the first conductive member 121 by etching and the effective time required to obtain the first drive electrode 111 by etching can be made closer.

For example, as shown in fig. 5A to 5C, the spacing between the fourth conductive part 124 and the first conductive part 121 is equal to the spacing between the adjacent first drive electrodes 111; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. For example, as shown in fig. 5A to 5C, the fourth conductive member 124 includes a plurality of fourth electrode patterns 1241 arranged at intervals, the plurality of fourth electrode patterns 1241 being arranged in a ring shape as a whole; in this case, the developing and etching uniformity and the performance of the electronic device substrate 100 can be further improved. For example, the fourth electrode pattern 1241 and the first driving electrode 111 have the same shape and size.

It should be noted that the fourth conductive component may also be disposed on the electronic device substrate 100 according to other examples or embodiments of the disclosure (e.g., the examples or embodiments shown in fig. 2A, fig. 3A, fig. 6A, and fig. 7), and details thereof are not repeated.

Fig. 6A illustrates a schematic plan view of yet another electronic device substrate 100 provided by at least one embodiment of the present disclosure. Fig. 6B illustrates a cross-sectional schematic view of the electronic device substrate 100 illustrated in fig. 6A. Fig. 6C shows a portion of the electronic device substrate 100 shown in fig. 6A (the common electrode layer or cathode layer is not shown). The electronic device substrate 100 shown in fig. 6A and 6B is similar to the electronic device substrate 100 shown in fig. 2A to 2C, and only the differences therebetween are described herein, and the description of the same parts is omitted.

As shown in fig. 6A-6C, compared to the electronic device substrate 100 shown in fig. 2A-2C, the peripheral region 102 of the electronic device substrate 100 shown in fig. 6A-6C further includes an electrical connection 125.

For example, as shown in fig. 6A to 6C, the electrical connection portion 125 is provided between the first conductive member 121 and the second conductive member 122 and between the second conductive member 122 and the third conductive member 123, the second conductive member 122 is connected to the first conductive member 121 through the electrical connection portion 125, and the second conductive member 122 is connected to the third conductive member 123 through the electrical connection portion 125. For example, the first and second

conductive members

121 and 122, the third conductive member 123, and the electrical connection portion 125 are integrally formed, that is, there is no interface between any adjacent two of the first and second

conductive members

121 and 122, the third conductive member 123, and the electrical connection portion 125. For example, as shown in fig. 6A-6C, first conductive component 121, second conductive component 122, third conductive component 123, and electrical connection 125 form one continuous loop structure 120. For example, by providing the electrical connection portion 125, the contact area can be further increased, and the contact resistance can be reduced.

Note that third conductive member 123 is not limited to being integrated with second conductive member 122 (being integrated with second conductive member 122 via electrical connection 125), and in some examples, third conductive member 123 may not be directly electrically connected to second conductive member 122. This is illustrated in connection with fig. 7. Fig. 7 illustrates a schematic cross-sectional view of yet another electronic device substrate 100 provided by at least one embodiment of the present disclosure. The electronic device substrate 100 shown in fig. 7 is similar to the electronic device substrate 100 shown in fig. 6A to 6C, and only the differences between the two are described herein, and the description of the same parts is omitted.

For example, as shown in fig. 7, compared to the electronic device substrate 100 shown in fig. 6A-6C, the electrical connection 125 shown in fig. 7 is only disposed between the first conductive member 121 and the second conductive member 122, and such that the first conductive member 121, the second conductive member 122, and the electrical connection 125 form one continuous ring-shaped structure 120. The ring structure 120 and the third conductive member 123 are disposed at an interval and are not directly electrically connected. For example, the pitch between the ring-shaped structure 120 and the third conductive member 123 (i.e., the pitch between the second conductive member 122 and the third conductive member 123), the pitch between the third conductive member 123 and the first driving electrode 111, and the pitch between adjacent first driving electrodes 111 are equal to each other.

In some examples, the first insulating layer 131 further includes a recess. For example, the recess is formed in the process of forming the first conductive member 121 and the second conductive member 122.

Fig. 10 illustrates a recess 1315 provided by at least one embodiment of the disclosure. As shown in fig. 10, the recess 1315 is located on a side of the first insulating layer 131 close to the first conductive part 121, and is located between an orthographic projection of the first conductive part 121 on the first insulating layer 131 and an orthographic projection of the first driving electrode 111 (e.g., the first driving electrode 111 located at the outermost edge of the array region) on the first insulating layer 131; an orthogonal projection of the recess 1315, an orthogonal projection of the first conductive member 121, an orthogonal projection of the second conductive member 122, and an orthogonal projection of the first drive electrode 111 on the substrate do not overlap. For example, orthographic projection non-overlapping means that the orthographic projections are spaced apart or that the sides of the orthographic projections are in direct contact.

As shown in fig. 10, a region of the first insulating layer 131 corresponding to the gap between the first conductive part 121 and the fourth conductive part 124 includes one recess; the region of the first insulating layer 131 corresponding to the gap between the first conductive part 121 and the second conductive part 122 includes one recess; the region of the first insulating layer 131 corresponding to the gap between the second conductive part 122 and the third conductive part 123 includes one recess; a region of the first insulating layer 131 corresponding to the gap between the third conductive member 123 and the first driving electrode 111 includes one recess. For example, the gap of the first insulating layer 131 corresponding to between the adjacent first driving electrodes 111 may also include a recess.

For example, a region of the first insulating layer 531 of the electronic device substrate 500 of fig. 1A and 1B corresponding to the gap between the conductive member 521 and the first driving electrode 511 may also include one recess (not shown in fig. 1A and 1B). For example, the size of the recess of the electronic device substrate 100 including between the first to fourth conductive members 121 to 124 and the first drive electrode 111 shown in fig. 10 is smaller compared to the recess of the electronic device substrate 500 of fig. 1A and 1B, because the spacing between adjacent electrodes (e.g., the first and second conductive members 121 and 122) is smaller. Therefore, the flatness of the common electrode layer 116 can be further improved.

Fig. 11 illustrates a schematic cross-sectional view of yet another electronic device substrate 100 provided by at least one embodiment of the present disclosure. The electronic device substrate 100 shown in fig. 11 is similar to the electronic device substrate 100 shown in fig. 5B, and only the differences between the two are described herein, and the descriptions of the same parts are omitted.

The electronic device substrate 100 shown in fig. 11 has the following differences compared to the electronic device substrate 100 shown in fig. 5B. (1) The electronic device substrate 100 shown in fig. 11 further includes a sensing region 180, wherein the sensing region 180 is disposed between the array region and the third conductive member 123 and includes a sensing element, which can sense temperature, for example, and is electrically connected to the driving back plate 134 via a via (not shown). (2) The electronic device substrate 100 shown in FIG. 11 further includes a fifth conductive member 129 (e.g., a conductive ring), the fifth conductive member 129 being disposed between the sensing region 180 and the array region (e.g., the sensing element 181 and the first drive electrode 111). (3) The electronic device substrate 100 shown in fig. 11 further includes an intermediate insulating layer 191, a first portion of which overlaps the third conductive part 123 and the second conductive part 122 and is located between the common electrode layer 116 and the third conductive part 123 (the second conductive part 122) so that the common electrode layer 116 and the third conductive part 123 (the second conductive part 122) are not electrically connected directly, in which case the third conductive part 123 (the second conductive part 122) is floating. For example, the second portion of the intermediate insulating layer overlaps the fifth conductive part 129 and is located between the common electrode layer 116 and the fifth conductive part 129 so that the common electrode layer 116 and the fifth conductive part 129 are not directly electrically connected, in which case the fifth conductive part 129 is floating. (4) The electronic device substrate 100 shown in fig. 11 includes two first conductive members 121.

At least one embodiment of the present disclosure also provides an electronic device. Fig. 8 is an exemplary block diagram of an electronic device provided by at least one embodiment of the present disclosure. As shown in fig. 8, the electronic device includes any one of the electronic device substrates provided by the embodiments of the present disclosure. The electronic device may be implemented as a display device, a light emitting device, or the like.

It should be noted that, for the electronic device substrate 100 and other components of the electronic device 10 (for example, the thin film transistor, the control device, the image data encoding/decoding device, the row scanning driver, the column scanning driver, the clock circuit, etc.), suitable components may be adopted, which should be understood by those skilled in the art, and are not described herein again, and should not be taken as a limitation to the present disclosure.

At least one embodiment of the present disclosure provides a method of manufacturing an electronic device substrate, including: providing a substrate base plate; forming a first insulating layer on a substrate; and forming a plurality of light emitting sub-units, a first conductive member and a second conductive member on a side of the first insulating layer away from the substrate base plate. The plurality of light emitting sub-units are arranged in an array area of the electronic device substrate, the first conductive component is arranged in a peripheral area of the electronic device substrate surrounding the array area, and the second conductive component is arranged between the first conductive component and the array area; the orthographic projection of the first conductive component on the substrate base plate is spaced from the orthographic projection of the second conductive component on the substrate base plate; each of the light emitting sub-units includes a first driving electrode and a second driving electrode stacked on each other, the first driving electrode and the second driving electrode being configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer; the peripheral area further comprises a second common electrode layer, the first conductive part is electrically connected with the second common electrode layer, and the second common electrode layer is electrically connected with the first common electrode layer; and the first conductive part, the second conductive part and the first driving electrode are all in direct contact with the first insulating layer.

For example, forming a plurality of light emitting sub-units in an array region of an electronic device substrate, and forming a plurality of light emitting sub-units, a first conductive member, and a second conductive member on a side of the first insulating layer away from the substrate, includes: forming a first conductive layer; patterning the first conductive layer to form a first drive electrode, a first conductive member, and a second conductive member of the plurality of light emitting sub-units; and forming a common electrode layer on the first driving electrode, the first conductive member, and the second conductive member. The common electrode layer includes a first common electrode layer and a second common electrode layer which are integrated.

Taking the electronic device substrate shown in fig. 4A-4C as an example, a method for manufacturing the electronic device substrate according to at least one embodiment of the present disclosure is exemplarily described below.

For example, at least one embodiment of the present disclosure provides a method for manufacturing an electronic device substrate, including the following steps S101 to S110.

Step S101: a driving back plate is provided.

For example, the driving back plate includes a first region configured to provide a first voltage and a second region configured to provide a second voltage, the first voltage being greater than the second voltage. For example, as shown in fig. 9, the driving backplate may include a substrate base plate, which is a semiconductor substrate base plate made of monocrystalline silicon, germanium, gallium arsenide, or other suitable semiconductor material. For example, the driving backplate may be implemented as a silicon-based driving backplate, i.e. the substrate base plate comprised by the driving backplate is made of monocrystalline silicon. For example, the driving backplane further includes a driving transistor, a switching transistor, a storage capacitor, and the like disposed on the substrate base. For example, the specific manufacturing method of the driving back plate can be referred to a semiconductor integrated circuit manufacturing process, and is not described herein again.

Step S102: and forming a second insulating layer on the driving back plate, forming a third via hole on the part of the second insulating layer corresponding to the first area, and forming a fourth via hole on the part of the second insulating layer corresponding to the second area.

For example, the number of third vias is equal to the number of light emitting sub-units to be formed. For example, the number (e.g., one or more) of the fourth vias may be set according to the actual application requirements. For example, the second insulating layer may be made of silicon dioxide or other suitable material.

Step S103: and filling the third via hole and the fourth via hole with a conductive material.

For example, the conductive material may be tungsten metal (W) or other suitable material. For example, when filling with a conductive material, if there is too much conductive material, the conductive material may be located outside the via; in this case, the conductive material outside the via may be removed by, for example, grinding to improve the electrical contact performance.

Step S104: an intermediate conductive layer is formed on a side of the second insulating layer remote from the driving backplane.

For example, the intermediate conductive layer includes a first conductive structure and a second conductive structure, which may be, for example, traces or other suitable conductive structures. For example, the number of the first conductive structures, the number of the third vias, and the number of the light emitting sub-units to be formed are equal to each other. For example, the number of the second conductive structures is equal to the number of the second electrode patterns of the first conductive member to be formed. For example, the plurality of second conductive structures are arranged in a ring shape surrounding the plurality of first conductive structures. For example, the first conductive structure at least partially overlaps the corresponding third via, and the second conductive structure at least partially overlaps the corresponding fourth via.

For example, each of the first and second conductive structures may be implemented as a multi-layer structure (having multiple layers in a direction perpendicular to the driving backplane). For example, each of the first and second conductive structures may include a three-layer stacked conductive layer of a material such as titanium (Ti), aluminum (Al), and titanium nitride (TiN) in this order, and the conductive layer made of titanium (Ti) is closer to the driving backplate than the conductive layer made of titanium nitride (TiN). For another example, each of the first and second conductive structures may include two stacked conductive layers of, for example, titanium (Ti) and aluminum (Al) in this order, and the conductive layer made of titanium (Ti) is closer to the driving back plate than the conductive layer made of aluminum (Al). For example, an insulating layer is provided between adjacent conductive layers, and thus, the adjacent conductive layers are electrically connected by a via. For example, each of the stacked conductive layers may have a thickness of about 5 nm to about 50 nm.

Step S105: and forming a first insulating layer on one side of the intermediate conductive layer far away from the second insulating layer, forming a first through hole on the part of the first insulating layer corresponding to the first area, and forming a second through hole on the part of the first insulating layer corresponding to the second area.

For example, the number of the first vias, the number of the third vias, and the number of the light emitting sub-units to be formed are equal to each other. For example, the number of the second vias, the number of the second conductive structures, and the number of the second conductive patterns to be formed are equal to each other. For example, the first insulating layer may be made of silicon dioxide or other suitable material.

Step S106: and filling the first via hole and the second via hole with a conductive material.

For example, the conductive material may be tungsten metal (W). For example, when filling with a conductive material, if there is too much conductive material, the conductive material may be located outside the via; in this case, the conductive material outside the via may be removed by, for example, grinding to improve the electrical contact performance.

Step S107: a first conductive layer is formed on a side of the first insulating layer away from the intermediate conductive layer, and the first conductive layer (e.g., a single conductive layer) is patterned using the same patterning process to form a first drive electrode, a first conductive feature, a second conductive feature, and a third conductive feature of the plurality of light emitting sub-units.

For example, each of the first conductive member, the second conductive member, and the third conductive member includes a plurality of electrode patterns arranged at intervals.

Step S108: and forming a light-emitting material layer on one side of the layer on which the first driving electrode is positioned, which is far away from the first insulating layer. For example, as shown in fig. 4B, the layer of light emitting material covers (e.g., completely covers) the first drive electrode of the light emitting subcell and a portion of the third conductive member. For example, the light emitting material layer includes light emitting layers corresponding to the plurality of light emitting sub-units in the same structural layer. For example, when the light emitting layers of the plurality of light emitting sub-units emit light of the same color, the light emitting layers of the plurality of light emitting sub-units are made of the same material and are integrally formed, and no interface exists between the light emitting layers of the plurality of light emitting sub-units.

Step S109: and forming a second conductive layer on the driving substrate on which the light-emitting material layer is formed, wherein the second conductive layer is a common electrode layer.

Step S110: and a first packaging layer, a color film layer and a second packaging layer are sequentially formed on one side of the common electrode layer, which is far away from the driving substrate.

For example, the material of the first conductive layer and the second conductive layer is selected from a metal, a metal alloy, and a transparent conductive material. At least one of the first conductive layer and the second conductive layer is a transparent or semitransparent electrode, and the transparent conductive material includes Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Cadmium Tin Oxide (CTO), tin oxide (SnO dioxide)₂) Zinc oxide (ZnO), and the like; the metal and metal alloy include gold (Au), aluminum (Al), indium (In), magnesium (Mg), calcium (Ca), and the like. For example, firstThe conductive layer is used to form an anode and the second conductive layer is used to form a cathode.

For example, by providing the second conductive part and the third conductive part, the risk of breaking the common electrode layer (e.g., reducing the length of different regions of the common electrode layer extending in a direction perpendicular to the panel surface of the electronic device substrate) can be reduced, the flatness of the common electrode layer (e.g., avoiding portions of the common electrode layer falling into the gap between the adjacent first conductive part and the first drive electrode) and the uniformity of the electrical signal on the common electrode layer can be improved, and the development and etching uniformity can be improved. For example, by providing the second conductive member and the third conductive member, the amount of etching liquid (or etching gas) around the first conductive member can also be reduced in the etching process, and therefore, the time required to obtain the first conductive member (cathode ring) by etching can be made closer to the time required to obtain the first drive electrode by etching, whereby etching uniformity can be improved.

Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims

1. An electronic device substrate comprises a substrate, a first insulating layer, a plurality of light emitting sub-units, a first conductive member and a second conductive member,

wherein the plurality of light emitting sub-units, the first conductive component and the second conductive component are arranged on one side of the first insulating layer far away from the substrate;

the plurality of light emitting sub-units are arranged in an array area of the electronic device substrate, the first conductive part is arranged in a peripheral area of the electronic device substrate surrounding the array area, and the second conductive part is arranged between the first conductive part and the array area;

the orthographic projection of the first conductive component on the substrate base plate is spaced from the orthographic projection of the second conductive component on the substrate base plate;

each of the plurality of light emitting sub-units comprises a first driving electrode and a second driving electrode configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer;

the peripheral region further comprises a second common electrode layer, the first conductive part is electrically connected with the second common electrode layer, and the second common electrode layer is electrically connected with the first common electrode layer; and

the first conductive member, the second conductive member, and the first drive electrode are all in direct contact with the first insulating layer;

the electronic device substrate further comprises a third conductive part, wherein the third conductive part is arranged on one side, far away from the substrate, of the first insulating layer, the third conductive part is arranged around the array region and is located in the same conductive structure layer with the first driving electrode, and the second conductive part is arranged around the third conductive part;

each of the plurality of light emitting sub-units includes a light emitting layer, the light emitting layers of the plurality of light emitting sub-units being integrated to form a light emitting material layer; and

the layer of light emitting material extends onto and at least partially overlaps the third conductive member.

2. The electronic device substrate according to claim 1, wherein the first conductive member and the second conductive member overlap the second common electrode layer;

the first conductive part, the second conductive part and the first driving electrode are also positioned in the same conductive structure layer;

the orthographic projection of the first conductive component on the substrate base plate, the orthographic projection of the second conductive component on the substrate base plate and the orthographic projection of the first driving electrode on the substrate base plate are arranged at intervals; and

the second common electrode layer is integrated with the first common electrode layer to form a common electrode layer.

3. The electronic device substrate of claim 1, wherein the second conductive component is in direct electrical connection with the second common electrode layer.

4. The electronic device substrate according to claim 1, wherein the second conductive member includes a plurality of first electrode patterns provided at intervals, the plurality of first electrode patterns being arranged in a ring shape as a whole.

5. The electronic device substrate of claim 4, wherein the first conductive component is a continuous first ring-shaped structure.

6. The electronic device substrate according to claim 4, wherein the first conductive member includes a plurality of second electrode patterns provided at intervals, the plurality of second electrode patterns being arranged in a ring shape as a whole.

7. The electronic device substrate of claim 6, wherein a shape of the second electrode pattern, a shape of the first electrode pattern, and a shape of the first driving electrode are the same.

8. The electronic device substrate of claim 7, wherein a size of the second electrode pattern, a size of the first electrode pattern, and a size of the first driving electrode are equal.

9. The electronic device substrate of claim 1, wherein the first conductive component is a continuous first ring-shaped structure, the second conductive component is a continuous second ring-shaped structure, and the third conductive component is a continuous third ring-shaped structure.

10. The electronic device substrate of claim 9, wherein the second conductive component is not directly electrically connected to the first conductive component.

11. The electronic device substrate of claim 9, wherein a loop width of the second conductive member is smaller than a loop width of the first conductive member in a direction from the array region toward the peripheral region.

12. The electronic device substrate according to claim 1, wherein a pitch between the first conductive member and the second conductive member is equal to a pitch between first driving electrodes of adjacent light emitting sub-units in a direction from the array region toward the peripheral region.

13. The electronic device substrate according to claim 9, wherein a spacing between the second conductive member and the third conductive member is equal to a spacing between the second conductive member and the first conductive member, and a loop width of the second conductive member is equal to a loop width of the third conductive member in a direction from the array region toward the peripheral region.

14. The electronic device substrate of any of claims 1-12, wherein the first driving electrode is an anode, the second driving electrode is a cathode, and the first conductive feature is a cathode ring;

the orthographic projection of the second common electrode layer on the plane where the first driving electrode is located is a continuous plane; and

the orthographic projection of the second common electrode layer on the plane where the first driving electrode is located completely covers the first conductive part.

15. The electronic device substrate of any of claims 1-12, wherein the peripheral region further comprises a fourth conductive member surrounding the first conductive member;

the fourth conductive part is arranged on one side of the first insulating layer far away from the substrate base plate; and

the fourth conductive part is overlapped with the second common electrode layer and is electrically connected with the second common electrode layer.

16. The electronic device substrate of any of claims 1-12, wherein the first insulating layer comprises a recess;

the recessed portion is located on one side of the first insulating layer close to the first conductive member and located between an orthographic projection of the first conductive member on the first insulating layer and an orthographic projection of the first driving electrode on the first insulating layer; and

an orthographic projection of the recessed portion on the base substrate, an orthographic projection of the first conductive member on the base substrate, an orthographic projection of the second conductive member on the base substrate, and an orthographic projection of the first drive electrode on the base substrate do not overlap.

17. The electronic device substrate of any of claims 1-12, further comprising an intermediate conductive layer,

wherein the first insulating layer comprises a first via and a second via;

the middle conducting layer is positioned on one side of the first insulating layer far away from the first driving electrode and comprises a first conducting structure and a second conducting structure;

the first drive electrode is electrically connected to the first conductive structure via the first via, the second drive electrode is electrically connected to the second conductive structure via the first conductive feature and the second via, and the second conductive feature and the intermediate conductive layer are not directly electrically connected.

18. The electronic device substrate of claim 17, wherein an orthographic projection of the second conductive feature on the substrate, an orthographic projection of the first conductive structure on the substrate, and an orthographic projection of the second conductive structure on the substrate are spaced apart.

19. The electronic device substrate of claim 18, further comprising a second insulating layer and a drive backplane disposed on a side of the intermediate conductive layer distal from the first drive electrode;

the driving back plate comprises the substrate base plate;

the second insulating layer is arranged between the middle conducting layer and the driving back plate;

the second insulating layer comprises a third via and a fourth via; and

the first driving electrode is electrically connected with the first area of the driving backboard through the first via hole, the first conductive structure and the third via hole, the second driving electrode is electrically connected with the second area of the driving backboard through the first conductive part, the second via hole, the second conductive structure and the fourth via hole, and the second conductive part and the driving backboard are not directly electrically connected.

20. The electronic device substrate of claim 19, wherein the second conductive component does not directly receive a signal provided by the driving backplane.

21. The electronic device substrate of claim 1, wherein the second conductive member is floating.

22. An electronic device comprising the electronic device substrate of any of claims 1-21.

23. A method for manufacturing an electronic device substrate comprises the following steps:

providing a substrate base plate;

forming a first insulating layer on the substrate base plate; and

forming a plurality of light emitting sub-units, a first conductive member, a second conductive member and a third conductive member on a side of the first insulating layer away from the substrate base plate,

wherein the plurality of light emitting sub-units are disposed in an array region of the electronic device substrate, the first conductive member is disposed in a peripheral region of the electronic device substrate surrounding the array region, and the second conductive member is disposed between the first conductive member and the array region;

each of the light emitting sub-units includes a first driving electrode and a second driving electrode stacked on each other, the first driving electrode and the second driving electrode being configured to apply a light emitting driving voltage, the second driving electrodes of the plurality of light emitting sub-units being integrated to form a first common electrode layer;

the third conductive part is arranged around the array region and is positioned in the same conductive structure layer with the first driving electrode, and the second conductive part is arranged around the third conductive part;

24. The method of making an electronic device substrate of claim 23, wherein forming the plurality of light emitting sub-units, the first conductive component, the second conductive component, and the third conductive component on a side of the first insulating layer away from the substrate comprises:

forming a first conductive layer;

patterning the first conductive layer to form the first drive electrode, the first conductive component, the second conductive component, and the third conductive component of the plurality of light emitting sub-units; and

forming a common electrode layer on the first driving electrode, the first conductive member, the second conductive member, and the third conductive member, wherein the common electrode layer includes the first common electrode layer and the second common electrode layer integrated.