CN112768417A - 具有加热功能的转接板以及电子装置 - Google Patents
具有加热功能的转接板以及电子装置 Download PDFInfo
- Publication number
- CN112768417A CN112768417A CN201911379853.XA CN201911379853A CN112768417A CN 112768417 A CN112768417 A CN 112768417A CN 201911379853 A CN201911379853 A CN 201911379853A CN 112768417 A CN112768417 A CN 112768417A
- Authority
- CN
- China
- Prior art keywords
- conductive
- micro
- heaters
- disposed
- conductive contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010438 heat treatment Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 238000003466 welding Methods 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0212—Printed circuits or mounted components having integral heating means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/345—Arrangements for heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32112—Disposition the layer connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81234—Applying energy for connecting using means for applying energy being within the device, e.g. integrated heater
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81238—Applying energy for connecting using electric resistance welding, i.e. ohmic heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83234—Applying energy for connecting using means for applying energy being within the device, e.g. integrated heater
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83238—Applying energy for connecting using electric resistance welding, i.e. ohmic heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9211—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1115—Resistance heating, e.g. by current through the PCB conductors or through a metallic mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
本发明公开一种具有加热功能的转接板以及电子装置。电子装置包括一电路基板、设置在电路基板上的一转接板以及被转接板所承载的至少一电子芯片。转接板包括一绝缘本体、多个顶端导电接点、多个底端导电接点、多个导电连接结构以及多个微加热器。绝缘本体设置在电路基板上。多个顶端导电接点与多个底端导电接点设置在绝缘本体上。多个导电连接结构设置在绝缘本体上,且多个导电连接结构分别电性连接于多个顶端导电接点且分别电性连接于多个底端导电接点。多个微加热器设置在绝缘本体上或者内部,且分别邻近多个顶端导电接点与多个底端导电接点。借此,每一微加热器能针对相对应的顶端导电接点或者相对应的底端导电接点进行加热。
Description
技术领域
本发明涉及一种转接板以及电子装置,特别是涉及一种具有加热功能的转接板以及一种使用所述转接板的电子装置。
背景技术
目前,IC芯片可能会通过一转接板而电性连接于一电路板,然而现有的转接板仍具有改善空间。
发明内容
本发明所要解决的技术问题在于,针对现有技术的不足提供一种具有加热功能的转接板以及一种使用所述转接板的电子装置。
为了解决上述的技术问题,本发明所采用的其中一技术方案是,提供一种具有加热功能的转接板,其包括:一绝缘本体、多个顶端导电接点、多个底端导电接点、多个导电连接结构以及多个微加热器。多个所述顶端导电接点设置在所述绝缘本体的一顶端上。多个所述底端导电接点设置在所述绝缘本体的一底端上。多个所述导电连接结构设置在所述绝缘本体的内部,多个所述导电连接结构分别电性连接于多个所述顶端导电接点且分别电性连接于多个所述底端导电接点,以使得每一所述导电连接结构电性连接于相对应的所述顶端导电接点与相对应的所述底端导电接点之间。多个所述微加热器设置在所述绝缘本体上或者内部,且分别邻近多个所述顶端导电接点与多个所述底端导电接点。其中,当多个顶端焊接物分别设置在多个所述顶端导电接点,且多个底端焊接物分别设置在多个所述底端导电接点时,多个所述微加热器对多个所述顶端焊接物与多个所述底端焊接物进行加热。
进一步地,当所述绝缘本体被设置在一电路基板上且承载至少一电子芯片时,一第一非导电薄膜被设置在所述绝缘本体与所述电路基板之间,且一第二非导电薄膜被设置在所述至少一电子芯片与所述绝缘本体之间;其中,所述至少一电子芯片通过所述转接板以电性连接于所述电路基板,且多个所述微加热器对所述第一非导电薄膜与所述第二非导电薄膜进行加热;其中,多个所述底端导电接点分别通过多个所述底端焊接物的电性导通,以分别电性连接于所述电路基板的多个基板导电接点,且多个所述顶端导电接点分别通过多个所述顶端焊接物的电性导通,以分别电性连接于所述至少一电子芯片的多个芯片导电接点;其中,所述导电连接结构为一笔直的或者非笔直的导电连接体,且所述导电连接结构的两相反端分别电性连接于所述顶端导电接点与所述底端导电接点;其中,多个所述微加热器区分成多个顶端微加热器以及多个底端微加热器,所述顶端微加热器比所述底端微加热器更靠近所述至少一电子芯片,所述底端微加热器比所述顶端微加热器更靠近所述电路基板。
进一步地,所述转接板进一步包括:多个第一顶端电源输入点,其设置在所述绝缘本体的所述顶端,每一所述第一顶端电源输入点电性连接于多个所述顶端微加热器之中的至少一个;多个底端电源输入点,其设置在所述绝缘本体的所述底端,每一所述底端电源输入点电性连接于多个所述底端微加热器之中的至少一个;以及多个第二顶端电源输入点,其设置在所述绝缘本体的所述顶端,且分别对应于多个所述底端电源输入点,每一所述第二顶端电源输入点通过一导电通道,以电性连接于相对应的所述底端电源输入点。
为了解决上述的技术问题,本发明所采用的另外一技术方案是,提供一种具有加热功能的转接板,其包括:一绝缘本体、多个顶端导电接点、多个底端导电接点、多个导电连接结构以及多个微加热器。多个所述顶端导电接点设置在所述绝缘本体上。多个所述底端导电接点设置在所述绝缘本体上。多个所述导电连接结构设置在所述绝缘本体上,且多个所述导电连接结构分别电性连接于多个所述顶端导电接点且分别电性连接于多个所述底端导电接点。多个所述微加热器设置在所述绝缘本体上或者内部,且分别邻近多个所述顶端导电接点与多个所述底端导电接点。其中,每一所述微加热器对相对应的所述顶端导电接点或者相对应的所述底端导电接点进行加热。
进一步地,当所述绝缘本体被设置在一电路基板上且承载至少一电子芯片时,一第一非导电薄膜被设置在所述绝缘本体与所述电路基板之间,且一第二非导电薄膜被设置在所述至少一电子芯片与所述绝缘本体之间;其中,所述至少一电子芯片通过所述转接板以电性连接于所述电路基板,且多个所述微加热器对所述第一非导电薄膜与所述第二非导电薄膜进行加热;其中,多个所述底端导电接点分别通过多个底端焊接物的电性导通,以分别电性连接于所述电路基板的多个基板导电接点,且多个所述顶端导电接点分别通过多个顶端焊接物的电性导通,以分别电性连接于所述至少一电子芯片的多个芯片导电接点;其中,所述导电连接结构为一笔直的或者非笔直的导电连接体,且所述导电连接结构的两相反端分别电性连接于所述顶端导电接点与所述底端导电接点;其中,多个所述微加热器区分成多个顶端微加热器以及多个底端微加热器,所述顶端微加热器比所述底端微加热器更靠近所述至少一电子芯片,所述底端微加热器比所述顶端微加热器更靠近所述电路基板。
进一步地,所述转接板进一步包括:多个第一顶端电源输入点,其设置在所述绝缘本体的所述顶端,每一所述第一顶端电源输入点电性连接于多个所述顶端微加热器之中的至少一个;多个底端电源输入点,其设置在所述绝缘本体的所述底端,每一所述底端电源输入点电性连接于多个所述底端微加热器之中的至少一个;以及多个第二顶端电源输入点,其设置在所述绝缘本体的所述顶端,且分别对应于多个所述底端电源输入点,每一所述第二顶端电源输入点通过一导电通道,以电性连接于相对应的所述底端电源输入点。
为了解决上述的技术问题,本发明所采用的另外一技术方案是,提供一种电子装置,其包括:一电路基板、设置在所述电路基板上的一转接板以及被所述转接板所承载的至少一电子芯片,其特征在于,所述转接板包括:一绝缘本体、多个顶端导电接点、多个底端导电接点、多个导电连接结构以及多个微加热器。所述绝缘本体设置在所述电路基板上。多个所述顶端导电接点设置在所述绝缘本体上。多个所述底端导电接点设置在所述绝缘本体上。多个所述导电连接结构设置在所述绝缘本体上,且多个所述导电连接结构分别电性连接于多个所述顶端导电接点且分别电性连接于多个所述底端导电接点。多个所述微加热器设置在所述绝缘本体上或者内部,且分别邻近多个所述顶端导电接点与多个所述底端导电接点。其中,每一所述微加热器对相对应的所述顶端导电接点或者相对应的所述底端导电接点进行加热。
进一步地,所述电子装置进一步包括:一第一非导电薄膜以及一第二非导电薄膜,所述第一非导电薄膜被设置在所述绝缘本体与所述电路基板之间,且所述第二非导电薄膜被设置在所述至少一电子芯片与所述绝缘本体之间;其中,所述至少一电子芯片通过所述转接板以电性连接于所述电路基板,且多个所述微加热器对所述第一非导电薄膜与所述第二非导电薄膜进行加热;其中,多个所述底端导电接点分别通过多个底端焊接物的电性导通,以分别电性连接于所述电路基板的多个基板导电接点,且多个所述顶端导电接点分别通过多个顶端焊接物的电性导通,以分别电性连接于所述至少一电子芯片的多个芯片导电接点;其中,所述导电连接结构为一笔直的或者非笔直的导电连接体,且所述导电连接结构的两相反端分别电性连接于所述顶端导电接点与所述底端导电接点;其中,多个所述微加热器区分成多个顶端微加热器以及多个底端微加热器,所述顶端微加热器比所述底端微加热器更靠近所述至少一电子芯片,所述底端微加热器比所述顶端微加热器更靠近所述电路基板。
进一步地,所述转接板进一步包括:多个第一顶端电源输入点,其设置在所述绝缘本体的所述顶端,每一所述第一顶端电源输入点电性连接于多个所述顶端微加热器之中的至少一个;多个底端电源输入点,其设置在所述绝缘本体的所述底端,每一所述底端电源输入点电性连接于多个所述底端微加热器之中的至少一个;以及多个第二顶端电源输入点,其设置在所述绝缘本体的所述顶端,且分别对应于多个所述底端电源输入点,每一所述第二顶端电源输入点通过一导电通道,以电性连接于相对应的所述底端电源输入点。
进一步地,多个所述顶端焊接物分别设置在多个所述顶端导电接点,多个所述底端焊接物分别设置在多个所述底端导电接点,多个所述微加热器对多个所述顶端焊接物与多个所述底端焊接物进行加热。
本发明的其中一有益效果在于,本发明所提供的转接板与电子装置,其能通过“多个所述微加热器设置在所述绝缘本体上或者内部”以及“多个所述微加热器分别邻近多个所述顶端导电接点与多个所述底端导电接点”的技术方案,以使得每一所述微加热器能针对相对应的所述顶端导电接点或者相对应的所述底端导电接点进行加热。借此,当多个顶端焊接物分别设置在多个所述顶端导电接点,且多个底端焊接物分别设置在多个所述底端导电接点时,多个所述微加热器能对多个所述顶端焊接物与多个所述底端焊接物进行加热。
为使能进一步了解本发明的特征及技术内容,请参阅以下有关本发明的详细说明与附图,然而所提供的附图仅用于提供参考与说明,并非用来对本发明加以限制。
附图说明
图1为本发明第一实施例所提供具有加热功能的转接板的示意图。
图2为本发明第一实施例所提供的第一顶端电源输入点与顶端微加热器的相互关系的功能方块图。
图3为本发明第一实施例所提供的底端电源输入点与底端微加热器的相互关系的功能方块图。
图4为本发明第二实施例所提供具有加热功能的转接板的示意图。
图5为本发明第三实施例所提供的电子装置的分解示意图。
图6为本发明第三实施例所提供的电子装置的组合示意图。
图7为本发明第三实施例所提供的电子装置的俯视示意图。
具体实施方式
以下是通过特定的具体实施例来说明本发明所公开有关“具有加热功能的转接板以及电子装置”的实施方式,本领域技术人员可由本说明书所公开的内容了解本发明的优点与效果。本发明可通过其他不同的具体实施例加以施行或应用,本说明书中的各项细节也可基于不同观点与应用,在不背离本发明的构思下进行各种修改与变更。另外,本发明的附图仅为简单示意说明,并非依实际尺寸的描绘,事先声明。以下的实施方式将进一步详细说明本发明的相关技术内容,但所公开的内容并非用以限制本发明的保护范围。
应当可以理解的是,虽然本文中可能会使用到“第一”、“第二”等术语来描述各种组件,但这些组件不应受这些术语的限制。这些术语主要是用以区分一组件与另一组件。另外,本文中所使用的术语“或”,应视实际情况可能包括相关联的列出项目中的任一个或者多个的组合。
第一实施例
参阅图1至图3所示,本发明第一实施例提供一种具有加热功能的转接板B,其包括:一绝缘本体10、多个顶端导电接点11、多个底端导电接点12、多个导电连接结构13以及多个微加热器14。
进一步来说,如图1所示,多个顶端导电接点11设置在绝缘本体10上,并且多个底端导电接点12也设置在绝缘本体10上。另外,多个导电连接结构13设置在绝缘本体10上,并且多个导电连接结构13分别电性连接于多个顶端导电接点11且分别电性连接于多个底端导电接点12。此外,多个微加热器14设置在绝缘本体10上,并且多个微加热器14分别邻近多个顶端导电接点11与多个底端导电接点12。借此,每一微加热器14能针对相对应的顶端导电接点11或者相对应的底端导电接点12进行加热。
举例来说,如图1所示,多个顶端导电接点11能设置在绝缘本体10的一顶端上,并且多个底端导电接点12能设置在绝缘本体10的一底端上。另外,多个导电连接结构13能设置在绝缘本体10的内部,导电连接结构13可为一笔直的或者非笔直的导电连接体,并且导电连接结构13的两相反端分别电性连接于顶端导电接点11与底端导电接点12。也就是说,当多个导电连接结构13分别电性连接于多个顶端导电接点11且分别电性连接于多个底端导电接点12时,每一导电连接结构13就会电性连接于相对应的顶端导电接点11与相对应的底端导电接点12之间。然而,本发明不以上述所举的例子为限。
举例来说,每一个微加热器14会对应到一个顶端导电接点11或者一个底端导电接点12。此外,微加热器14可为一围绕状,以围绕顶端导电接点11或者底端导电接点12;微加热器14亦可设置在顶端导电接点11的任意三侧或者设置在底端导电接点12的任意三侧;微加热器14亦可设置在顶端导电接点11的任意两侧或者设置在底端导电接点12的任意两侧(如图1所示);或者,微加热器14亦可设置在顶端导电接点11的任意一侧或者设置在底端导电接点12的任意一侧。另外,多个微加热器14可以采用并联、串联或者并联加串联的方式彼此电性连接。然而,本发明不以上述所举的例子为限。
再者,配合图1至图3所示,本发明第一实施例所提供具有加热功能的转接板B进一步包括:多个第一顶端电源输入点15、多个底端电源输入点16以及多个第二顶端电源输入点17。进一步来说,多个第一顶端电源输入点15可设置在绝缘本体10的顶端,并且每一第一顶端电源输入点15能电性连接于多个顶端微加热器14T之中的至少一个(如图2所示)。另外,多个底端电源输入点16可设置在绝缘本体10的底端,并且每一底端电源输入点16能电性连接于多个底端微加热器14B之中的至少一个(如图3所示)。此外,多个第二顶端电源输入点17可设置在绝缘本体10的顶端,多个第二顶端电源输入点17可分别对应于多个底端电源输入点16,并且每一第二顶端电源输入点17可通过一导电通道18,以电性连接于相对应的底端电源输入点16。也就是说,多个第一顶端电源输入点15与多个第二顶端电源输入点17可以同时被设置在绝缘本体10的顶端上,以便于使用者直接在绝缘本体10的顶端上对多个第一顶端电源输入点15与多个第二顶端电源输入点17输入电源,借此以驱动每一微加热器14对相对应的顶端导电接点11或者相对应的底端导电接点12进行加热。举例来说,每一第一顶端电源输入点15可以包括一正极接点与一负极接点,并且每一第二顶端电源输入点17可以包括一正极接点与一负极接点。然而,本发明不以上述所举的例子为限。
第二实施例
参阅图4所示,本发明第二实施例提供一种具有加热功能的转接板B,其包括:一绝缘本体10、多个顶端导电接点11、多个底端导电接点12、多个导电连接结构13以及多个微加热器14。由图4与图1的比较可知,本发明第二实施例与第一实施例最大的差别在于:在第二实施例中,多个微加热器14能被设置在绝缘本体10的内部。换言之,多个微加热器14可以预先制作成具有多个微加热器14的一微加热器薄膜,然后再将具有多个微加热器14的微加热器薄膜设置在绝缘本体10的顶端或者底端(如图1所示的第一实施例),或者在制作绝缘本体10时,直接将多个微加热器14内嵌在绝缘本体10的内部(如图4所示的第二实施例)。然而,本发明不以第一实施例或者第二实施例所举的例子为限,只要是能够将多个微加热器14设置在转接板B的任意位置,都是本发明要保护的技术特征。
第三实施例
参阅图5至图7所示,本发明第三实施例提供一种电子装置E,其包括:一电路基板P、设置在电路基板P上的一转接板B以及被转接板B所承载的至少一电子芯片C,并且转接板B包括一绝缘本体10、多个顶端导电接点11、多个底端导电接点12、多个导电连接结构13以及多个微加热器14。
进一步来说,配合图5与图6所示,绝缘本体10设置在电路基板P上,多个顶端导电接点11设置在绝缘本体10上,并且多个底端导电接点12设置在绝缘本体10上。另外,多个导电连接结构13设置在绝缘本体10上,并且多个导电连接结构13分别电性连接于多个顶端导电接点11且分别电性连接于多个底端导电接点12。此外,多个微加热器14设置在绝缘本体10上或者内部,多个微加热器14分别邻近多个顶端导电接点11与多个底端导电接点12,并且每一微加热器14能针对相对应的顶端导电接点11或者相对应的底端导电接点12进行加热。借此,当多个顶端焊接物S1分别设置在多个顶端导电接点11,并且多个底端焊接物S2分别设置在多个底端导电接点12时,多个微加热器14能对多个顶端焊接物S1与多个底端焊接物S2进行加热,借此以使得至少一电子芯片C能通过多个顶端焊接物S1的加热而稳固地固接在转接板B上,并且使得转接板B能通过多个底端焊接物S2的加热而稳固地固接在电路基板P上。举例来说,顶端焊接物S1与底端焊接物S2可为锡球、锡膏或者任何能用于焊接的导电材料,然而本发明不以上述所举的例子为限。
进一步来说,配合图5与图6所示,当绝缘本体10被设置在电路基板P上且承载至少一电子芯片C时,至少一电子芯片C能通过转接板B以电性连接于电路基板P。借此,多个底端导电接点12能分别通过多个底端焊接物S2的电性导通,以分别电性连接于电路基板P的多个基板导电接点P10,并且多个顶端导电接点11能分别通过多个顶端焊接物S1的电性导通,以分别电性连接于至少一电子芯片C的多个芯片导电接点C10。
进一步来说,配合图5与图6所示,本发明第三实施例的电子装置E还能进一步包括一第一非导电薄膜F1(或者第一非导电胶,例如底部填充剂)以及一第二非导电薄膜F2(或者第二非导电胶,例如底部填充剂)。当第一非导电薄膜F1被设置在绝缘本体10与电路基板P之间,并且第二非导电薄膜F2被设置在至少一电子芯片C与绝缘本体10之间时,多个微加热器14就能对第一非导电薄膜F1与第二非导电薄膜F2进行加热。借此,第一非导电薄膜F1会因为受热而能稳固地被设置在绝缘本体10与电路基板P之间,以将绝缘本体10与电路基板P之间的空隙填满而避免产生多余的空隙,并且第二非导电薄膜F2会因为受热而能稳固地被设置在至少一电子芯片C与绝缘本体10之间,以将至少一电子芯片C与绝缘本体10之间的空隙填满而避免产生多余的空隙。举例来说,当多个微加热器14对第一非导电薄膜F1与第二非导电薄膜F2进行加热时,第一非导电薄膜F1与第二非导电薄膜F2会因为受热而改变形状,借此以将绝缘本体10与电路基板P之间的空隙填满而避免产生多余的空隙,并且将至少一电子芯片C与绝缘本体10之间的空隙填满而避免产生多余的空隙。
值得注意的是,如图6所示,当多个微加热器14区分成多个顶端微加热器14T以及多个底端微加热器14B时,顶端微加热器14T会比底端微加热器14B更靠近至少一电子芯片C,而底端微加热器14B会比顶端微加热器14T更靠近电路基板P。配合图6与图7所示,多个第二顶端电源输入点17可设置在绝缘本体10的顶端,多个第二顶端电源输入点17可分别对应于多个底端电源输入点16,并且每一第二顶端电源输入点17可通过一导电通道18,以电性连接于相对应的底端电源输入点16。也就是说,多个第一顶端电源输入点15与多个第二顶端电源输入点17可以同时被设置在绝缘本体10的顶端上,以便于使用者直接在绝缘本体10的顶端上对多个第一顶端电源输入点15与多个第二顶端电源输入点17输入电源,借此以驱动每一微加热器14对相对应的顶端导电接点11或者相对应的底端导电接点12进行加热。
实施例的有益效果
本发明的其中一有益效果在于,本发明所提供的转接板B与电子装置E,其能通过“多个微加热器14设置在绝缘本体10上或者内部”以及“多个微加热器14分别邻近多个顶端导电接点11与多个底端导电接点12”的技术方案,以使得每一微加热器14能针对相对应的顶端导电接点11或者相对应的底端导电接点12进行加热。借此,当多个顶端焊接物S1分别设置在多个顶端导电接点11,且多个底端焊接物S2分别设置在多个底端导电接点12时,多个微加热器14能对多个顶端焊接物S1与多个底端焊接物S2进行加热。
以上所公开的内容仅为本发明的优选可行实施例,并非因此局限本发明的权利要求书的保护范围,所以凡是运用本发明说明书及附图内容所做的等效技术变化,均包含于本发明的权利要求书的保护范围内。
Claims (10)
1.一种具有加热功能的转接板,其特征在于,所述转接板包括:
一绝缘本体;
多个顶端导电接点,其设置在所述绝缘本体的一顶端上;
多个底端导电接点,其设置在所述绝缘本体的一底端上;
多个导电连接结构,其设置在所述绝缘本体的内部,多个所述导电连接结构分别电性连接于多个所述顶端导电接点且分别电性连接于多个所述底端导电接点,以使得每一所述导电连接结构电性连接于相对应的所述顶端导电接点与相对应的所述底端导电接点之间;以及
多个微加热器,其设置在所述绝缘本体上或者内部,且分别邻近多个所述顶端导电接点与多个所述底端导电接点;
其中,当多个顶端焊接物分别设置在多个所述顶端导电接点,且多个底端焊接物分别设置在多个所述底端导电接点时,多个所述微加热器对多个所述顶端焊接物与多个所述底端焊接物进行加热。
2.根据权利要求1所述的转接板,其特征在于,当所述绝缘本体被设置在一电路基板上且承载至少一电子芯片时,一第一非导电薄膜被设置在所述绝缘本体与所述电路基板之间,且一第二非导电薄膜被设置在所述至少一电子芯片与所述绝缘本体之间;其中,所述至少一电子芯片通过所述转接板以电性连接于所述电路基板,且多个所述微加热器对所述第一非导电薄膜与所述第二非导电薄膜进行加热;其中,多个所述底端导电接点分别通过多个所述底端焊接物的电性导通,以分别电性连接于所述电路基板的多个基板导电接点,且多个所述顶端导电接点分别通过多个所述顶端焊接物的电性导通,以分别电性连接于所述至少一电子芯片的多个芯片导电接点;其中,所述导电连接结构为一笔直的或者非笔直的导电连接体,且所述导电连接结构的两相反端分别电性连接于所述顶端导电接点与所述底端导电接点;其中,多个所述微加热器区分成多个顶端微加热器以及多个底端微加热器,所述顶端微加热器比所述底端微加热器更靠近所述至少一电子芯片,所述底端微加热器比所述顶端微加热器更靠近所述电路基板。
3.根据权利要求2所述的转接板,其特征在于,所述转接板进一步包括:
多个第一顶端电源输入点,其设置在所述绝缘本体的所述顶端,每一所述第一顶端电源输入点电性连接于多个所述顶端微加热器之中的至少一个;
多个底端电源输入点,其设置在所述绝缘本体的所述底端,每一所述底端电源输入点电性连接于多个所述底端微加热器之中的至少一个;以及
多个第二顶端电源输入点,其设置在所述绝缘本体的所述顶端,且分别对应于多个所述底端电源输入点,每一所述第二顶端电源输入点通过一导电通道,以电性连接于相对应的所述底端电源输入点。
4.一种具有加热功能的转接板,其特征在于,所述转接板包括:
一绝缘本体;
多个顶端导电接点,其设置在所述绝缘本体上;
多个底端导电接点,其设置在所述绝缘本体上;
多个导电连接结构,其设置在所述绝缘本体上,多个所述导电连接结构分别电性连接于多个所述顶端导电接点且分别电性连接于多个所述底端导电接点;以及
多个微加热器,其设置在所述绝缘本体上或者内部,且分别邻近多个所述顶端导电接点与多个所述底端导电接点;
其中,每一所述微加热器对相对应的所述顶端导电接点或者相对应的所述底端导电接点进行加热。
5.根据权利要求4所述的转接板,其特征在于,当所述绝缘本体被设置在一电路基板上且承载至少一电子芯片时,一第一非导电薄膜被设置在所述绝缘本体与所述电路基板之间,且一第二非导电薄膜被设置在所述至少一电子芯片与所述绝缘本体之间;其中,所述至少一电子芯片通过所述转接板以电性连接于所述电路基板,且多个所述微加热器对所述第一非导电薄膜与所述第二非导电薄膜进行加热;其中,多个所述底端导电接点分别通过多个底端焊接物的电性导通,以分别电性连接于所述电路基板的多个基板导电接点,且多个所述顶端导电接点分别通过多个顶端焊接物的电性导通,以分别电性连接于所述至少一电子芯片的多个芯片导电接点;其中,所述导电连接结构为一笔直的或者非笔直的导电连接体,且所述导电连接结构的两相反端分别电性连接于所述顶端导电接点与所述底端导电接点;其中,多个所述微加热器区分成多个顶端微加热器以及多个底端微加热器,所述顶端微加热器比所述底端微加热器更靠近所述至少一电子芯片,所述底端微加热器比所述顶端微加热器更靠近所述电路基板。
6.根据权利要求5所述的转接板,其特征在于,所述转接板进一步包括:
多个第一顶端电源输入点,其设置在所述绝缘本体的所述顶端,每一所述第一顶端电源输入点电性连接于多个所述顶端微加热器之中的至少一个;
多个底端电源输入点,其设置在所述绝缘本体的所述底端,每一所述底端电源输入点电性连接于多个所述底端微加热器之中的至少一个;以及
多个第二顶端电源输入点,其设置在所述绝缘本体的所述顶端,且分别对应于多个所述底端电源输入点,每一所述第二顶端电源输入点通过一导电通道,以电性连接于相对应的所述底端电源输入点。
7.一种电子装置,其包括:一电路基板、设置在所述电路基板上的一转接板以及被所述转接板所承载的至少一电子芯片,其特征在于,所述转接板包括:
一绝缘本体,其设置在所述电路基板上;
多个顶端导电接点,其设置在所述绝缘本体上;
多个底端导电接点,其设置在所述绝缘本体上;
多个导电连接结构,其设置在所述绝缘本体上,多个所述导电连接结构分别电性连接于多个所述顶端导电接点且分别电性连接于多个所述底端导电接点;以及
多个微加热器,其设置在所述绝缘本体上或者内部,且分别邻近多个所述顶端导电接点与多个所述底端导电接点;
其中,每一所述微加热器对相对应的所述顶端导电接点或者相对应的所述底端导电接点进行加热。
8.根据权利要求7所述的电子装置,其特征在于,所述电子装置进一步包括:一第一非导电薄膜以及一第二非导电薄膜,所述第一非导电薄膜被设置在所述绝缘本体与所述电路基板之间,且所述第二非导电薄膜被设置在所述至少一电子芯片与所述绝缘本体之间;其中,所述至少一电子芯片通过所述转接板以电性连接于所述电路基板,且多个所述微加热器对所述第一非导电薄膜与所述第二非导电薄膜进行加热;其中,多个所述底端导电接点分别通过多个底端焊接物的电性导通,以分别电性连接于所述电路基板的多个基板导电接点,且多个所述顶端导电接点分别通过多个顶端焊接物的电性导通,以分别电性连接于所述至少一电子芯片的多个芯片导电接点;其中,所述导电连接结构为一笔直的或者非笔直的导电连接体,且所述导电连接结构的两相反端分别电性连接于所述顶端导电接点与所述底端导电接点;其中,多个所述微加热器区分成多个顶端微加热器以及多个底端微加热器,所述顶端微加热器比所述底端微加热器更靠近所述至少一电子芯片,所述底端微加热器比所述顶端微加热器更靠近所述电路基板。
9.根据权利要求8所述的电子装置,其特征在于,所述转接板进一步包括:
多个第一顶端电源输入点,其设置在所述绝缘本体的所述顶端,每一所述第一顶端电源输入点电性连接于多个所述顶端微加热器之中的至少一个;
多个底端电源输入点,其设置在所述绝缘本体的所述底端,每一所述底端电源输入点电性连接于多个所述底端微加热器之中的至少一个;以及
多个第二顶端电源输入点,其设置在所述绝缘本体的所述顶端,且分别对应于多个所述底端电源输入点,每一所述第二顶端电源输入点通过一导电通道,以电性连接于相对应的所述底端电源输入点。
10.根据权利要求8所述的电子装置,其特征在于,多个所述顶端焊接物分别设置在多个所述顶端导电接点,多个所述底端焊接物分别设置在多个所述底端导电接点,多个所述微加热器对多个所述顶端焊接物与多个所述底端焊接物进行加热。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108140260 | 2019-11-06 | ||
TW108140260A TWI710298B (zh) | 2019-11-06 | 2019-11-06 | 具有加熱功能的轉接板以及電子裝置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112768417A true CN112768417A (zh) | 2021-05-07 |
Family
ID=74202428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911379853.XA Pending CN112768417A (zh) | 2019-11-06 | 2019-12-27 | 具有加热功能的转接板以及电子装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20210136909A1 (zh) |
CN (1) | CN112768417A (zh) |
TW (1) | TWI710298B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI810571B (zh) | 2021-05-21 | 2023-08-01 | 歆熾電氣技術股份有限公司 | 適用於加熱安裝的基板、適用於加熱安裝的電路基板及適用於加熱安裝的治具 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7474540B1 (en) * | 2008-01-10 | 2009-01-06 | International Business Machines Corporation | Silicon carrier including an integrated heater for die rework and wafer probe |
US20130134606A1 (en) * | 2011-11-25 | 2013-05-30 | Samsung Electronics Co., Ltd. | Semiconductor packages |
US20150016083A1 (en) * | 2013-07-05 | 2015-01-15 | Stephen P. Nootens | Thermocompression bonding apparatus and method |
CN106104795A (zh) * | 2014-03-29 | 2016-11-09 | 英特尔公司 | 使用局部热源的集成电路芯片附接 |
US20170178994A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | Integrated circuit package support structures |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007141956A (ja) * | 2005-11-15 | 2007-06-07 | Three M Innovative Properties Co | プリント回路基板の接続方法 |
DE102013113045A1 (de) * | 2013-11-26 | 2015-05-28 | Aixtron Se | Heizvorrichtung |
KR102329513B1 (ko) * | 2016-05-10 | 2021-11-23 | 램 리써치 코포레이션 | 적층된 히터와 히터 전압 입력부들 사이의 연결부들 |
EP3557144A1 (de) * | 2018-04-20 | 2019-10-23 | Future Carbon GmbH | Mehrschichtiges verbundsystem aufweisend eine beheizbare schicht und kit zum herstellen des mehrschichtigen verbundsystems |
-
2019
- 2019-11-06 TW TW108140260A patent/TWI710298B/zh active
- 2019-12-27 CN CN201911379853.XA patent/CN112768417A/zh active Pending
-
2020
- 2020-06-03 US US16/891,290 patent/US20210136909A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7474540B1 (en) * | 2008-01-10 | 2009-01-06 | International Business Machines Corporation | Silicon carrier including an integrated heater for die rework and wafer probe |
US20130134606A1 (en) * | 2011-11-25 | 2013-05-30 | Samsung Electronics Co., Ltd. | Semiconductor packages |
US20150016083A1 (en) * | 2013-07-05 | 2015-01-15 | Stephen P. Nootens | Thermocompression bonding apparatus and method |
CN106104795A (zh) * | 2014-03-29 | 2016-11-09 | 英特尔公司 | 使用局部热源的集成电路芯片附接 |
US20170178994A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | Integrated circuit package support structures |
WO2017112136A1 (en) * | 2015-12-21 | 2017-06-29 | Intel Corporation | Integrated circuit package support structures |
Also Published As
Publication number | Publication date |
---|---|
TWI710298B (zh) | 2020-11-11 |
TW202119886A (zh) | 2021-05-16 |
US20210136909A1 (en) | 2021-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR920004280Y1 (ko) | 전자부품의 접속구조 | |
CN107251669B (zh) | 基板单元 | |
CN108449861B (zh) | 一种柔性电路板及移动终端 | |
CN104426244B (zh) | 无线充电装置 | |
US10502638B2 (en) | Temperature detecting device and electronic device | |
US3366914A (en) | Solderless connector for printed board circuits | |
KR20130025205A (ko) | 휴대용 데이터 저장 장치 | |
CN102164453A (zh) | 电路模块 | |
CN112768417A (zh) | 具有加热功能的转接板以及电子装置 | |
US20160050745A1 (en) | Electronic assembly | |
CN106252332A (zh) | 热敏电阻搭载装置及热敏电阻部件 | |
JP2005535079A (ja) | Bga接続を有する印刷回路基板組立 | |
US7794287B1 (en) | Electrical connector configured by wafer having coupling foil and method for making the same | |
CN112788845A (zh) | 具有加热功能的非导电薄膜以及电子装置 | |
US8708741B2 (en) | Electrical connector with thermal conductive substrate | |
US9356368B2 (en) | Low profile electrical connector | |
JP5890217B2 (ja) | 電気コネクタ | |
CN209517614U (zh) | 一种电路板 | |
US10312003B2 (en) | Circuit board with thermal paths for thermistor | |
CN105280603A (zh) | 电子封装组件 | |
CN105163487A (zh) | 一种柔性多层印刷电路板 | |
CN105070504B (zh) | 一种电阻电容共体器件 | |
JP6060053B2 (ja) | パワー半導体装置 | |
CN218242171U (zh) | 电池模块 | |
CN100466895C (zh) | 散热结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20210913 Address after: 5 / F, 2 / F, No. 611, Section 1, Wanshou Road, Guishan District, Taoyuan City, Taiwan, China Applicant after: Xinchi Electric Technology Co.,Ltd. Address before: TaiWan, China Applicant before: Taiwan Aisidi Technology Co.,Ltd. |
|
TA01 | Transfer of patent application right |