CN112764977A - Memory controller and test data generation method - Google Patents
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Abstract
The invention provides a memory controller and a test data generation method. The method comprises the following steps: (1) determining a conversion threshold according to the predetermined zero-one ratio corresponding to the test data and the predetermined integer range, wherein the conversion threshold is one of a plurality of consecutive integers in the predetermined integer range; (2) generating a target random integer within the predetermined range of integers; (3) judging whether the target random integer is larger than the conversion threshold value; wherein in response to determining that the target random integer is greater than or not greater than the conversion threshold, converting the target random integer to 1 or 0 and setting an i-th bit of the test data to the target random integer; and (4) determining whether i is equal to N, wherein in response to determining that i is not equal to N, adding 1 to i, and re-executing step (2); wherein in response to determining that i is equal to N, the test data is responded to according to the set N bits of the test data.
Description
Technical Field
The present invention relates to a memory controller and a test data generation method used by the memory controller.
Background
In the mass production process of part of large-capacity flash memory storage devices, in order to confirm the quality of the flash memory, part or all of data read-write tests are carried out on the flash memory to determine available blocks in the flash memory. In particular, some blocks of the flash memory are sensitive to specific data, so different data are required to test the blocks, thereby eliminating the blocks with higher sensitivity and improving the stability of reading and writing of the flash memory.
Disclosure of Invention
The present invention is directed to a memory controller for controlling a memory device configured with a rewritable non-volatile memory module and a test data generation method used by the memory controller.
Embodiments of the present invention provide a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The storage controller includes: the device comprises a connection interface circuit, a memory interface control circuit, a test data circuit unit and a processor. The connection interface circuit is used for being coupled to a host system. The memory interface control circuit is configured to couple to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical pages. The processor is coupled to the connection interface circuit, the memory interface control circuit and the test data circuit unit. The processor is used for instructing the test data circuit unit to execute a test data generating operation according to a predetermined zero-one ratio and a predetermined integer range of corresponding test data so as to generate the test data. The test data generating operation includes the steps of: (1) determining a conversion threshold according to the predetermined zero-one ratio corresponding to the test data and the predetermined integer range, wherein the conversion threshold is one of a plurality of consecutive integers in the predetermined integer range; (2) generating a target random integer within the predetermined range of integers; (3) judging whether the target random integer is larger than the conversion threshold value; wherein in response to determining that the target random integer is greater than the conversion threshold value, converting the target random integer to 1 and setting an ith bit of the test data to the target random integer, where i has an initial value of 1 and the test data has a total of N bits, where N is a positive integer, wherein in response to determining that the target random integer is not greater than the conversion threshold value, converting the target random integer to 0 and setting the ith bit of the test data to the target random integer; and (4) determining whether i is equal to N, wherein in response to determining that i is not equal to N, adding 1 to i, and re-executing step (2); wherein in response to determining that i is equal to N, the test data is responded to the processor according to the set N bits of the test data, such that the test data is written to the rewritable non-volatile memory module via the processor.
In an embodiment of the invention, the plurality of consecutive integers in the predetermined integer range is 1 to 100.
In an embodiment of the present invention, the predetermined zero-one ratio is used to represent a ratio of a plurality of bit values "0" to a total number of respective plurality of bit values "1" among all bit values of the test value after desired generation.
In an embodiment of the invention, the conversion threshold value is equal to a sum of a starting value of the consecutive integers plus a first value, wherein the first value is a second value minus 1, wherein the second value is a ratio of a total number of the consecutive integers multiplied by a value 0, wherein the ratio of the value 0 is calculated by the predetermined ratio of zero and one.
Embodiments of the present invention provide a test data generation method for generating test data to be written to a rewritable nonvolatile memory module of a memory device. The method comprises the following steps: (1) determining a conversion threshold according to the predetermined zero-one ratio corresponding to the test data and the predetermined integer range, wherein the conversion threshold is one of a plurality of consecutive integers in the predetermined integer range; (2) generating a target random integer within the predetermined range of integers; (3) judging whether the target random integer is larger than the conversion threshold value; wherein in response to determining that the target random integer is greater than the conversion threshold value, converting the target random integer to 1 and setting an ith bit of the test data to the target random integer, where i has an initial value of 1 and the test data has a total of N bits, where N is a positive integer, wherein in response to determining that the target random integer is not greater than the conversion threshold value, converting the target random integer to 0 and setting the ith bit of the test data to the target random integer; and (4) determining whether i is equal to N, wherein in response to determining that i is not equal to N, adding 1 to i, and re-executing step (2); wherein in response to determining that i is equal to N, the test data is responded to according to the set N bits of the test data such that the test data is written to the rewritable non-volatile memory module.
Based on the above, the memory controller and the test data generating method provided by the embodiment of the invention can control the ratio between the total numbers of 0 and 1 in all bit values of the test data generated in a random manner in the case of customizing the predetermined zero-one ratio and the predetermined integer range corresponding to the predetermined zero-one ratio and the predetermined integer range of the test data. Therefore, the user-defined test data with different zero-one ratios can be generated under the condition that the data is relatively natural, so that the test data meeting the requirement of the specific zero-one ratio can be efficiently and flexibly generated, and the integrity of the reliability test executed on a plurality of blocks of the rewritable nonvolatile memory module by the generated test data can be maintained.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a block diagram illustrating a host system and a storage device according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating a method for generating test data according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a predetermined zero-to-one ratio and a conversion threshold according to an embodiment of the invention.
FIG. 4 is a diagram illustrating a configuration of test data according to an embodiment of the present invention.
Description of the reference numerals
10: host system
110. 211: processor with a memory having a plurality of memory cells
120: host memory
130: data transmission interface circuit
210: storage controller
212: data management circuit
213: memory interface control circuit
214: error checking and correcting circuit
215: test data circuit unit
216: buffer memory
217: power management circuit
220: rewritable nonvolatile memory module
230: connection interface circuit
S21, S22, S23, S24, S25, S26, S27, S28: the flow steps 300, 400 of the test data generation method: test data
A31, A411 to A412, A421 to A422, A431 to A432, A441 to A442, A451 to A452, A461 to A462, A471 to A472, A481 to A482: arrow head
400(1) - (400 (8)): bit/bit
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a block diagram illustrating a host system and a storage device according to an embodiment of the invention. Referring to fig. 1, a host system 10 is, for example, a personal computer, a notebook computer, or a server. The Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, a Data Transfer Interface Circuit (Data Interface Circuit)130, and a storage device 140. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120, the data transmission interface circuit 130 and the storage device. In another embodiment, the Processor (Processor)110, the host memory 120, the data transmission interface circuit 130 and the storage device 140 are coupled to each other by a System Bus (System Bus). In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10.
The Memory device 20 includes a Memory Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a Connection Interface Circuit (Connection Interface Circuit) 230. The Memory controller 210 includes a processor 211, a Data Management Circuit (Data Management Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.
In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.
In this embodiment, the number of the data transmission interface circuits 130 may be one or more. The motherboard can be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.
In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data by using a Non-Volatile Memory interface (NVMe) protocol.
However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-eMI) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-P Package) interface standard, multimedia Memory Card (Multi-Media) interface, Flash Memory standard (MMC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.
In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.
The memory controller 210 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.
More specifically, the processor 211 in the memory controller 210 is computing hardware for controlling the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control commands/program codes, and the control commands/program codes are executed to perform data writing, reading and erasing operations during the operation of the memory device 20. In addition, in the embodiment, the control instructions/program codes may also be executed to perform a test data generation operation, so as to implement the test data generation method provided by the present invention.
It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.
In one embodiment, the memory controller 210 further has a read only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (bootstrap code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit of the rewritable nonvolatile memory module 220 dedicated for storing system data.
In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be referred to as operations performed by the storage controller 210.
The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory cells of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.
The memory interface control circuit 213 is used to receive an instruction from the processor 211, and cooperate with the data management circuit 212 to perform a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220.
For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units of the rewritable nonvolatile memory module 220 corresponding to the read instruction; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.
In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence for instructing writing data, a test data write command sequence for instructing writing test data, a read command sequence for instructing reading data, an erase command sequence for instructing erasing data, and corresponding command sequences for instructing various memory operations. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In addition, the memory controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record an address mapping relationship between a Logical unit (e.g., a Logical block, a Logical page, or a Logical sector) and a Physical unit (e.g., a Physical erase unit/a Physical block, a Physical page, a Physical sector) configured To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may look up an entity unit mapped by a logic unit (e.g., look up an entity page mapped by a logic page; look up an entity address mapped by a logic address) through the logical-to-entity address mapping table, and the memory controller 210 may look up a logic unit mapped by an entity unit (e.g., look up a logic page mapped by an entity page; look up a logic address mapped by an entity address) through the entity-to-logic address mapping table. However, the technical concepts related to the mapping of the logical units and the physical units are conventional technical means for those skilled in the art and are not the technical solutions to be described in the present invention, and are not described herein again.
In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code. In addition, after the Error checking and correcting process, if the read data is successfully decoded, the Error checking and correcting circuit 214 may return an Error bit value to the processor 211. If the number of error bits corresponding to a piece of data is higher, the processor 211 may determine that the physical state of the physical unit (e.g., physical sector/physical page/physical block) for storing the data is worse.
In one embodiment, the memory controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and is used to control the power of the memory device 20.
The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 Bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one memory Cell), a three-dimensional NAND flash memory module (3D NAND flash memory module), or a Vertical flash memory module (Vertical flash memory module) or other same flash memory modules having the same memory module A memory module of a nature. The Memory cells (also called Memory cells) in the rewritable nonvolatile Memory module 220 are arranged in an array.
In the embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each of the word lines is coupled to a plurality of memory cells. A plurality of memory cells on the same word line constitute a physical program cell (also called a physical page). In addition, a plurality of physical pages may constitute one physical block (also called physical erase unit).
In the present embodiment, the minimum unit of the data size of the write data written into the rewritable non-volatile memory module 220 at a time is a Cluster (Cluster). The operating system executed by the host system 10 accesses/manages data written to the logical pages using the cluster as a minimum unit, and the operating system can grasp/manage the logical address and size of each data. The size of one cluster may be smaller than or equal to the size of one physical page. One cluster may have a plurality of sectors (sectors). The size of one cluster may be less than or equal to one logical page.
For convenience of explanation, in the following embodiments, the size of one cluster is equal to the size of one physical page, and the size of one physical page is also equal to the size of one logical page. Further, assume that the size of each physical page of the rewritable non-volatile memory module 220 is 1024 Bytes (Bytes). However, it should be noted that the present invention is not limited to the size of each physical page, logical page, cluster.
In this embodiment, in order to perform the reliability test on the physical block or the physical page, the processor 211 may first instruct the test data circuit unit 215 to perform the data test data generation operation to implement the test data generation method provided by the present invention, so as to obtain the test data for the reliability test. More specifically, processor 211 instructs the test data circuit cells to perform test data generation operations to generate the test data according to a "predetermined zero-to-one ratio" and a "predetermined integer range" corresponding to the test data for the reliability test. The test data generation method provided by the present invention will be described below with reference to fig. 2.
FIG. 2 is a flowchart illustrating a method for generating test data according to an embodiment of the invention. Referring to fig. 2, in step S21, the test data circuit unit 215 determines a conversion threshold according to a predetermined zero-one ratio corresponding to the test data and a predetermined integer range, wherein the conversion threshold is one of a plurality of consecutive integers in the predetermined integer range. Specifically, the test data circuit unit 215 may calculate a corresponding specific value within the predetermined integer range according to the predetermined zero-one ratio, and use the corresponding specific value as the conversion threshold. The following description will be made with reference to fig. 3.
FIG. 3 is a diagram illustrating a predetermined zero-to-one ratio and a conversion threshold according to an embodiment of the invention. Referring to fig. 3, in the present embodiment, the user can customize the predetermined zero-one ratio and the plurality of consecutive integers in the predetermined integer range. Here, it is assumed that a plurality of consecutive integers in the predetermined integer range are "1" to "100", and that the predetermined zero-one ratio is "3: 1".
More specifically, the predetermined zero-one ratio is used to represent the ratio of the number of bit values "0" to the total number of bit values "1" respectively among all the bit values (bits) of the desired generated test value. For example, as shown by arrow A31 of FIG. 3, the user presets a predetermined ratio of zero to one of 3, which indicates that the user desires to generate test data 300 having a ratio of the total number of bits "0" to the total number of bits "1" of 3:1 (i.e., 3).
The test data circuit unit 215 may calculate a specific value within the predetermined integer range according to a ratio of a total number (e.g., 100) of a plurality of consecutive integers in the predetermined integer range to zero or one, so that a ratio between the specific value and a total number of integers ordered before the specific value and a total number of consecutive integers ordered after the specific value is equal to the predetermined ratio of zero to one within the predetermined integer range.
For example, the specific value (i.e., the conversion threshold) can be calculated by the following equation:
the conversion threshold value ═ initial value + [ (total number of predetermined integer ranges) × (ratio of value 0) -1]
Wherein the "start value" is a value of a top-ranked integer of a plurality of consecutive integers of the predetermined range of integers; "a predetermined total number of ranges of integers" is a total number of the plurality of consecutive integers; the "occupancy of 0 value" is a value calculated according to the predetermined zero-one ratio such that the bits "0" occupy a percentage of the entire test data (e.g., the predetermined zero-one ratio is "3: 1", and the corresponding "occupancy of 0 value" is 3/(3+1) × 100 ═ 75 (%)).
The above calculation formula of the conversion threshold is merely exemplary, and the present invention is not limited thereto. Those skilled in the art can derive the specific value corresponding to the predetermined ratio of zero to one in the predetermined integer range as the conversion threshold value according to the predetermined ratio of the integer range to zero to one from the concept of setting the conversion threshold value from the upper part.
Referring back to FIG. 2, after determining/obtaining the transition threshold, the test data circuit unit 215 sets all bit values (bit values) of the test value (steps S22-S26).
More specifically, in step S22, the test data circuit unit 215 generates a target random integer within the predetermined integer range. For example, the test data circuit unit 215 may generate the target random integer by using a random function in a case where the generated random number is limited within the predetermined integer range (e.g., a maximum value and a minimum value of the generated random number are designated as a maximum value and a minimum value of the predetermined integer range, respectively).
Next, in step S23, the test data circuit unit 215 determines whether the target random integer is greater than the conversion threshold value.
In response to determining that the target random integer is greater than the conversion threshold value (S23 → YES), the test data circuit unit 215 performs step S24; in response to determining that the target random integer is not greater than the conversion threshold value (S23 → NO), the test data circuit unit 215 performs step S25.
In step S24, the test data circuit unit 215 converts the target random integer into 1, and sets the ith bit of the test data, where the initial value of i is 1, as the target random integer, and the test data has N bits (bits) in total, where N is a positive integer.
In step S25, the test data circuit unit 215 converts the target random integer into 0, and sets the i-th bit of the test data as the target random integer.
In brief, in the process of steps S23-S25, the test data circuit unit 215 determines to convert the generated target random integer from the current value to "1" or "0" according to whether the generated target random integer is greater than the conversion threshold, and assigns/sets the converted bit value (bit value) to the ith bit (bit) of the test data.
Next, in step S26, the test data circuit unit 215 determines whether i is equal to N.
In response to the determination that i is not equal to N, the test data circuit unit 215 performs step S27(S26 → NO); in response to the determination that i is equal to N (S26 → YES), the test data circuit unit 215 performs step S28.
In step S27, the test data circuit unit 215 adds 1 to i to set the value of the next bit of the test data.
That is, after repeating the steps S22-S27 for N times, all the values of the N bits (N bit values) of the test data are set, i.e., the test data generating operation is completed.
In step S28, the test data circuit unit 215 responds the test data to the processor 211 according to the set N bits (N bit values/bit values) of the test data, so that the test data is written to the rewritable nonvolatile memory module 220 via the processor 211.
Specifically, the test data circuit unit 215 may send the configured/generated test data back to the processor 211, so that the processor 211 may write the test to the rewritable nonvolatile memory module via the memory interface control circuit 213 according to the test data to perform the reliability test.
FIG. 4 is a diagram illustrating a configuration of test data according to an embodiment of the present invention. Referring to fig. 4, for convenience of explanation, it is assumed that the test data 400 to be generated has 8 bits (bits) 400(1) to 400(8) (i.e., N is 8), the predetermined integer range is "1" to "100", and the corresponding transition threshold is 75.
For the bit 400(1) to be set, the test data circuit unit 215 generates the target random integer "97" (step S22); as indicated by an arrow a411, the target random integer "97" is converted to "1" in accordance with the determination that the target random integer "97" is greater than the conversion threshold value "75" (step S23 → S24); next, as indicated by arrow a412, bit 400(1) is set to "1" according to the converted target random integer "1". Next, the test data circuit unit 215 sets the next bit of the test data 400.
Next, the test data circuit unit 215 generates a target random integer "36" for the bit 400(2) to be set (step S22); as indicated by an arrow a421, the target random integer "36" is converted to "0" in accordance with the determination that the target random integer "36" is not greater than the conversion threshold value "75" (step S23 → S25); next, as indicated by arrow a422, bit 400(1) is set to "0" according to the converted target random integer "0". Next, the test data circuit unit 215 sets the next bit of the test data 400.
For the bit 400(3) to be set, the test data circuit unit 215 generates the target random integer "17" (step S22); as indicated by an arrow a431, the target random integer "17" is converted to "0" in accordance with the determination that the target random integer "17" is not greater than the conversion threshold value "75" (step S23 → S25); next, as indicated by an arrow a432, the bit 400(3) is set to "0" according to the converted target random integer "0". Next, the test data circuit unit 215 sets the next bit of the test data 400.
For the bit 400(4) to be set, the test data circuit unit 215 generates the target random integer "74" (step S22); as indicated by an arrow a441, the target random integer "74" is converted to "0" in accordance with the determination that the target random integer "74" is not greater than the conversion threshold value "75" (step S23 → S25); next, as indicated by arrow a442, bits 400(4) are set to "0" according to the converted target random integer "0". Next, the test data circuit unit 215 sets the next bit of the test data 400.
For the bit 400(5) to be set, the test data circuit unit 215 generates the target random integer "36" (step S22); as indicated by an arrow a451, the target random integer "36" is converted to "0" in accordance with the determination that the target random integer "36" is not greater than the conversion threshold value "75" (step S23 → S25); next, as indicated by an arrow a452, the bit 400(5) is set to "0" in accordance with the converted target random integer "0". Next, the test data circuit unit 215 sets the next bit of the test data 400.
For the bit 400(6) to be set, the test data circuit unit 215 generates the target random integer "5" (step S22); as indicated by an arrow a461, converting the target random integer "5" to "0" in accordance with a determination that the target random integer "5" is not greater than the conversion threshold value "75" (step S23 → S25); next, as indicated by arrow a462, bit 400(6) is set to "0" according to the converted target random integer "0". Next, the test data circuit unit 215 sets the next bit of the test data 400.
For the bit 400(7) to be set, the test data circuit unit 215 generates the target random integer "89" (step S22); as indicated by an arrow a471, the target random integer "89" is converted to "1" in accordance with the determination that the target random integer "89" is greater than the conversion threshold value "75" (step S23 → S24); next, as indicated by an arrow a472, the bit 400(7) is set to "1" in accordance with the converted target random integer "1". Next, the test data circuit unit 215 sets the next bit of the test data 400.
For the bit 400(8) to be set, the test data circuit unit 215 generates the target random integer "49" (step S22); as indicated by an arrow a481, the target random integer "49" is converted to "0" in accordance with the determination that the target random integer "49" is not greater than the conversion threshold value "75" (step S23 → S25); next, as indicated by an arrow a482, the bits 400(8) are set to "0" in accordance with the converted target random integer "0".
At this time, all bits of the test data 400 are set, and the test data circuit unit 215 responds to the set test data 400 (i.e., "10000010") to the processor 211.
It should be noted that, in other embodiments, the test data circuit unit 215 may be implemented in software or firmware and executed by the processor 211, so as to implement the test data generating method provided by the present invention.
Based on the above, the memory controller and the test data generating method provided by the embodiment of the invention can control the ratio between the total numbers of 0 and 1 in all bit values of the test data generated in a random manner in the case of customizing the predetermined zero-one ratio and the predetermined integer range corresponding to the predetermined zero-one ratio and the predetermined integer range of the test data. Therefore, the user-defined test data with different zero-one ratios can be generated under the condition that the data is relatively natural, so that the test data meeting the requirement of the specific zero-one ratio can be efficiently and flexibly generated, and the integrity of the reliability test executed on a plurality of blocks of the rewritable nonvolatile memory module by the generated test data can be maintained.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:
a connection interface circuit for coupling to a host system;
a memory interface control circuit for coupling to the rewritable nonvolatile memory module;
a test data circuit unit; and
a processor coupled to the connection interface circuit, the memory interface control circuit, and the test data circuit unit,
wherein the processor is configured to instruct the test data circuit unit to perform a test data generating operation according to a predetermined zero-to-one ratio and a predetermined integer range of corresponding test data to generate the test data, the test data generating operation comprising the steps of:
(1) determining a conversion threshold according to the predetermined zero-one ratio corresponding to the test data and the predetermined integer range, wherein the conversion threshold is one of a plurality of consecutive integers in the predetermined integer range;
(2) generating a target random integer within the predetermined range of integers;
(3) judging whether the target random integer is larger than the conversion threshold value;
wherein in response to determining that the target random integer is greater than the conversion threshold, the target random integer is converted to 1 and the ith bit of the test data is set to the target random integer, where i has an initial value of 1 and the test data has a total of N bits, where N is a positive integer,
wherein in response to determining that the target random integer is not greater than the conversion threshold, converting the target random integer to 0 and setting an i-th bit of the test data to the target random integer; and
(4) it is determined whether i is equal to N,
wherein in response to determining that i is not equal to N, adding 1 to i, and re-performing step (2);
wherein in response to determining that i is equal to N, the test data is responded to the processor according to the set N bits of the test data, such that the test data is written to the rewritable non-volatile memory module via the processor.
2. The storage controller of claim 1, wherein the plurality of consecutive integers in the predetermined range of integers is from 1 to 100.
3. The memory controller of claim 2, wherein the predetermined zero-one ratio is used to represent a ratio of a number of bit values 0 to a total number of bit values 1, respectively, among all bit values of the desired generated test value.
4. The storage controller of claim 3, wherein the conversion threshold is equal to a sum of a starting value of the plurality of consecutive integers plus a first value, wherein the first value is a second value minus 1, wherein the second value is a ratio of a total number of the plurality of consecutive integers multiplied by a value 0, wherein the ratio of the value 0 is calculated via the predetermined zero-one ratio.
5. A method for generating test data for writing to a rewritable nonvolatile memory module of a memory device, the method comprising:
(1) determining a conversion threshold according to a predetermined zero-one ratio corresponding to the test data and the predetermined integer range, wherein the conversion threshold is one of a plurality of consecutive integers in the predetermined integer range;
(2) generating a target random integer within the predetermined range of integers;
(3) judging whether the target random integer is larger than the conversion threshold value;
wherein in response to determining that the target random integer is greater than the conversion threshold, the target random integer is converted to 1 and the ith bit of the test data is set to the target random integer, where i has an initial value of 1 and the test data has a total of N bits, where N is a positive integer,
wherein in response to determining that the target random integer is not greater than the conversion threshold, converting the target random integer to 0 and setting an i-th bit of the test data to the target random integer; and
(4) it is determined whether i is equal to N,
wherein in response to determining that i is not equal to N, adding 1 to i, and re-performing step (2);
wherein in response to determining that i is equal to N, the test data is responded to according to the set N bits of the test data such that the test data is written to the rewritable non-volatile memory module.
6. The test data generation method of claim 5, wherein the plurality of consecutive integers in the predetermined range of integers is from 1 to 100.
7. The method of claim 6, wherein the predetermined zero-one ratio is used to represent a ratio of a number of bit values 0 to a total number of bit values 1 among all bit values of the desired generated test value.
8. The method of claim 7, wherein the conversion threshold is equal to a sum of a starting value of the consecutive integers plus a first value, wherein the first value is a second value minus 1, wherein the second value is a ratio of a total number of the consecutive integers multiplied by a value 0, wherein the ratio of the value 0 is calculated via the predetermined zero-one ratio.
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