CN112736078B - PNP high-voltage ESD device and LDMOS based on BCD technology - Google Patents

PNP high-voltage ESD device and LDMOS based on BCD technology Download PDF

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CN112736078B
CN112736078B CN201911028049.7A CN201911028049A CN112736078B CN 112736078 B CN112736078 B CN 112736078B CN 201911028049 A CN201911028049 A CN 201911028049A CN 112736078 B CN112736078 B CN 112736078B
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esd device
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CN112736078A (en
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林威
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GTA Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thyristors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a PNP type high-voltage ESD device and an LDMOS (laterally diffused metal oxide semiconductor) based on a BCD (binary-coded decimal) process, wherein the PNP type high-voltage ESD device comprises a P type collector electrode, a P type emitter electrode and a first STI (shallow trench isolation) positioned between the P type collector electrode and the P type emitter electrode, and the standard length of the first STI is expressed as L; the first STI has a length ofThe PNP high-voltage ESD device further comprises a polysilicon gate, wherein the polysilicon gate is positioned in the upper area of the two ends of the first STI and the P-type emitter. According to the invention, by adjusting the structure of the PNP type high-voltage ESD device, the higher secondary breakdown current It2, the lower on-resistance Ron and the lower secondary breakdown voltage Vt2 are obtained on the premise that a photomask is not increased in the LDMOS manufacturing process. The PNP type high-voltage ESD device manufactured by the method has the advantages that the secondary breakdown current It2 is doubled, the on-resistance Ron is reduced by about 2/3, the size of the device is reduced, and the performance of the device is greatly improved.

Description

PNP high-voltage ESD device and LDMOS based on BCD technology
Technical Field
The invention relates to an ESD (Electro-STATIC DISCHARGE, electrostatic discharge) device, in particular to a PNP high-voltage ESD device and LDMOS (LATERALLY-Diffused Metal-Oxide Semiconductor, lateral diffusion metal oxide semiconductor) based on a BCD (Bipolar-CMOS-DMOS) process.
Background
ESD phenomenon is a serious problem for normal operation of a semiconductor device, and ESD devices can be classified into a discharge flow pattern based on forward conduction and a discharge flow pattern based on negative resistance effect. For ESD devices, the second breakdown current It2, the on-resistance Ron, and the second breakdown voltage Vt2 are significant for device design. Therefore, in the LDMOS manufacturing process, how to improve the current bearing capability of the ESD device, i.e., the second breakdown current It2, the on-resistance Ron and the second breakdown voltage Vt2, and the volume of the ESD device without increasing the process cost in the existing BCD process is a concern.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of lower secondary breakdown current It2, higher on-resistance Ron, higher secondary breakdown voltage Vt2 and larger device volume of a PNP type high-voltage ESD device in the existing manufacturing process of the semiconductor LDMOS based on the BCD technology, and provide the PNP type high-voltage ESD device and the LDMOS based on the BCD technology.
The invention solves the technical problems by the following technical scheme:
The invention provides a PNP type high-voltage ESD device based on a BCD process, which comprises a P type collector electrode, a P type emitter electrode and a first STI (shallow trench isolation) positioned between the P type collector electrode and the P type emitter electrode, wherein the standard length of the first STI is expressed as L;
the first STI has a length of The PNP type high-voltage ESD device further comprises a polysilicon gate, wherein the polysilicon gate is positioned in the upper area of the two ends of the first STI adjacent to the P type emitter.
In the scheme, the structure of the existing PNP type high-voltage ESD device with the first STI with the standard length is adjusted, specifically, the size of the STI between the P type collector and the P type emitter in the existing PNP type high-voltage ESD device is reduced to one third to one half of the original size, and meanwhile, a polysilicon Gate (Poly Gate) is used for making up, so that the PNP type high-voltage ESD device with the first STI with the standard length has higher current uniformity, lower on-resistance Ron and secondary breakdown voltage Vt2 and higher secondary breakdown current It2 compared with the existing PNP type high-voltage ESD device with the first STI with the standard length can be obtained, and meanwhile, the size of the device is reduced.
Preferably, the standard length has a value ranging from 1 to 2 microns.
Preferably, the PNP type high voltage ESD device is a PNP type triode.
Preferably, the operating voltage of the PNP type high voltage ESD device ranges from 40 to 65V (volts).
Preferably, the PNP type high voltage ESD device further comprises: an N-type base, a P substrate, a high-voltage N well, a P-type drift region, an N-type drift region, a second STI, a third STI, a fourth STI, a first N well and a second N well;
the high-voltage N well is positioned in the P substrate;
the P-type drift region and the N-type drift region are arranged in the high-voltage N well and are adjacent to each other;
The third STI, the N-type base electrode and the fourth STI are sequentially arranged on one side of the P-type emitter, which is far away from the first STI;
the second STI is positioned at one side of the P-type collector away from the first STI;
the P-type drift region spans a region between the first STI and the second STI;
the N-type drift region spans a region between the first STI and the fourth STI;
The first N well and the second N well are arranged in the N-type drift region;
The first N well spans the region between the polysilicon gate and the third STI;
The second N-well spans a region between the third STI and the fourth STI.
Preferably, the node range of the BCD process is 65-180 nm (nanometers).
The invention also provides an LDMOS which comprises the PNP type high-voltage ESD device based on the BCD technology.
Preferably, the LDMOS is a high-voltage LDMOS.
The invention has the positive progress effects that:
the invention provides a PNP type high-voltage ESD device and an LDMOS (laterally diffused metal oxide semiconductor) based on a BCD (binary-semiconductor) process, which realize that a higher secondary breakdown current It2, a lower on-resistance Ron and a lower secondary breakdown voltage Vt2 are obtained on the premise that a photomask is not increased in the LDMOS manufacturing process by adjusting the structure of the PNP type high-voltage ESD device. The PNP type high-voltage ESD device manufactured by the method has the advantages that the secondary breakdown current It2 is doubled, the on-resistance Ron is reduced by about 2/3, the size of the device is reduced, and the performance of the device is greatly improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a PNP type high voltage ESD device based on BCD process according to embodiment 1 of the invention.
Fig. 2 is a schematic cross-sectional view of a conventional PNP type high voltage ESD device based on BCD process in the prior art.
Fig. 3 is a current density diagram of the second breakdown voltage Vt2 corresponding to the PNP type high voltage ESD device based on BCD process according to embodiment 1 of the present invention.
Fig. 4 is a current density diagram of the second breakdown voltage Vt2 corresponding to the PNP type high voltage ESD device based on the BCD process in the prior art.
Fig. 5 is an electric field intensity diagram of the second breakdown voltage Vt2 corresponding to the PNP type high voltage ESD device based on BCD process in embodiment 1 of the present invention.
Fig. 6 is an electric field intensity diagram of a second breakdown voltage Vt2 corresponding to a PNP type high voltage ESD device based on a BCD process in the prior art.
Fig. 7 is a comparison graph of TLP (transmission line pulse technique) test curves corresponding to the PNP type high-voltage ESD device based on BCD process and the conventional PNP type high-voltage ESD device based on BCD process according to embodiment 1 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the present embodiment discloses a PNP type high voltage ESD device based on BCD technology, which includes a P substrate 1, a high voltage N well 2, a P type drift region 3, an N type drift region 4, a first N well 5, a second N well 6, an N type base 13, a P type collector 11, a P type emitter 12, a polysilicon gate 14, a gate oxide layer 15, a first STI8, a second STI7, a third STI9, and a fourth STI10. The PNP type high-voltage ESD device is a PNP triode; the range of the working voltage is 40-65V; the node range of the BCD technology is 65-180 nm.
Wherein the first STI8 is located between the P-type collector 11 and the P-type emitter 12. The polysilicon gate 14 is located in an upper region of the first STI8 and the P-type emitter 12 at both ends adjacent thereto. A gate oxide layer 15 is located between the polysilicon gate 14 and the second STI8 and the P-type emitter 12. The high-voltage N well 2 is positioned in the P substrate 1; the P-type drift region 3 and the N-type drift region 4 are arranged in the high-voltage N well 2 and are adjacent to each other; the first N well 5 and the second N well 6 are arranged in the N type drift region 4; the side of the P-type emitter 12 far away from the first STI8 is sequentially provided with a third STI9, an N-type base 13 and a fourth STI10; the second STI7 is located on the side of the P-type collector 11 remote from the first STI 8. Specifically, the P-type drift region 3 spans the region between the first STI8 and the second STI 7; the N-type drift region 4 spans the region between the first STI8 and the fourth STI10; the first N-well 5 spans the region between the polysilicon gate 14 and the third STI; the second N-well 6 spans the region between the third STI9 and the fourth STI 10.
As shown in fig. 2, the length of the first STI8' of the conventional PNP high-voltage ESD device based on BCD in the prior art is a standard length, the value range is 1-2 micrometers, the standard length is denoted as L, and the length of the first STI8 in this embodiment isIn this embodiment, the STI at the P-type emitter 12 end, i.e., the first STI8, is pulled back, and the pulled back dimension is replaced by the polysilicon gate, specifically, the dimension of the STI located between the P-type collector and the P-type emitter in the existing PNP-type high-voltage ESD device is reduced to one third to one half, and meanwhile, the polysilicon gate is used for compensation, so that the PNP-type high-voltage ESD device with the first STI having the standard length has higher current uniformity, lower on-resistance Ron and secondary breakdown voltage Vt2, and higher secondary breakdown current It2, and meanwhile, the volume of the device is reduced.
Fig. 3 and fig. 4 are current density diagrams of the second breakdown voltage Vt2 corresponding to the PNP type high-voltage ESD device based on BCD process disclosed in the present embodiment and the existing PNP type high-voltage ESD device based on BCD process in fig. 2, respectively, and it is found by comparison that the PNP type high-voltage ESD device based on BCD process corresponding to fig. 2 has no Poly Gate, and the second breakdown voltage Vt2 depends on junction concentration; in the case of adding PolyGate to the PNP type high-voltage ESD device based on BCD technology disclosed in this embodiment, the current distribution increases, the current density is more uniform, the SPACE CHARGE (space charge) region increases, and the secondary breakdown current It2 increases.
Fig. 5 and fig. 6 are electric field intensity diagrams of the second breakdown voltage Vt2 corresponding to the PNP type high voltage ESD device based on the BCD process disclosed in the present embodiment and the conventional PNP type high voltage ESD device based on the BCD process shown in fig. 2, respectively. In contrast, the PNP high-voltage ESD device based on BCD technology disclosed in this embodiment is found to have more concentrated electric field strength and a breakdown point far away from the PN junction when Poly Gate is added.
Fig. 7 is a comparison chart of TLP test curves corresponding to the PNP type high-voltage ESD device based on BCD process disclosed in this embodiment and the conventional PNP type high-voltage ESD device based on BCD process in fig. 2, wherein curve 16 corresponds to this embodiment, and curve 17 corresponds to the conventional PNP type high-voltage ESD device. Both trigger voltages Vt1 are 80V, the second breakdown voltage Vt2 in this embodiment is 90V, and the second breakdown voltage Vt2 of the conventional PNP high-voltage ESD device based on BCD process in FIG. 2 is 110V, i.e. the response is that the embodiment obtains relatively lower second breakdown voltage Vt2 on the curve. Simulation results and test results show that the PNP type high-voltage ESD device based on the BCD technology disclosed by the embodiment realizes that the secondary breakdown current It2 is increased by about one time, the on-resistance Ron is reduced by about 2/3, the secondary breakdown voltage Vt2 is reduced, the size of the device is reduced, and the performance of the device is greatly improved by adjusting the structure of the PNP type high-voltage ESD device under the condition that a photomask is not increased through adjusting the structure of the PNP type high-voltage ESD device.
Example 2
The embodiment discloses an LDMOS, which is a high-voltage LDMOS and comprises the PNP type high-voltage ESD device based on the BCD technology disclosed in the embodiment 1. The PNP type high-voltage ESD device based on the BCD technology is used for achieving ESD protection of the high-voltage LDMOS. Under the condition that the peak voltage caused by the instantaneous current of the LDMOS exceeds the working voltage of 40-65V but does not reach the secondary breakdown voltage, the current is guided through the PNP type high-voltage ESD device, so that ESD protection is realized. In this embodiment, by adjusting the PNP type high-voltage ESD device structure, a higher second breakdown current It2, a lower on-resistance Ron and a lower second breakdown voltage Vt2 are obtained without increasing a photomask in the LDMOS manufacturing process. The size of the device can be reduced, and the performance of the device is greatly improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims (5)

1. A PNP type high-voltage ESD device based on a BCD process, comprising a P type collector, a P type emitter and a first STI positioned between the P type collector and the P type emitter, wherein the standard length of the first STI is expressed as L;
characterized in that the first STI has a length of The PNP type high-voltage ESD device further comprises a polysilicon gate, wherein the polysilicon gate is positioned in the upper area of the two ends of the first STI adjacent to the P type emitter;
The value range of the standard length is 1-2 micrometers;
the working voltage range of the PNP type high-voltage ESD device is 40-65V;
the node range of the BCD process is 65-180 nm;
the PNP type high-voltage ESD device further comprises a gate oxide layer;
the gate oxide layer is positioned among the polysilicon gate, the first STI and the P-type emitter.
2. The BCD-based PNP high voltage ESD device of claim 1, wherein said PNP high voltage ESD device is a PNP transistor.
3. The BCD-process-based PNP high voltage ESD device of claim 1, further comprising: an N-type base, a P substrate, a high-voltage N well, a P-type drift region, an N-type drift region, a second STI, a third STI, a fourth STI, a first N well and a second N well;
the high-voltage N well is positioned in the P substrate;
the P-type drift region and the N-type drift region are arranged in the high-voltage N well and are adjacent to each other;
The third STI, the N-type base electrode and the fourth STI are sequentially arranged on one side of the P-type emitter, which is far away from the first STI;
the second STI is positioned at one side of the P-type collector away from the first STI;
the P-type drift region spans a region between the first STI and the second STI;
the N-type drift region spans a region between the first STI and the fourth STI;
The first N well and the second N well are arranged in the N-type drift region;
The first N well spans the region between the polysilicon gate and the third STI;
The second N-well spans a region between the third STI and the fourth STI.
4. An LDMOS comprising a PNP high voltage ESD device based on a BCD process according to any of claims 1 to 3.
5. The LDMOS of claim 4, wherein the LDMOS is a high-voltage LDMOS.
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