CN112736078A - PNP type high-voltage ESD device based on BCD process and LDMOS - Google Patents
PNP type high-voltage ESD device based on BCD process and LDMOS Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract description 33
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The invention discloses a PNP type high-voltage ESD device and an LDMOS (laterally diffused metal oxide semiconductor) based on a BCD (binary coded decimal) process, wherein the PNP type high-voltage ESD device comprises a P type collector electrode, a P type emitter electrode and a first STI (shallow trench isolation) positioned between the P type collector electrode and the P type emitter electrode, and the standard length of the first STI is expressed as L; the first STI has a length of
The PNP type high-voltage ESD device further comprises a polysilicon gate, and the polysilicon gate is located in the upper regions of two ends, adjacent to the first STI and the P type emitter. According to the invention, by adjusting the structure of the PNP type high-voltage ESD device, a higher secondary breakdown current It2, a lower on-resistance Ron and a lower secondary breakdown voltage Vt2 are obtained on the premise of not increasing a photomask in the LDMOS manufacturing process. According to the PNP type high-voltage ESD device manufactured by the invention, the secondary breakdown current It2 is increased by about one time, the on-resistance Ron is reduced by about 2/3, and meanwhile, the device is reducedThe volume greatly improves the performance of the device.
Description
Technical Field
The present invention relates to an ESD (Electro-Static discharge) device, and more particularly, to a PNP (PNP-type high voltage ESD device and an LDMOS (Laterally Diffused Metal-Oxide Semiconductor) based on a BCD (Bipolar-CMOS-DMOS) process.
Background
The ESD phenomenon is a serious problem for the normal operation of the semiconductor device, and the ESD device may be classified into a forward-on leakage current type based on a negative resistance effect and an on leakage current type based on a positive resistance effect. For an ESD device, the second breakdown current It2, the on-resistance Ron, and the second breakdown voltage Vt2 are significant for the design of the device. Therefore, in the manufacturing process of the LDMOS, how to improve the current endurance capability of the ESD device, i.e. the second breakdown current It2, the on-resistance Ron and the second breakdown voltage Vt2, and improve the volume of the ESD device, without increasing the process cost in the conventional BCD process is a current concern.
Disclosure of Invention
The invention provides a PNP type high-voltage ESD device based on a BCD process and an LDMOS, and aims to overcome the defects that in the existing manufacturing process of the semiconductor LDMOS based on the BCD process, the secondary breakdown current It2 of the PNP type high-voltage ESD device is low, the on-resistance Ron is high, the secondary breakdown voltage Vt2 is high, and the size of the device is large.
The invention solves the technical problems through the following technical scheme:
the invention provides a PNP type high-voltage ESD device based on a BCD process, which comprises a P type collector electrode, a P type emitter electrode and a first STI (shallow trench isolation) positioned between the P type collector electrode and the P type emitter electrode, wherein the standard length of the first STI is expressed as L;
the first STI has a length of
The PNP type high-voltage ESD device further comprises a polysilicon gate, wherein the polysilicon gate is located in the upper regions of two adjacent ends of the first STI and the P type emitter.
In the scheme, the structure of the existing PNP type high-voltage ESD device with the first STI with the standard length is adjusted, specifically, the size of the STI between the P type collector and the P type emitter in the existing PNP type high-voltage ESD device is reduced to one third to one half of the original size, and meanwhile, the polysilicon Gate (Poly Gate) is used for making up, so that higher current uniformity, lower on-resistance Ron and second breakdown voltage Vt2 and higher second breakdown current It2 compared with the existing PNP type high-voltage ESD device with the first STI with the standard length can be obtained, and meanwhile, the size of the device is also reduced.
Preferably, the standard length ranges from 1 micron to 2 microns.
Preferably, the PNP type high voltage ESD device is a PNP type triode.
Preferably, the working voltage of the PNP high-voltage ESD device ranges from 40 to 65V (volts).
Preferably, the PNP type high voltage ESD device further includes: the device comprises an N-type base electrode, a P substrate, a high-voltage N well, a P-type drift region, an N-type drift region, a second STI, a third STI, a fourth STI, a first N well and a second N well;
the high-voltage N-well is positioned in the P substrate;
the P-type drift region and the N-type drift region are arranged in the high-voltage N well and are adjacent;
the third STI, the N-type base and the fourth STI are sequentially arranged on one side of the P-type emitter, which is far away from the first STI;
the second STI is positioned on one side of the P-type collector away from the first STI;
the P-type drift region spans a region between the first STI and the second STI;
the N-type drift region spans a region between the first STI and the fourth STI;
the first N well and the second N well are arranged in the N-type drift region;
the first N well spans a region between the polysilicon gate and the third STI;
the second N-well spans a region between the third STI and the fourth STI.
Preferably, the node range of the BCD process is 65-180 nm (nanometers).
The invention also provides an LDMOS, which comprises the PNP type high-voltage ESD device based on the BCD process.
Preferably, the LDMOS is a high voltage LDMOS.
The positive progress effects of the invention are as follows:
the invention provides a PNP type high-voltage ESD device based on a BCD process and an LDMOS, and achieves the purposes of obtaining higher secondary breakdown current It2, lower on-resistance Ron and lower secondary breakdown voltage Vt2 on the premise of not increasing a photomask in the LDMOS manufacturing process by adjusting the structure of the PNP type high-voltage ESD device. According to the PNP type high-voltage ESD device manufactured by the invention, the secondary breakdown current It2 is increased by about one time, the on-resistance Ron is reduced by about 2/3, the size of the device is reduced, and the performance of the device is greatly improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a PNP type high-voltage ESD device based on BCD process in embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional view of a conventional PNP-type high-voltage ESD device based on BCD process in the prior art.
Fig. 3 is a current density diagram of a second breakdown voltage Vt2 corresponding to the PNP type high-voltage ESD device based on the BCD process in embodiment 1 of the present invention.
Fig. 4 is a current density diagram of a second breakdown voltage Vt2 corresponding to a conventional PNP-type high-voltage ESD device based on BCD process in the prior art.
Fig. 5 is a diagram of the electric field strength of the second breakdown voltage Vt2 corresponding to the PNP type high-voltage ESD device based on the BCD process in embodiment 1 of the present invention.
Fig. 6 is a diagram of an electric field strength of a second breakdown voltage Vt2 corresponding to a conventional PNP-type high-voltage ESD device based on BCD process in the prior art.
Fig. 7 is a TLP (transmission line pulse technique) test curve comparison chart of the PNP type high-voltage ESD device based on the BCD process and the conventional PNP type high-voltage ESD device based on the BCD process in embodiment 1 of the invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the present embodiment discloses a PNP type high voltage ESD device based on BCD process, which includes a P substrate 1, a high voltage N well 2, a P type drift region 3, an N type drift region 4, a first N well 5, a second N well 6, an N type base 13, a P type collector 11, a P type emitter 12, a polysilicon gate 14, a gate oxide layer 15, a first STI8, a second STI7, a third STI9, and a fourth STI 10. The PNP type high-voltage ESD device is a PNP type triode; the working voltage range is 40-65V; the node range of the BCD process is 65-180 nm.
Wherein the first STI8 is located between the P-type collector 11 and the P-type emitter 12. The polysilicon gate 14 is located in the upper region of the first STI8 adjacent both ends of the P-type emitter 12. The gate oxide layer 15 is located between the polysilicon gate 14 and the second STI8 and the P-type emitter 12. The high-voltage N well 2 is positioned in the P substrate 1; the P-type drift region 3 and the N-type drift region 4 are arranged in the high-voltage N well 2 and are adjacent; the first N well 5 and the second N well 6 are arranged in the N-type drift region 4; the side of the P-type emitter 12 far away from the first STI8 is sequentially provided with a third STI9, an N-type base 13 and a fourth STI 10; the second STI7 is located on the side of the P-type collector 11 away from the first STI 8. Specifically, the P-type drift region 3 spans the region between the first STI8 and the second STI 7; the N-type drift region 4 spans the region between the first STI8 and the fourth STI 10; the first N-well 5 spans the region between the polysilicon gate 14 and the third STI; the second N-well 6 spans the region between the third STI9 and the fourth STI 10.
As shown in fig. 2, the length of the first STI 8' of the conventional PNP high-voltage ESD device based on BCD process in the prior art is a standard length, which is 1-2 micrometers, and the standard length is denoted as L, in this embodiment, the length of the first STI8 is denoted as L
In this embodiment, the STI at the end of the P-type emitter 12, that is, the first STI8 is pulled back, and the polysilicon gate is used to replace the pulled-back size, specifically, the size of the STI located between the P-type collector and the P-type emitter in the existing PNP-type high-voltage ESD device is reduced to one third to one half of the original size, and the polysilicon gate is used to make up the STI, so that higher current uniformity, lower on-resistance Ron and second breakdown voltage Vt2, and higher second breakdown current It2 can be obtained compared with the existing PNP-type high-voltage ESD device with the first STI having a standard length, and meanwhile, the first STI8 is pulled back, and the polysilicon gate is used to replace the pulled-The volume of the device is also reduced.
Fig. 3 and fig. 4 are current density graphs of the second breakdown voltage Vt2 corresponding to the PNP high-voltage ESD device based on BCD process disclosed in this embodiment and the conventional PNP high-voltage ESD device based on BCD process in fig. 2, respectively, and it is found by comparison that the conventional PNP high-voltage ESD device based on BCD process in fig. 2 has no Poly Gate, and the second breakdown voltage Vt2 depends on the junction concentration; in the case of increasing PolyGate, the current distribution of the PNP high-voltage ESD device based on the BCD process disclosed in this embodiment is increased, the current density is more uniform, the space charge (space charge) area is increased, and the secondary breakdown current It2 is increased.
Fig. 5 and fig. 6 are electric field intensity diagrams of the second breakdown voltage Vt2 of the PNP high-voltage ESD device based on BCD process disclosed in this embodiment and the conventional PNP high-voltage ESD device based on BCD process in fig. 2, respectively. In contrast, in the case that the Poly Gate is added to the PNP type high-voltage ESD device based on the BCD process disclosed in this embodiment, the electric field strength is more concentrated, and the breakdown point is far away from the PN junction.
Fig. 7 is a TLP test curve comparison graph of the PNP high-voltage ESD device based on BCD process disclosed in this embodiment and the conventional PNP high-voltage ESD device based on BCD process in fig. 2, where the curve 16 corresponds to this embodiment, and the curve 17 corresponds to the conventional PNP high-voltage ESD device. Both the trigger voltages Vt1 are 80V, the second breakdown voltage Vt2 is 90V in this embodiment, and the second breakdown voltage Vt2 of the conventional PNP-type high-voltage ESD device based on BCD process in fig. 2 is 110V, i.e. it is reflected in the curve that the embodiment obtains a relatively low second breakdown voltage Vt 2. Both simulation results and test results show that the PNP type high-voltage ESD device based on the BCD process disclosed in this embodiment realizes that the secondary breakdown current It2 is increased by about one time, the on-resistance Ron is reduced by about 2/3, the secondary breakdown voltage Vt2 is reduced, the size of the device is reduced, and the performance of the device is greatly improved by adjusting the structure of the PNP type high-voltage ESD device without adding a photomask.
Example 2
The embodiment discloses an LDMOS which is a high-voltage LDMOS, and includes the PNP type high-voltage ESD device based on the BCD process disclosed in embodiment 1. The PNP type high-voltage ESD device based on the BCD process is used for achieving ESD protection of the high-voltage LDMOS. Under the condition that the peak voltage caused by the instantaneous current of the LDMOS exceeds the working voltage of 40-65V of the LDMOS but does not reach the secondary breakdown voltage, the current is guided through the PNP type high-voltage ESD device, and therefore ESD protection is achieved. In the embodiment, by adjusting the structure of the PNP-type high-voltage ESD device, a higher secondary breakdown current It2, a lower on-resistance Ron and a lower secondary breakdown voltage Vt2 can be obtained without adding a photomask in the LDMOS manufacturing process. The size of the device can be reduced, and the performance of the device is greatly improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (8)
1. A PNP type high-voltage ESD device based on a BCD process comprises a P type collector, a P type emitter and a first STI (shallow trench isolation) positioned between the P type collector and the P type emitter, wherein the standard length of the first STI is represented as L;
wherein the first STI has a length of
The PNP type high-voltage ESD device further comprises a polysilicon gate, wherein the polysilicon gate is located in the upper regions of two adjacent ends of the first STI and the P type emitter.
2. The PNP type high-voltage ESD device based on BCD process according to claim 1, wherein the standard length is in the range of 1-2 μm.
3. The BCD process-based PNP type high voltage ESD device according to claim 1, wherein the PNP type high voltage ESD device is a PNP type triode.
4. The BCD process-based PNP type high-voltage ESD device according to claim 1, wherein the working voltage of the PNP type high-voltage ESD device is in the range of 40-65V.
5. The BCD process-based PNP type high voltage ESD device according to claim 1, further comprising: the device comprises an N-type base electrode, a P substrate, a high-voltage N well, a P-type drift region, an N-type drift region, a second STI, a third STI, a fourth STI, a first N well and a second N well;
the high-voltage N-well is positioned in the P substrate;
the P-type drift region and the N-type drift region are arranged in the high-voltage N well and are adjacent;
the third STI, the N-type base and the fourth STI are sequentially arranged on one side of the P-type emitter, which is far away from the first STI;
the second STI is positioned on one side of the P-type collector away from the first STI;
the P-type drift region spans a region between the first STI and the second STI;
the N-type drift region spans a region between the first STI and the fourth STI;
the first N well and the second N well are arranged in the N-type drift region;
the first N well spans a region between the polysilicon gate and the third STI;
the second N-well spans a region between the third STI and the fourth STI.
6. The PNP type high-voltage ESD device based on BCD process according to any of claims 1 to 5, wherein the node range of BCD process is 65-180 nm.
7. An LDMOS, comprising a PNP type high voltage ESD device based on BCD process as claimed in any one of claims 1 to 6.
8. The LDMOS of claim 7, wherein the LDMOS is a high voltage LDMOS.
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| CN201911028049.7A CN112736078A (en) | 2019-10-28 | 2019-10-28 | PNP type high-voltage ESD device based on BCD process and LDMOS |
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| CN201911028049.7A CN112736078A (en) | 2019-10-28 | 2019-10-28 | PNP type high-voltage ESD device based on BCD process and LDMOS |
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Citations (7)
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| US20120175673A1 (en) * | 2011-01-12 | 2012-07-12 | Mueng-Ryul Lee | Semiconductor device and fabricating method thereof |
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2019
- 2019-10-28 CN CN201911028049.7A patent/CN112736078A/en active Pending
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| US6316805B1 (en) * | 2000-01-06 | 2001-11-13 | Vanguard International Semiconductor Corporation | Electrostatic discharge device with gate-controlled field oxide transistor |
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| CN102969312A (en) * | 2012-12-18 | 2013-03-13 | 江南大学 | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate |
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