CN112713858B - Oscillator - Google Patents

Oscillator Download PDF

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Publication number
CN112713858B
CN112713858B CN202011528074.4A CN202011528074A CN112713858B CN 112713858 B CN112713858 B CN 112713858B CN 202011528074 A CN202011528074 A CN 202011528074A CN 112713858 B CN112713858 B CN 112713858B
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China
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circuit
coupled
output
chopper
output end
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CN112713858A (en
Inventor
雷宇超
张旭
陈光胜
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Shanghai Eastsoft Microelectronics Co ltd
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Shanghai Eastsoft Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature

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  • Amplifiers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

An oscillator, comprising: the chopper voltage average value feedback circuit is characterized in that one input end of the chopper voltage average value feedback circuit inputs temperature drift calibration reference voltage, and the other input end of the chopper voltage average value feedback circuit is coupled with one voltage output end of the RC charge-discharge circuit; the input end of the threshold voltage detection circuit is respectively coupled with the chopper voltage average value feedback circuit and the RC charge-discharge circuit; the other two voltage output ends of the RC charge-discharge circuit are coupled with the two input ends of the threshold voltage detection circuit; two output ends of the threshold voltage detection circuit are coupled with two input ends of the ESR trigger control circuit; two input ends of the stable clock output circuit are coupled with two output ends of the ESR trigger control circuit, the two output ends respectively output two paths of clock signals, and the other output end outputs a clock stability indication signal; and the two signal input ends of the chopper clock bootstrap circuit are respectively coupled with the second output end and the third output end of the stable clock output circuit. The output clock frequency of the oscillator is independent of temperature and voltage.

Description

Oscillator
Technical Field
The present disclosure relates to electronic circuits, and particularly to an oscillator.
Background
An oscillator is an energy conversion device that can produce an alternating signal of a certain frequency, a certain amplitude and a certain waveform. Due to the integration requirements, the microcontroller (Micro Controller Unit, MCU) chip requires an integrated high precision oscillator inside.
In a chip, a traditional RC oscillator adopts a comparator to control RC charge and discharge; the traditional current source type sawtooth wave oscillator adopts a current source and a current trap to charge and discharge a capacitor respectively, then sets a charge and discharge voltage threshold value through two paths of comparators, and realizes the charge and discharge switching through an SR trigger.
However, in the existing oscillator structure, comparators are used, and due to the delay of the comparators, the error is smaller when the output frequency is lower (for example, less than 1 MHz), but when the output frequency exceeds 10MHz, the delay of the comparators changes with temperature and voltage, and the output clock frequency error is larger.
Disclosure of Invention
The embodiment of the invention solves the technical problem of larger error caused by the change of the output clock frequency along with the change of temperature and voltage.
To solve the above technical problem, an embodiment of the present invention provides an oscillator, including: chopper voltage average value feedback circuit, RC charge-discharge circuit, threshold voltage detection circuit, ESR trigger control circuit, stable clock output circuit and chopper clock bootstrap circuit, wherein: the chopper voltage average value feedback circuit is characterized in that a first input end of the chopper voltage average value feedback circuit inputs a temperature drift calibration reference voltage, a second input end of the chopper voltage average value feedback circuit is coupled with a first voltage output end of the RC charge-discharge circuit, a clock signal input end of the chopper voltage average value feedback circuit is coupled with a clock signal output end of the chopper clock bootstrap circuit, and an enable signal input end of the chopper voltage average value feedback circuit is coupled with an enable signal output end of the chopper clock bootstrap circuit; the first input end and the second input end of the threshold voltage detection circuit are coupled with the output end of the chopper voltage average value feedback circuit, the third input end of the threshold voltage detection circuit is coupled with the second voltage output end of the RC charge-discharge circuit, and the fourth input end of the threshold voltage detection circuit is coupled with the third voltage output end of the RC charge-discharge circuit; the first input end of the RC charge-discharge circuit is coupled with the first output end of the ESR trigger control circuit, and the second input end of the RC charge-discharge circuit is coupled with the second output end of the ESR trigger control circuit; the first input end of the ESR trigger control circuit is coupled with the first output end of the threshold voltage detection circuit, the second input end of the ESR trigger control circuit is coupled with the second output end of the threshold voltage detection circuit, and the third input end of the ESR trigger control circuit inputs an enabling signal; the first input end of the stable clock output circuit is coupled with the second output end of the ESR trigger control circuit, the second input end of the stable clock output circuit is coupled with the first output end of the ESR trigger control circuit, the first output end of the stable clock output circuit outputs a first output clock signal, the second output end of the stable clock output circuit outputs a second output clock signal, and the third output end of the stable clock output circuit outputs a clock stability indication signal; the chopper clock bootstrap circuit has a clock signal input coupled to the second output of the stable clock output circuit and an enable signal input coupled to the third output of the stable clock output circuit.
Optionally, the chopper voltage average value feedback circuit includes: a chopper operational amplifier COA and an integrating loop, wherein: the first input end of the chopper operational amplifier COA inputs the temperature drift calibration reference voltage, the second input end of the chopper operational amplifier COA is coupled with the input end of the integrating circuit, and the output end of the chopper operational amplifier COA is coupled with the output end of the integrating circuit, the first input end of the threshold voltage detection circuit and the second input end of the chopper operational amplifier COA; and the input end of the integrating loop is coupled with the first voltage output end of the RC charge-discharge circuit.
Optionally, the integrating loop includes an integrating resistor Rx and an integrating capacitor Cx, where: the first end of the integrating resistor Rx is coupled with the first voltage output end of the RC charge-discharge circuit, and the second end of the integrating resistor Rx is coupled with the first end of the integrating capacitor Cx and the second input end of the chopper operational amplifier COA; the second end of the integrating capacitor Cx is coupled with the output end of the chopper operational amplifier COA.
Optionally, the chopper operational amplifier COA includes: the first chopper circuit, the second chopper circuit, the third chopper circuit, the first operational amplifier, the second operational amplifier, the third operational amplifier, the fourth operational amplifier, the noise band-stop filter and the output filter capacitor, wherein: the first operational amplifier, the second operational amplifier and the third operational amplifier are rail-to-rail differential input rail-to-rail differential output operational amplifiers, and the fourth operational amplifier is a rail-to-rail differential input rail-to-rail single-ended output operational amplifier, wherein: the first input end of the first chopper circuit is the first input end of the chopper operational amplifier COA, and the second input end of the first chopper circuit is the second input end of the chopper operational amplifier COA; the first operational amplifier has a first input end coupled with the first output end of the first chopper circuit and the first output end of the third operational amplifier, and a second input end coupled with the second output end of the first chopper circuit and the second output end of the third operational amplifier; the first input end of the second chopper circuit is coupled with the first output end of the first operational amplifier, and the second input end of the second chopper circuit is coupled with the second output end of the first operational amplifier; the first input end of the second operational amplifier is coupled with the first output end of the second chopper circuit, and the second input end of the second operational amplifier is coupled with the second output end of the second chopper circuit; the first input end of the third chopper circuit is coupled with the first output end of the second operational amplifier, and the second input end of the third chopper circuit is coupled with the second output end of the second operational amplifier; the first input end of the noise band-stop filter is coupled with the first output end of the third chopper circuit, and the second input end of the noise band-stop filter is coupled with the second output end of the third chopper circuit; the first input end of the third operational amplifier is coupled with the first output end of the noise band-stop filter, and the second input end of the third operational amplifier is coupled with the second output end of the noise band-stop filter; the first input end of the fourth operational amplifier is coupled with the first output end of the second chopper circuit, the second input end of the fourth operational amplifier is coupled with the second output end of the second chopper circuit, and the output end of the fourth operational amplifier is the output end of the chopper operational amplifier COA; the output filter capacitor is coupled between the second input end of the fourth operational amplifier and the output end of the fourth operational amplifier; the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band-stop filter all comprise enabling signal input ends and clock signal input ends, the enabling signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band-stop filter are all coupled with the enabling signal input ends of the chopper voltage average value feedback circuit, and the clock signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band-stop filter are all coupled with the clock signal input ends of the chopper voltage average value feedback circuit.
Optionally, the chopper clock bootstrap circuit includes: a first programmable counter, a first D flip-flop, a second D flip-flop, and a first inverter, wherein: the first programmable counter has a clock signal input end coupled with the second output end of the stable clock output circuit, an enable signal input end coupled with the third output end of the stable clock output circuit, a control end for inputting a first control signal, and an output end coupled with the clock signal input end of the first D trigger; the data end of the first D trigger is coupled with the output end of the first inverter, the output end of the first D trigger is coupled with the input end of the first inverter, the clock signal input end of the second D trigger and the clock signal input end of the chopper voltage average value feedback circuit, and the enabling end of the first D trigger is coupled with the third output end of the stable clock output circuit; and the data end of the second D trigger is input with a preset power supply voltage, the output end of the second D trigger is coupled with the enabling signal input end of the chopper voltage average value feedback circuit, and the enabling end of the second D trigger is coupled with the third output end of the stable clock output circuit.
Optionally, the threshold voltage detection circuit includes: a first comparator and a second comparator, wherein: the first input end of the first comparator is coupled with the output end of the chopper voltage average value feedback circuit, the second input end of the first comparator is coupled with the second voltage output end of the RC charge-discharge circuit, and the output end of the first comparator is coupled with the first input end of the ESR trigger control circuit; and the first input end of the second comparator is coupled with the output end of the chopper voltage average value feedback circuit, the second input end of the second comparator is coupled with the third voltage output end of the RC charge-discharge circuit, and the output end of the second comparator is coupled with the second input end of the ESR trigger control circuit.
Optionally, the ESR trigger control circuit includes: first NAND gate, second NAND gate and buffer, wherein: the first NAND gate has a first input end coupled to the first output end of the threshold voltage detection circuit, an enabling end coupled to the output end of the buffer, a second input end coupled to the output end of the second NAND gate, and an output end being the second output end of the ESR trigger control circuit; the first input end of the second NAND gate is coupled with the second output end of the threshold voltage detection circuit, the enabling end of the second NAND gate is coupled with the input end of the buffer, the second input end of the second NAND gate is coupled with the output end of the first NAND gate, and the output end of the second NAND gate is the first output end of the ESR trigger control circuit; the input end of the buffer inputs an enabling signal, and the output end of the buffer is further coupled with the enabling signal input end of the chopper clock bootstrap circuit.
Optionally, the stable clock output circuit includes: frequency stabilization indicating circuit, first AND gate and second AND gate, wherein: the input end of the frequency stability indicating circuit is coupled with the second output end of the ESR trigger control circuit, and the output end of the frequency stability indicating circuit is coupled with the first input end of the first AND gate, the first input end of the second AND gate and the enable signal input end of the chopper clock bootstrap circuit; the second input end of the first AND gate is coupled with the second output end of the ESR trigger control circuit, and the output end of the first AND gate outputs the first output clock signal; the second input end of the second AND gate is coupled with the first output end of the ESR trigger control circuit, and the output end of the second AND gate outputs the second output clock signal.
Optionally, the frequency stability indicating circuit includes: a second programmable counter, a third D flip-flop, a fourth D flip-flop, and a second inverter, wherein: the second programmable counter has an enable signal input end for inputting an enable signal, a clock signal input end for inputting the second control signal, and a control end coupled with the clock signal input end of the third D trigger; the data end of the third D flip-flop is coupled with the output end of the second inverter, the output end of the third D flip-flop is coupled with the input end of the second inverter and the clock signal input end of the fourth D flip-flop, and the enabling end of the third D flip-flop inputs the enabling signal; and the data end of the fourth D trigger is input with a preset power supply voltage, the output end of the fourth D trigger is the output end of the frequency stability indicating circuit, and the enabling end of the fourth D trigger is input with the enabling signal.
Optionally, the RC charge-discharge circuit includes: the first adjustable resistor, the second adjustable resistor, the first adjustable capacitor, the second adjustable capacitor, the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, wherein: the fixed end of the first switch circuit is coupled with the first end of the first adjustable resistor, and the control end of the first switch circuit is coupled with the second output end of the ESR trigger control circuit; the second end of the first adjustable resistor is coupled with the movable end of the fifth switching circuit, the fixed end of the second switching circuit and the first end of the first adjustable capacitor, and the second end of the first adjustable resistor is also coupled with the third input end of the threshold voltage detection circuit; the fixed end of the fifth switching circuit is coupled with the second end of the first adjustable capacitor, and the control end of the fifth switching circuit is coupled with the first output end of the ESR trigger control circuit; the second end of the first adjustable capacitor is coupled with the ground; the dynamic end of the second switch circuit is coupled with the first voltage output end of the RC charge-discharge circuit, and the control end of the second switch circuit is coupled with the second output end of the ESR trigger control circuit; the fixed end of the third switching circuit is coupled with the first end of the second adjustable resistor, and the control end of the third switching circuit is coupled with the first output end of the ESR trigger control circuit; the second end of the second adjustable resistor is coupled with the movable end of the sixth switching circuit, the fixed end of the fourth switching circuit and the first end of the second adjustable capacitor, and the second end of the second adjustable resistor is also coupled with the fourth input end of the threshold voltage detection circuit; the fixed end of the sixth switching circuit is coupled with the second end of the second adjustable capacitor, and the control end of the sixth switching circuit is coupled with the second output end of the ESR trigger control circuit; the second end of the second adjustable capacitor is coupled with the ground; and the moving end of the fourth switch circuit is coupled with the first voltage output end of the RC charge-discharge circuit, and the control end of the fourth switch circuit is coupled with the first output end of the ESR trigger control circuit.
Optionally, the temperature drift calibration reference voltage is generated by a temperature drift calibration reference voltage generating circuit and is output through an output end of the temperature drift calibration reference voltage generating circuit.
Optionally, the temperature drift calibration reference voltage generating circuit includes: PMOS current source, first NMOS current source, second NMOS current source to and third adjustable resistance, fourth adjustable resistance, fifth adjustable resistance and the sixth adjustable resistance of establishing ties in proper order, wherein: the first output end of the PMOS current source is coupled with the second end of the fifth adjustable resistor and the first end of the sixth adjustable resistor; the input end of the first NMOS current source is coupled with the second output end of the PMOS current source, and the output end of the first NMOS current source is coupled with the input end of the PMOS current source; the input end of the second NMOS current source is coupled with the third output end of the PMOS current source, and the output end of the second NMOS current source is coupled with the first end of the fourth adjustable resistor and the second end of the third adjustable resistor; the first end of the third adjustable resistor is input with a power supply voltage, and the second end of the third adjustable resistor is coupled with the first end of the fourth adjustable resistor; the second end of the fourth adjustable resistor is coupled with the first end of the fifth adjustable resistor and the output end of the NMOS current source, and is coupled with the output end of the temperature drift calibration reference voltage generation circuit; the first end of the fifth adjustable resistor is coupled with the output end of the temperature drift calibration reference voltage generation circuit, and the second end of the fifth adjustable resistor is coupled with the first end of the sixth adjustable resistor and the output end of the PMOS current source; the second end of the sixth adjustable resistor is grounded.
Optionally, the PMOS current source includes: the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube, wherein: the source electrode of the first PMOS tube inputs power supply voltage, the grid electrode of the first PMOS tube is coupled with the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is coupled with the input end of the first NMOS current source; the source electrode of the second PMOS tube inputs the power supply voltage, and the drain electrode of the second PMOS tube is coupled with the grid electrode of the second PMOS tube and the output end of the first NMOS current source; the source electrode of the third PMOS tube inputs the power supply voltage, the grid electrode of the third PMOS tube is coupled with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is coupled with the input end of the second NMOS current source; and the source electrode of the fourth PMOS tube is input with the power supply voltage, the grid electrode of the fourth PMOS tube is coupled with the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is the first output end of the PMOS current source.
Optionally, the first NMOS current source includes: the first NMOS transistor, the second NMOS transistor, the first PNP triode, the second PNP triode and the current resistor, wherein: the grid electrode of the first NMOS tube is coupled with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is coupled with the emitter electrode of the first PNP triode, and the drain electrode of the first NMOS tube is the input end of the first NMOS current source; the grid electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the output of the first NMOS current source, and the source electrode of the second NMOS tube is coupled with the first end of the current resistor; the second end of the current resistor is coupled with the emitter of the second PNP triode; the base electrode of the first PNP triode is coupled with the collector electrode of the first PNP triode and is grounded; and the base electrode and the collector electrode of the second PNP triode are coupled and grounded.
Optionally, the second NMOS current source includes: third NMOS pipe and fourth NMOS pipe, wherein: the grid electrode of the third NMOS tube is coupled with the drain electrode of the third NMOS tube, the third NMOS tube is an input end of the second NMOS current source, and the source electrode of the third NMOS tube is grounded; and the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube is the output end of the second NMOS current source, and the source electrode of the fourth NMOS tube is grounded.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the temperature drift calibration reference voltage generating circuit generates a temperature drift calibration reference voltage with a specific temperature coefficient, and the temperature drift calibration reference voltage generating circuit is matched with the chopper voltage average value feedback circuit with the self-calibration feedback loop to realize that the output clock frequency is irrelevant to temperature and voltage.
Further, the integration loop in the chopper voltage average value feedback circuit can eliminate high-frequency noise, and the delay time of the comparator in the chopper operational amplifier can be eliminated by the integration loop. The chopper operational amplifier is provided with a self-calibration feedback loop, so that the chopper noise can be restrained while the offset voltage and flicker noise are reduced, and the high-frequency phase noise of the oscillator can be restrained by a negative feedback structure, so that the sensitivity to the high-frequency power supply noise is low.
In addition, clock bootstrap of the chopper operational amplifier is realized through the chopper clock bootstrap circuit, and a clock signal with stable frequency can be provided.
Drawings
Fig. 1 is a schematic diagram of an oscillator according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a chopper operational amplifier in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of a frequency stability indicator circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a chopper clock bootstrap circuit in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a temperature drift calibration reference voltage generating circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a transmission characteristic of the output noise of an integrating loop in an embodiment of the present invention;
FIG. 7 is a schematic diagram of the transmission characteristics of an integrated loop phase noise in an embodiment of the present invention;
FIG. 8 is a schematic diagram of output noise of a conventional operational amplifier in an embodiment of the present invention;
FIG. 9 is a schematic diagram of output noise of a conventional chopper operational amplifier in accordance with an embodiment of the present invention;
FIG. 10 is a schematic diagram of the output noise of a chopper operational amplifier including a self-calibrating feedback loop in an embodiment of the present invention;
Fig. 11 is a schematic diagram of output noise of a chopper voltage average value feedback circuit in an embodiment of the invention.
Detailed Description
As can be seen from the above, in the conventional oscillator structure, the comparator is used, and the error is small when the output frequency is low (for example, less than 1 MHz) because of the delay of the comparator, but when the output frequency exceeds 10MHz, the delay of the comparator changes with temperature and voltage, and the output clock frequency error is large.
In the embodiment of the invention, the temperature drift calibration reference voltage with a specific temperature coefficient is generated through the temperature drift calibration reference voltage, and the output clock frequency is irrelevant to temperature and voltage by matching with the chopper voltage average value feedback circuit with the self-calibration feedback loop.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides an oscillator including: the chopper voltage average value feedback circuit 11, the RC charge-discharge circuit 12, the threshold voltage detection circuit 13, the ESR trigger control circuit 14, the stable clock output circuit 15, the chopper clock bootstrap circuit 16, and the temperature drift calibration reference voltage generation circuit 17.
In a specific implementation, a first input end of the chopper voltage average value feedback circuit 11 inputs a temperature drift calibration reference voltage, a second input end of the chopper voltage average value feedback circuit 11 is coupled with a first voltage output end of the RC charge-discharge circuit 12, a clock signal input end of the chopper voltage average value feedback circuit 11 is coupled with a clock signal output end of the chopper clock bootstrap circuit 16, and an enable signal input end of the chopper voltage average value feedback circuit 11 is coupled with an enable signal output end of the chopper clock bootstrap circuit 16;
The first input end and the second input end of the threshold voltage detection circuit 13 are coupled with the output end of the chopper voltage average value feedback circuit 11, the third input end of the threshold voltage detection circuit 13 is coupled with the second voltage output end of the RC charge-discharge circuit 12, and the fourth input end of the threshold voltage detection circuit 13 is coupled with the third voltage output end of the RC charge-discharge circuit 12;
A first input terminal of the RC charge-discharge circuit 12 is coupled to a first output terminal of the ESR trigger control circuit 14, and a second input terminal of the RC charge-discharge circuit 12 is coupled to a second output terminal of the ESR trigger control circuit 14;
a first input terminal of the ESR trigger control circuit 14 is coupled to a first output terminal of the threshold voltage detection circuit 13, and a second input terminal of the ESR trigger control circuit 14 is coupled to a second output terminal of the threshold voltage detection circuit 13; the input end EN is the input enable of the whole circuit and controls the on and off of the whole circuit.
The first input terminal of the stable clock output circuit 15 is coupled to the second output terminal of the ESR trigger control circuit 14, the second input terminal of the stable clock output circuit 15 is coupled to the first output terminal of the ESR trigger control circuit 14, the first output terminal of the stable clock output circuit 15 outputs the first output clock signal CLKOUTP, the second output terminal of the stable clock output circuit 15 outputs the second output clock signal CLKOUTN, and the third output terminal of the stable clock output circuit 15 outputs the clock stability indication signal CLKOK.
The clock signal input of the chopper clock bootstrap circuit 16 is coupled to the second output of the stable clock output circuit 15, and the enable signal input of the chopper clock bootstrap circuit 16 is coupled to the third output of the stable clock output circuit 15.
The specific structure of the above-described oscillator will be described in detail.
In a specific implementation, the chopper voltage average value feedback circuit 11 may include a chopper operational amplifier COA and an integrating loop.
In the embodiment of the present invention, a first input terminal of the chopper operational amplifier COA inputs the temperature drift calibration reference voltage, a second input terminal of the chopper operational amplifier COA is coupled to an input terminal of the integrating circuit, and an output terminal of the chopper operational amplifier COA is coupled to an output terminal of the integrating circuit, a first input terminal of the threshold voltage detecting circuit 13, and a second input terminal of the threshold voltage detecting circuit 13.
The input of the integrating circuit may also be coupled to a first voltage output of the RC charge-discharge circuit 12.
In an implementation, the integrating loop may include an integrating resistor Rx and an integrating capacitance Cx, wherein:
the first end of the integrating resistor Rx is coupled with the first voltage output end of the RC charge-discharge circuit 12, and the second end of the integrating circuit is coupled with the first end of the integrating capacitor Cx and the second input end of the chopper operational amplifier COA; the second terminal of the integrating capacitor Cx is coupled to the output terminal of the chopper operational amplifier COA.
In a specific application, the first end of the integrating resistor Rx may be an input end of the integrating loop, and the second end of the integrating capacitor Cx may be an output end of the integrating loop.
In a specific implementation, the first input terminal of the chopper operational amplifier COA may be its corresponding "+" input terminal, and the second input terminal of the chopper operational amplifier COA may be its corresponding "-" input terminal.
It will be appreciated that in practical applications the structure of the integrating loop is not limited to the examples described above.
The following describes the chopper operational amplifier COA provided in the embodiment of the present invention in detail. Referring to fig. 2, a schematic diagram of a chopper operational amplifier COA according to an embodiment of the present invention is shown.
In the embodiment of the present invention, the chopper operational amplifier COA may include a first chopper circuit CP1, a second chopper circuit CP2, a third chopper circuit CP3, a first operational amplifier A1, a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, a noise band-stop filter NF, and an output filter capacitor Cc, wherein:
The first input end of the first chopper circuit CP1 is the first input end of the chopper operational amplifier COA, and the second input end of the first chopper circuit CP1 is the second input end of the chopper operational amplifier COA;
The first operational amplifier A1 is a rail-to-rail differential input rail-to-rail differential output operational amplifier, a first input end of the first operational amplifier A1 is coupled with a first output end of the first chopper circuit CP1 and a first output end of the third operational amplifier A3, and a second input end of the first operational amplifier A1 is coupled with a second output end of the first chopper circuit CP1 and a second output end of the third operational amplifier A3;
a first input end of the second chopper circuit CP2 is coupled to a first output end of the first operational amplifier A1, and a second input end of the second chopper circuit CP2 is coupled to a second output end of the first operational amplifier A1;
The second operational amplifier A2 is a rail-to-rail differential input rail-to-rail differential output operational amplifier, a first input end of the second operational amplifier A2 is coupled with a first output end of the second chopper circuit CP2, and a second input end of the second operational amplifier A2 is coupled with a second output end of the second chopper circuit CP 2;
the first input end of the third chopper circuit CP3 is coupled to the first output end of the second operational amplifier A2, and the second input end of the third chopper circuit CP3 is coupled to the second output end of the second operational amplifier A2;
a first input end of the noise band-stop filter NF is coupled with a first output end of the third chopper circuit CP3, and a second input end of the noise band-stop filter NF is coupled with a second output end of the third chopper circuit CP 3;
the third operational amplifier A3 is a rail-to-rail differential input rail-to-rail differential output operational amplifier, a first input end of the third operational amplifier A3 is coupled with a first output end of the noise band-stop filter NF, and a second input end of the third operational amplifier A3 is coupled with a second output end of the noise band-stop filter NF;
the first input end of the fourth operational amplifier A4 is coupled with the first output end of the second chopper circuit CP2, the second input end of the fourth operational amplifier A4 is coupled with the second input end of the second chopper circuit CP2, and the output end of the fourth operational amplifier A4 is the output end of the chopper operational amplifier COA;
The output filter capacitor Cc is coupled between the second input terminal of the fourth operational amplifier A4 and the output terminal of the fourth operational amplifier A4.
In the embodiment of the present invention, the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3, and the noise band stop filter NF each include an enable signal input terminal and a clock signal input terminal, and: the enabling signal input ends of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3 and the noise band-stop filter NF are coupled with the enabling signal input end of the chopper voltage average value feedback circuit 11; the clock signal inputs of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3 and the noise band stop filter NF are coupled to the clock signal input of the chopper voltage average value feedback circuit 11.
In other words, the enable signals input to the enable signal input terminals of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3, and the noise band stop filter NF are the enable signal a en output from the enable signal output terminal of the chopper clock bootstrap circuit 16; the clock signals input to the clock signal input terminals of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3, and the noise band elimination filter NF are the clock signal a clk output from the clock signal output terminal of the chopper clock bootstrap circuit 16.
In the embodiment of the present invention, the first input terminal of the first operational amplifier A1 is a "+" input terminal thereof, the second input terminal of the first operational amplifier A1 is a "-" input terminal thereof, the first output terminal of the first operational amplifier A1 is a "+" output terminal thereof, and the second output terminal of the first operational amplifier A1 is a "-" output terminal thereof.
Correspondingly, for the second operational amplifier A2 and the third operational amplifier A3, the corresponding first input terminal is the "+" input terminal, the corresponding second input terminal is the "-" input terminal, the corresponding first output terminal is the "+" output terminal, and the corresponding second output terminal is the "-" output terminal.
For the fourth operational amplifier A4, its first input is its "+" input and its second input is its "-" input.
In fig. 2, the first input terminal of the chopper operational amplifier COA is INP, the second input terminal of the chopper operational amplifier COA is INN, and the output terminal of the chopper operational amplifier COA is Vout. In essence, when the chopper operational amplifier COA of fig. 2 is applied to fig. 1, the INP port is the "+" input terminal of the chopper operational amplifier COA, the INN port is the "-" input terminal of the chopper operational amplifier COA, and the voltage output by the Vout port is V Y.
The chopper operational amplifier COA adopting the structure comprises a self-calibration feedback loop, so that chopping ripple waves can be filtered. Flicker noise and offset voltage can be removed at low frequency, and high frequency noise can be filtered by the coupled integrating loop, so that the jitter of the output clock signal is small.
Referring to fig. 1, in an embodiment of the present invention, the RC charge-discharge circuit 12 may include a first adjustable resistor R1, a second adjustable resistor R2, a first adjustable capacitor C1, a second adjustable capacitor C2, and a first switch circuit K1, a second switch circuit K2, a third switch circuit K3, a fourth switch circuit K4, a fifth switch circuit K5, and a sixth switch circuit K6, wherein:
The power supply voltage VDD is input to the dynamic end of the first switch circuit K1, the fixed end of the first switch circuit K1 is coupled to the first end of the first adjustable resistor R1, and the control end of the first switch circuit K1 is coupled to the second output end of the ESR trigger control circuit 14;
the second end of the first adjustable resistor R1 is coupled with the movable end of the fifth switch circuit K5, the fixed end of the second switch circuit K2 and the first end of the first adjustable capacitor C1, and the second end of the first adjustable resistor R1 is also coupled with the third input end of the threshold voltage detection circuit 13; in other words, the second end of the first adjustable resistor R1 may be the second voltage output end of the RC charge-discharge circuit 12;
The fixed end of the fifth switching circuit K5 is coupled with the second end of the first adjustable capacitor C1, and the control end of the fifth switching circuit K5 is coupled with the first output end of the ESR trigger control circuit 14;
the second end of the first adjustable capacitor C1 is grounded, and the fixed end of the fifth switch circuit K5 is also grounded;
the dynamic end of the second switch circuit K2 is coupled with the first voltage output end of the RC charge-discharge circuit 12, and the control end of the second switch circuit K2 is coupled with the second output end of the ESR trigger control circuit 14;
the power supply voltage VDD is input to the movable end of the third switch circuit K3, the fixed end of the third switch circuit K3 is coupled to the first end of the second adjustable resistor R2, and the control end of the third switch circuit K3 is coupled to the first output end of the ESR trigger control circuit 14;
the second end of the second adjustable resistor R2 is coupled to the moving end of the sixth switching circuit K6, the fixed end of the fourth switching circuit K4, and the first end of the second adjustable capacitor C2, and the second end of the second adjustable resistor R2 is further coupled to the fourth input end of the threshold voltage detection circuit 13; in other words, the second end of the second adjustable resistor R2 may be the third voltage output end of the RC charge-discharge circuit 12;
A fixed end of the sixth switching circuit K6 may be coupled to the second end of the second adjustable capacitor C2, and a control end of the sixth switching circuit K6 is coupled to the second output end of the ESR trigger control circuit 14;
The second end of the second adjustable capacitor C2 is coupled with the ground, and the second end of the sixth switching circuit K6 is also grounded;
The dynamic end of the fourth switch circuit K4 is coupled to the first voltage output end of the RC charge-discharge circuit 12, and the control end of the fourth switch circuit K4 is coupled to the first output end of the ESR trigger control circuit 14.
In the embodiment of the present invention, the RC charge-discharge circuit 12 may be equivalent to a voltage-controlled oscillator using the output voltage of the chopper voltage average value feedback circuit 11 as a control signal. The voltage at the constant terminal of the second switch circuit K2 and the voltage at the constant terminal of the fourth switch circuit K4 are synthesized into the voltage output through the first voltage output terminal of the RC charge-discharge circuit 12, and input to the chopper voltage average value feedback circuit 11. Due to the characteristics of the weak short and the weak break, the voltage output by the first voltage output end of the RC charge-discharge circuit 12 is maintained near the temperature drift calibration reference voltage V REF.
Referring to fig. 1, the RC charge/discharge circuit 12 is indirectly controlled by the output V Y of the chopper voltage average value feedback circuit 11 as a control signal. The voltage V O1 at the constant terminal of the second switch circuit K2 and the voltage V O2 at the constant terminal of the fourth switch circuit K4 are synthesized into V X, and are input to the second input terminal of the chopper operational amplifier COA through the integration resistor Rx. V X remains near V REF due to the nature of the weak short and weak break.
Referring to fig. 1, in an implementation, the threshold voltage detection circuit 13 may include: a first comparator RCP1 and a second comparator RCP2, wherein:
A first input end of the first comparator RCP1 is coupled to an output end of the chopper voltage average value feedback circuit 11, a second input end of the first comparator RCP1 is coupled to a second voltage output end of the RC charge-discharge circuit 12, and an output end of the first comparator RCP1 is coupled to a first input end of the ESR trigger control circuit 14;
The first input terminal of the second comparator RCP2 is coupled to the output terminal of the chopper voltage average feedback circuit 11, the second input terminal of the second comparator RCP2 is coupled to the third voltage output terminal of the RC charge-discharge circuit 12, and the output terminal of the second comparator RCP2 is coupled to the second input terminal of the ESR trigger control circuit 14.
In the embodiment of the present invention, the first input terminal of the first comparator RCP1 may be the first input terminal of the threshold voltage detection circuit 13, the second input terminal of the first comparator RCP1 may be the second input terminal of the threshold voltage detection circuit 13, and the output terminal of the first comparator RCP1 may be the first output terminal of the threshold voltage detection circuit 13.
The first input terminal of the second comparator RCP2 may be a third input terminal of the threshold voltage detection circuit 13, the second input terminal of the second comparator RCP2 may be a fourth input terminal of the threshold voltage detection circuit 13, and the output terminal of the second comparator RCP2 may be a second output terminal of the threshold voltage detection circuit 13.
In an implementation, the first and second comparators RCP1 and RCP2 are complementary rail-to-rail input comparators.
In particular implementations, the ESR trigger control circuit 14 includes: a first NAND gate NAND1, a second NAND gate NAND2, and a buffer BUF, wherein:
a first input end of the first NAND gate NAND1 is coupled with a first output end of the threshold voltage detection circuit 13, an enabling end of the first NAND gate NAND1 is coupled with an output end of the buffer BUF, and a second input end of the first NAND gate NAND1 is coupled with an output end of the second NAND gate NAND 2; the output terminal of the first NAND gate NAND1 is the second output terminal CLKN of the ESR trigger control circuit 14;
The first input terminal of the second NAND gate NAND2 is coupled to the second output terminal of the threshold voltage detection circuit 13, the enable terminal of the second NAND gate NAND2 is coupled to the input terminal of the buffer BUF, the second input terminal of the second NAND gate NAND2 is coupled to the output terminal of the first NAND gate NAND1, and the output terminal of the second NAND gate NAND2 is the first output terminal CLKP of the ESR trigger control circuit 14.
The buffer BUF realizes a ns-level delay when EN is enabled, so that the ESR trigger control circuit is ensured to enter a normal working state.
In particular implementations, the stable clock output circuit 15 may include: a frequency stability indicating circuit 151, a first AND gate AND1, AND a second AND gate AND2, wherein:
An input terminal of the frequency stability indicating circuit 151 is coupled to a second output terminal of the ESR trigger control circuit 14, AND an output terminal of the frequency stability indicating circuit 151 is coupled to a first input terminal of the first AND gate AND1, a first input terminal of the second AND gate AND2, AND an enable signal input terminal of the chopper clock bootstrap circuit 16;
A second input terminal of the first AND gate AND1 is coupled to a second output terminal of the ESR trigger control circuit 14, AND an output terminal of the first AND gate AND1 outputs a first output clock signal CLKOUTP;
a second input of the second AND gate AND2 is coupled to the first output of the ESR trigger control circuit 14, AND an output of the second AND gate AND2 outputs a second output clock signal CLKOUTN.
In the embodiment of the present invention, the input terminal of the frequency stabilization indicating circuit 151 may be the first input terminal CLKN of the stabilization clock output circuit 15; the second input terminal of the second AND gate AND2 may be the second input terminal CLKP of the stable clock output circuit 15; the output terminal of the frequency stability indicating circuit 151 may be a third output terminal of the stable clock output circuit 15, for outputting a clock stability indicating signal CLKOK;
The output terminal of the first AND gate AND1 may be a first output terminal of the stable clock output circuit 15, for outputting the first output clock signal CLKOUTP;
the output terminal of the second AND gate AND2 may be a second output terminal of the stable clock output circuit 15 for outputting the second output clock signal CLKOUTN.
Referring to fig. 3, a schematic diagram of a frequency stability indicator circuit 151 according to an embodiment of the present invention is shown.
In an implementation, the frequency stability indicating circuit 151 may include: a second programmable counter, a third D flip-flop D3, a fourth D flip-flop D4, and a second inverter INV2, wherein:
The enable signal input end of the second programmable counter inputs the enable signal EN, the clock signal input end of the second programmable counter is the input end of the frequency stability indicating circuit 151, and the control end of the second programmable counter inputs the second control signal F <15:0>, the output end of the second programmable counter is coupled with the clock signal input end of the third D trigger D3;
The data end D of the third D trigger D3 is coupled with the output end of the second inverter INV2, the output end Q of the third D trigger D3 is coupled with the input end of the second inverter INV2 and the clock signal input end of the fourth D trigger D4, and the reset end input of the third D trigger D3 is an enable signal EN;
the data terminal D of the fourth D flip-flop D4 inputs the preset power voltage VDD, the output terminal Q of the fourth D flip-flop D4 is the output terminal of the frequency stabilization indicating circuit 151, and the reset terminal of the fourth D flip-flop D4 inputs the enable signal EN.
In the embodiment of the present invention, the second programmable counter may be a 16-bit programmable counter, wherein the input second control signal F <15:0> is the number of clock cycles of the delayed output clock stability indicator signal CLKOK. For the programmable counter with 16, the corresponding delay time ranges from 0 to 2 16 -1 cycles.
For example, the second control signal is 0x0003, and then the clock stability indicating signal CLKOK is output to the chopper-clock bootstrap circuit 16 after a delay of 3 cycles.
Referring to fig. 4, a schematic diagram of a chopper clock bootstrap circuit 16 in an embodiment of the present invention is provided.
In particular implementations, chopper clock bootstrap circuit 16 may include a first programmable counter, a first D flip-flop D1, a second D flip-flop, and a first inverter INV1, wherein:
the first clock signal input end of the first programmable counter is a second output clock signal CLKOUTN, the enabling signal input end of the first programmable counter is a clock stability indicating signal CLKOK, the control end of the first programmable counter inputs a first control signal, and the output end of the first programmable counter is coupled with the clock signal input end of the first D trigger D1;
The data end D of the first D trigger D1 is coupled with the output end of the first inverter INV1, the output end Q of the first D trigger D1 is coupled with the input end of the first inverter INV1, the clock signal input end of the second D trigger D2 and the clock signal input end of the chopper voltage average value feedback circuit 11, and the reset end of the first D trigger inputs a clock stability indication signal CLKOK;
the data terminal D of the second D flip-flop D2 inputs the preset power voltage VDD, the output terminal Q of the second D flip-flop D2 is coupled to the enable signal input terminal of the chopper voltage average value feedback circuit 11, and the reset terminal of the second D flip-flop D2 inputs the clock stability indication signal CLKOK.
In the embodiment of the present invention, the first clock signal input end of the first programmable counter may be the clock signal input end of the chopper clock bootstrap circuit 16, the enable signal input end of the first programmable counter may be the enable signal input end of the chopper clock bootstrap circuit 16, the output end Q of the first D flip-flop D1 may be the clock signal output end of the chopper clock bootstrap circuit 16, and the output clock signal a clk; the output Q of the second D flip-flop D2 may be an enable signal output of the chopper clock bootstrap circuit 16, outputting an enable signal a en.
In an implementation, the first programmable counter may be a 64-bit programmable counter, wherein the input first control signal (C <63:0 >) is a division ratio for dividing the input second output clock signal CLKOUTN.
In a specific implementation, the temperature drift calibration reference voltage may be generated by the temperature drift calibration reference voltage generation circuit 17.
Referring to fig. 5, a schematic diagram of a temperature drift calibration reference voltage generating circuit 17 according to an embodiment of the present invention is shown.
In an embodiment of the present invention, the temperature drift calibration reference voltage generation circuit 17 may include: PMOS current source, first NMOS current source, second NMOS current source to and third adjustable resistance R3, fourth adjustable resistance R4, fifth adjustable resistance R5 and sixth adjustable resistance R6 that establish ties in proper order, wherein:
the first output end of the PMOS current source is coupled with the second end of the fifth adjustable resistor R5 and the first end of the sixth adjustable resistor R6;
the input end of the first NMOS current source is coupled with the second output end of the PMOS current source, and the output end of the first NMOS current source is coupled with the input end of the PMOS current source;
the output end of the second NMOS current source is coupled with the first end of the fourth adjustable resistor R4 and the second end of the third adjustable resistor R3;
a first end of the third adjustable resistor R3 is input with a power supply voltage, and a second end of the third adjustable resistor R3 is coupled with a first end of the fourth adjustable resistor R4;
The second end of the fourth adjustable resistor R4 is coupled with the first end of the fifth adjustable resistor R5 and the output end of the NMOS current source, and is coupled with the output end of the temperature drift calibration reference voltage generating circuit;
A first end of the fifth adjustable resistor R5 is coupled with the output end of the temperature drift calibration reference voltage generating circuit, and a second end of the fifth adjustable resistor R6 is coupled with the first end of the sixth adjustable resistor R6 and the output end of the PMOS current source;
And a sixth adjustable resistor R6, the second end of which is grounded.
In an implementation, the PMOS current source may include: the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4, wherein:
The source electrode of the first PMOS tube MP1 inputs power supply voltage, the grid electrode of the first PMOS tube MP2 is coupled with the grid electrode of the second PMOS tube MP2, the drain electrode of the second PMOS tube MP2 is coupled with the input end of the first NMOS current source;
The source electrode of the second PMOS tube MP2 inputs power supply voltage, and the drain electrode of the second PMOS tube MP2 is coupled with the grid electrode of the second PMOS tube and the output end of the first NMOS current source;
The source electrode of the third PMOS tube MP3 inputs power supply voltage, the grid electrode of the third PMOS tube MP3 is coupled with the grid electrode of the first PMOS tube MP1 and the grid electrode of the second PMOS tube MP2, and the drain electrode of the third PMOS tube MP3 is coupled with the input end of the second NMOS current source;
The source electrode of the fourth PMOS tube MP4 inputs power supply voltage, the grid electrode of the fourth PMOS tube MP4 is coupled with the grid electrode of the first PMOS tube MP1, the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3, and the drain electrode of the fourth PMOS tube MP3 is the first output end of the PMOS current source.
In an implementation, the first NMOS current source may include: the first NMOS transistor MN1, the second NMOS transistor MN2, the first PNP transistor Q1, the second PNP transistor Q2, and the current resistor R PTAT, wherein:
The grid electrode of the first NMOS tube MN1 is coupled with the drain electrode of the first NMOS tube MN1, the source electrode of the first NMOS tube MN1 is coupled with the emitter electrode of the first PNP triode Q1, and the drain electrode of the first NMOS tube MN1 is the input end of a first NMOS current source;
The grid electrode of the second NMOS tube MN2 is coupled with the grid electrode of the first NMOS tube MN1, the drain electrode of the second NMOS tube MN2 is connected with the output of the first NMOS current source, and the source electrode of the second NMOS tube MN2 is coupled with the first end of the current resistor R PTAT;
A second end of the current resistor R PTAT is coupled with the emitter of the second PNP triode Q2;
The base electrode of the first PNP triode Q1 is coupled with the collector electrode of the first PNP triode Q1 and is grounded;
and the base electrode of the second PNP triode Q2 is coupled with the collector electrode of the second PNP triode Q and is grounded.
In an implementation, the second NMOS current source may include: a third NMOS transistor MN3 and a fourth NMOS transistor MN4, wherein:
The gate of the third NMOS transistor MN3 is coupled with the drain thereof, and is an input end of the second NMOS current source, and the source thereof is grounded; the gate of the fourth NMOS MN4 is coupled to the gate of the third NMOS MN3, the drain is the output terminal of the second NMOS current source, and the source is grounded.
It will be appreciated that the specific structure of the PMOS current source may not be limited to the above example, nor the specific structure of the NMOS current source.
In the embodiment of the present invention, by adjusting the resistance values of the third to sixth adjustable resistors and the number ratio of the first PNP transistor to the second PNP transistor, the temperature drift coefficient of the temperature drift calibration reference voltage output by the temperature drift calibration reference voltage generating circuit 17 can be adjusted, so that the output frequency of the temperature drift calibration reference voltage is adjusted to be independent of temperature.
The operation principle of the oscillator provided in the above-described embodiment of the present invention will be described in detail.
The temperature drift calibration reference voltage V REF has a voltage division ratio of α, α=vdd/V REF.VREF, and the first adjustable resistor, the second adjustable resistor, the first adjustable capacitor and the second adjustable capacitor in the RC charge-discharge circuit 12 determine the frequency of the output clock signal. In the chopper voltage average value feedback circuit 11, the integration capacitance Cx and the integration resistance Rx of the integration loop determine the noise performance of the output clock signal.
The RC charge-discharge circuit 12 may be equivalently a voltage controlled oscillator with V Y as a control signal.
According to the virtual short and virtual break of the chopper operational amplifier COA, the integral loop is solved to obtain:
The integration of the two sides of the above formula (2.1) can be obtained:
the simplification of the above formula (2.2) can be obtained:
When the oscillator is in steady state, V Y (0) in the above equation (2.3) determines the steady state dc component of the output, the ac component is 0, and therefore:
The simplification of the above formula (2.4) can be obtained:
when there is a periodic steady state with T as the period,
Thus, a relationship between the steady-state integration period and the temperature drift calibration reference voltage is established. As can be seen from the above equation (2.6), the steady-state integration period of the integration loop is independent of the electrical parameters of the integration resistor Rx and the electrical parameters of the integration capacitor Cx.
Since the first adjustable resistor and the second adjustable resistor in the RC charge-discharge circuit 12 directly input the power voltage, the first adjustable capacitor and the second adjustable capacitor are grounded, and then:
V O1,2(t)＝Vdd(1-e-t/RC) (2.7) in the chopper voltage average value feedback circuit 11, there are
Substituting the formula (2.7) into the formula (2.8), and simplifying to obtain the compound:
R in the above formula (2.9) refers to the resistance values of the first adjustable resistor and the second adjustable resistor in the RC charge-discharge circuit 12, and C refers to the capacitance values of the first adjustable capacitor and the second adjustable capacitor in the RC charge-discharge circuit 12.
The chopper voltage average value feedback circuit 11 implements the condition in the above equation (2.9), and V Y can be automatically adjusted to maintain a stable frequency output, so as to be insensitive to the power supply voltage VDD and transmission delay. After the voltage division ratio is set, the electrical parameters of the first adjustable resistor, the first adjustable capacitor, the second adjustable resistor and the second adjustable capacitor can be adjusted to obtain specific output frequency.
As described above, RC charge-discharge circuit 12 may be equivalently a voltage-controlled oscillator, and defines a frequency gain of K VCO, vn to represent a noise spectrum contributed by devices such as chopper operational amplifier COA, and the periodic integral of Vx is equal to the input voltage Vx multiplied by the scaling factor β associated with the process of chopper operational amplifier COA. Because the chopping characteristics of the chopper op-amp COA are in the loop, its noise will be filtered out by its self-calibrating feedback loop.
The output noise of the integrating loop is:
the phase noise of the integrating loop is:
Wherein A is the gain of the chopper operational amplifier COA, s is the Laplara coefficient, and phi n in (2.11) is the system phase noise spectrum.
The pole-zero is as follows:
where f z is the first zero, f p1 is the first pole, and f p2 is the second pole.
The transmission characteristics of the integrated loop output noise are shown in fig. 6, and the transmission characteristics of the phase noise are shown in fig. 7. In fig. 6, the abscissa is log frequency log (freq), and the ordinate is output noise transmission characteristic phi out/Vn. In fig. 7, the abscissa represents the logarithmic frequency log (freq), and the ordinate represents the phase noise transmission characteristic phi out/φn. The output noise is small at high frequencies.
As can be seen from fig. 6, after the frequency exceeds the second point, the output noise of the integrating loop drops sharply. As can be seen from fig. 7, the phase noise increases with frequency when the frequency is between the first zero point and the second point. At frequencies less than the second pole, the phase noise is stable and at low frequencies the phase noise is less.
Referring to fig. 8, a schematic diagram of output noise of a conventional operational amplifier is given. Referring to fig. 9, a schematic diagram of output noise of a common chopper operational amplifier COA is given. Referring to fig. 10, a schematic diagram of the output noise of a chopper operational amplifier COA including a self-calibrating feedback loop is presented. Referring to fig. 11, a schematic diagram of output noise of a chopper voltage average value feedback circuit 11 in an embodiment of the present invention is given.
In fig. 8 to 11, the abscissa represents the logarithmic frequency log (freq), the ordinate represents the noise figure NF, and f c represents the chopping frequency of the chopping voltage average value feedback circuit.
As can be seen from fig. 8 to 11, the output noise of the chopper voltage average value feedback circuit provided in the embodiment of the invention has no flicker noise, and only includes low-pass thermal noise with a cutoff frequency f p2.
Therefore, the chopper voltage average value feedback circuit provided in the embodiment of the invention can inhibit low-frequency phase noise in the RC charge-discharge circuit 12, and small-size transistors can be used in the first comparator and the second comparator to reduce power consumption. In the chopper voltage average value feedback circuit, the flicker noise of the chopper operational amplifier COA can be filtered by the feedback loop, so that the chopper operational amplifier COA with small size can be selected to reduce the circuit area. The high frequency noise is eliminated and thus the sensitivity to the high frequency noise is low.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. An oscillator is provided, which comprises a first oscillator and a second oscillator, characterized by comprising the following steps: chopper voltage average value feedback circuit, RC charge-discharge circuit, threshold voltage detection circuit, ESR trigger control circuit, stable clock output circuit and chopper clock bootstrap circuit, wherein:
The chopper voltage average value feedback circuit is characterized in that a first input end of the chopper voltage average value feedback circuit inputs a temperature drift calibration reference voltage, a second input end of the chopper voltage average value feedback circuit is coupled with a first voltage output end of the RC charge-discharge circuit, a clock signal input end of the chopper voltage average value feedback circuit is coupled with a clock signal output end of the chopper clock bootstrap circuit, and an enable signal input end of the chopper voltage average value feedback circuit is coupled with an enable signal output end of the chopper clock bootstrap circuit;
The first input end and the second input end of the threshold voltage detection circuit are coupled with the output end of the chopper voltage average value feedback circuit, the third input end of the threshold voltage detection circuit is coupled with the second voltage output end of the RC charge-discharge circuit, and the fourth input end of the threshold voltage detection circuit is coupled with the third voltage output end of the RC charge-discharge circuit;
The first input end of the RC charge-discharge circuit is coupled with the first output end of the ESR trigger control circuit, and the second input end of the RC charge-discharge circuit is coupled with the second output end of the ESR trigger control circuit;
the first input end of the ESR trigger control circuit is coupled with the first output end of the threshold voltage detection circuit, the second input end of the ESR trigger control circuit is coupled with the second output end of the threshold voltage detection circuit, and the third input end of the ESR trigger control circuit inputs an enabling signal;
The first input end of the stable clock output circuit is coupled with the second output end of the ESR trigger control circuit, the second input end of the stable clock output circuit is coupled with the first output end of the ESR trigger control circuit, the first output end of the stable clock output circuit outputs a first output clock signal, the second output end of the stable clock output circuit outputs a second output clock signal, and the third output end of the stable clock output circuit outputs a clock stability indication signal;
The chopper clock bootstrap circuit has a clock signal input coupled to the second output of the stable clock output circuit and an enable signal input coupled to the third output of the stable clock output circuit.
2. The oscillator of claim 1, wherein the chopper voltage average feedback circuit comprises: a chopper operational amplifier COA and an integrating loop, wherein:
The first input end of the chopper operational amplifier COA inputs the temperature drift calibration reference voltage, the second input end of the chopper operational amplifier COA is coupled with the input end of the integration loop, and the output end of the chopper operational amplifier COA is coupled with the output end of the integration loop, the first input end of the threshold voltage detection circuit and the second input end of the chopper operational amplifier COA;
and the input end of the integrating loop is coupled with the first voltage output end of the RC charge-discharge circuit.
3. The oscillator of claim 2, wherein the integration loop comprises an integration resistor Rx and an integration capacitance Cx, wherein:
the first end of the integrating resistor Rx is coupled with the first voltage output end of the RC charge-discharge circuit, and the second end of the integrating resistor Rx is coupled with the first end of the integrating capacitor Cx and the second input end of the chopper operational amplifier COA;
the second end of the integrating capacitor Cx is coupled with the output end of the chopper operational amplifier COA.
4. The oscillator of claim 2, wherein the chopper operational amplifier COA comprises: the first chopper circuit, the second chopper circuit, the third chopper circuit, the first operational amplifier, the second operational amplifier, the third operational amplifier, the fourth operational amplifier, the noise band-stop filter and the output filter capacitor, wherein: the first operational amplifier, the second operational amplifier and the third operational amplifier are rail-to-rail differential input rail-to-rail differential output operational amplifiers, and the fourth operational amplifier is a rail-to-rail differential input rail-to-rail single-ended output operational amplifier, wherein:
The first input end of the first chopper circuit is the first input end of the chopper operational amplifier COA, and the second input end of the first chopper circuit is the second input end of the chopper operational amplifier COA;
the first operational amplifier has a first input end coupled with the first output end of the first chopper circuit and the first output end of the third operational amplifier, and a second input end coupled with the second output end of the first chopper circuit and the second output end of the third operational amplifier;
The first input end of the second chopper circuit is coupled with the first output end of the first operational amplifier, and the second input end of the second chopper circuit is coupled with the second output end of the first operational amplifier;
The first input end of the second operational amplifier is coupled with the first output end of the second chopper circuit, and the second input end of the second operational amplifier is coupled with the second output end of the second chopper circuit;
The first input end of the third chopper circuit is coupled with the first output end of the second operational amplifier, and the second input end of the third chopper circuit is coupled with the second output end of the second operational amplifier;
The first input end of the noise band-stop filter is coupled with the first output end of the third chopper circuit, and the second input end of the noise band-stop filter is coupled with the second output end of the third chopper circuit;
The first input end of the third operational amplifier is coupled with the first output end of the noise band-stop filter, and the second input end of the third operational amplifier is coupled with the second output end of the noise band-stop filter;
The first input end of the fourth operational amplifier is coupled with the first output end of the second chopper circuit, the second input end of the fourth operational amplifier is coupled with the second output end of the second chopper circuit, and the output end of the fourth operational amplifier is the output end of the chopper operational amplifier COA;
the output filter capacitor is coupled between the second input end of the fourth operational amplifier and the output end of the fourth operational amplifier;
The first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band-stop filter all comprise enabling signal input ends and clock signal input ends, the enabling signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band-stop filter are all coupled with the enabling signal input ends of the chopper voltage average value feedback circuit, and the clock signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band-stop filter are all coupled with the clock signal input ends of the chopper voltage average value feedback circuit.
5. The oscillator of claim 1, wherein the chopper clock bootstrap circuit comprises: a first programmable counter, a first D flip-flop, a second D flip-flop, and a first inverter, wherein: the first programmable counter has a clock signal input end coupled with the second output end of the stable clock output circuit, an enable signal input end coupled with the third output end of the stable clock output circuit, a control end for inputting a first control signal, and an output end coupled with the clock signal input end of the first D trigger;
The data end of the first D trigger is coupled with the output end of the first inverter, the output end of the first D trigger is coupled with the input end of the first inverter, the clock signal input end of the second D trigger and the clock signal input end of the chopper voltage average value feedback circuit, and the enabling end of the first D trigger is coupled with the third output end of the stable clock output circuit;
And the data end of the second D trigger is input with a preset power supply voltage, the output end of the second D trigger is coupled with the enabling signal input end of the chopper voltage average value feedback circuit, and the enabling end of the second D trigger is coupled with the third output end of the stable clock output circuit.
6. The oscillator of claim 1, wherein the threshold voltage detection circuit comprises: a first comparator and a second comparator, wherein:
The first input end of the first comparator is coupled with the output end of the chopper voltage average value feedback circuit, the second input end of the first comparator is coupled with the second voltage output end of the RC charge-discharge circuit, and the output end of the first comparator is coupled with the first input end of the ESR trigger control circuit;
And the first input end of the second comparator is coupled with the output end of the chopper voltage average value feedback circuit, the second input end of the second comparator is coupled with the third voltage output end of the RC charge-discharge circuit, and the output end of the second comparator is coupled with the second input end of the ESR trigger control circuit.
7. The oscillator of claim 1, wherein the ESR trigger control circuit comprises: first NAND gate, second NAND gate and buffer, wherein:
the first NAND gate has a first input end coupled to the first output end of the threshold voltage detection circuit, an enabling end coupled to the output end of the buffer, a second input end coupled to the output end of the second NAND gate, and an output end being the second output end of the ESR trigger control circuit;
the first input end of the second NAND gate is coupled with the second output end of the threshold voltage detection circuit, the enabling end of the second NAND gate is coupled with the input end of the buffer, the second input end of the second NAND gate is coupled with the output end of the first NAND gate, and the output end of the second NAND gate is the first output end of the ESR trigger control circuit;
The input end of the buffer inputs an enabling signal, and the output end of the buffer is further coupled with the enabling signal input end of the chopper clock bootstrap circuit.
8. The oscillator of claim 1, wherein the stable clock output circuit comprises: frequency stabilization indicating circuit, first AND gate and second AND gate, wherein:
The input end of the frequency stability indicating circuit is coupled with the second output end of the ESR trigger control circuit, and the output end of the frequency stability indicating circuit is coupled with the first input end of the first AND gate, the first input end of the second AND gate and the enable signal input end of the chopper clock bootstrap circuit;
the second input end of the first AND gate is coupled with the second output end of the ESR trigger control circuit, and the output end of the first AND gate outputs the first output clock signal;
The second input end of the second AND gate is coupled with the first output end of the ESR trigger control circuit, and the output end of the second AND gate outputs the second output clock signal.
9. The oscillator of claim 8, wherein the frequency stability indicating circuit comprises: a second programmable counter, a third D flip-flop, a fourth D flip-flop, and a second inverter, wherein: the second programmable counter has an enable signal input end for inputting an enable signal, a clock signal input end for inputting the second control signal, and a control end coupled with the clock signal input end of the third D trigger;
the data end of the third D flip-flop is coupled with the output end of the second inverter, the output end of the third D flip-flop is coupled with the input end of the second inverter and the clock signal input end of the fourth D flip-flop, and the enabling end of the third D flip-flop inputs the enabling signal;
and the data end of the fourth D trigger is input with a preset power supply voltage, the output end of the fourth D trigger is the output end of the frequency stability indicating circuit, and the enabling end of the fourth D trigger is input with the enabling signal.
10. The oscillator of claim 1, wherein the RC charge-discharge circuit comprises: the first adjustable resistor, the second adjustable resistor, the first adjustable capacitor, the second adjustable capacitor, the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, wherein:
the fixed end of the first switch circuit is coupled with the first end of the first adjustable resistor, and the control end of the first switch circuit is coupled with the second output end of the ESR trigger control circuit;
the second end of the first adjustable resistor is coupled with the movable end of the fifth switching circuit, the fixed end of the second switching circuit and the first end of the first adjustable capacitor, and the second end of the first adjustable resistor is also coupled with the third input end of the threshold voltage detection circuit;
The fixed end of the fifth switching circuit is coupled with the second end of the first adjustable capacitor, and the control end of the fifth switching circuit is coupled with the first output end of the ESR trigger control circuit;
The second end of the first adjustable capacitor is coupled with the ground;
The dynamic end of the second switch circuit is coupled with the first voltage output end of the RC charge-discharge circuit, and the control end of the second switch circuit is coupled with the second output end of the ESR trigger control circuit;
The fixed end of the third switching circuit is coupled with the first end of the second adjustable resistor, and the control end of the third switching circuit is coupled with the first output end of the ESR trigger control circuit;
the second end of the second adjustable resistor is coupled with the movable end of the sixth switching circuit, the fixed end of the fourth switching circuit and the first end of the second adjustable capacitor, and the second end of the second adjustable resistor is also coupled with the fourth input end of the threshold voltage detection circuit;
The fixed end of the sixth switching circuit is coupled with the second end of the second adjustable capacitor, and the control end of the sixth switching circuit is coupled with the second output end of the ESR trigger control circuit;
the second end of the second adjustable capacitor is coupled with the ground;
And the moving end of the fourth switch circuit is coupled with the first voltage output end of the RC charge-discharge circuit, and the control end of the fourth switch circuit is coupled with the first output end of the ESR trigger control circuit.
11. The oscillator of claim 1, wherein the temperature drift calibration reference voltage is generated by a temperature drift calibration reference voltage generation circuit and output via an output of the temperature drift calibration reference voltage generation circuit.
12. The oscillator of claim 11, wherein the temperature drift calibration reference voltage generation circuit comprises: PMOS current source, first NMOS current source, second NMOS current source to and third adjustable resistance, fourth adjustable resistance, fifth adjustable resistance and the sixth adjustable resistance of establishing ties in proper order, wherein:
the first output end of the PMOS current source is coupled with the second end of the fifth adjustable resistor and the first end of the sixth adjustable resistor;
The input end of the first NMOS current source is coupled with the second output end of the PMOS current source, and the output end of the first NMOS current source is coupled with the input end of the PMOS current source;
The output end of the second NMOS current source is coupled with the first end of the fourth adjustable resistor and the second end of the third adjustable resistor;
The first end of the third adjustable resistor is input with a power supply voltage, and the second end of the third adjustable resistor is coupled with the first end of the fourth adjustable resistor;
The second end of the fourth adjustable resistor is coupled with the first end of the fifth adjustable resistor and the output end of the NMOS current source, and is coupled with the output end of the temperature drift calibration reference voltage generation circuit;
The first end of the fifth adjustable resistor is coupled with the output end of the temperature drift calibration reference voltage generation circuit, and the second end of the fifth adjustable resistor is coupled with the first end of the sixth adjustable resistor and the output end of the PMOS current source;
the second end of the sixth adjustable resistor is grounded.
13. The oscillator of claim 12, wherein the PMOS current source comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube, wherein: the source electrode of the first PMOS tube inputs power supply voltage, the grid electrode of the first PMOS tube is coupled with the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is coupled with the input end of the first NMOS current source;
The source electrode of the second PMOS tube inputs the power supply voltage, and the drain electrode of the second PMOS tube is coupled with the grid electrode of the second PMOS tube and the output end of the first NMOS current source;
the source electrode of the third PMOS tube inputs the power supply voltage, the grid electrode of the third PMOS tube is coupled with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is coupled with the input end of the second NMOS current source;
and the source electrode of the fourth PMOS tube is input with the power supply voltage, the grid electrode of the fourth PMOS tube is coupled with the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is the first output end of the PMOS current source.
14. The oscillator of claim 12, wherein the first NMOS current source comprises: the first NMOS transistor, the second NMOS transistor, the first PNP triode, the second PNP triode and the current resistor, wherein:
The grid electrode of the first NMOS tube is coupled with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is coupled with the emitter electrode of the first PNP triode, and the drain electrode of the first NMOS tube is the input end of the first NMOS current source; the grid electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the output of the first NMOS current source, and the source electrode of the second NMOS tube is coupled with the first end of the current resistor;
The second end of the current resistor is coupled with the emitter of the second PNP triode;
the base electrode of the first PNP triode is coupled with the collector electrode of the first PNP triode and is grounded;
and the base electrode and the collector electrode of the second PNP triode are coupled and grounded.
15. The oscillator of claim 12, wherein the second NMOS current source comprises: third NMOS pipe and fourth NMOS pipe, wherein:
the grid electrode of the third NMOS tube is coupled with the drain electrode of the third NMOS tube, the third NMOS tube is an input end of the second NMOS current source, and the source electrode of the third NMOS tube is grounded;
And the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube is the output end of the second NMOS current source, and the source electrode of the fourth NMOS tube is grounded.
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