CN112713226A - Edge passivation method of HJT battery - Google Patents
Edge passivation method of HJT battery Download PDFInfo
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- CN112713226A CN112713226A CN202110024216.1A CN202110024216A CN112713226A CN 112713226 A CN112713226 A CN 112713226A CN 202110024216 A CN202110024216 A CN 202110024216A CN 112713226 A CN112713226 A CN 112713226A
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- 238000002161 passivation Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 68
- 230000008021 deposition Effects 0.000 claims abstract description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 47
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 11
- 238000012360 testing method Methods 0.000 claims abstract description 10
- 238000004806 packaging method and process Methods 0.000 claims abstract description 9
- 238000005520 cutting process Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 16
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000006872 improvement Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an edge passivation method of an HJT battery, which comprises the following steps: (1) slicing the whole HJT battery to obtain a HJT battery slice; (2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box; (3) placing the wafer box into PECVD equipment, and depositing on the edge of the HJT cell to form an intrinsic amorphous silicon layer; (4) sorting, testing and packaging the HJT battery piece; wherein, in the step (3), the deposition temperature for depositing the intrinsic amorphous silicon layer is 180-230 ℃, and the deposition time is 20-200 s. The method has the advantages of simple operation and high production efficiency, and can realize the edge passivation of the HJT battery to obtain the HJT battery with good passivation effect and high conversion efficiency.
Description
Technical Field
The invention relates to the technical field of HJT batteries, in particular to an edge passivation method of an HJT battery.
Background
The HJT cell is made by depositing an amorphous silicon thin film on crystalline silicon, belongs to one of N-type cells, and the structure of the HJT cell can improve the performance of a PN junction, so that the conversion efficiency and the open-circuit voltage are improved.
Before the HJT battery is prepared into a component, generally, the whole HJT battery needs to be divided by laser scribing and splitting to obtain independent HJT battery pieces; laser scribing can cause certain defect to the edge of the HJT battery piece, a composite center is formed, and due to the fact that the silicon substrate of the laser scribing is not covered by the passivation layer, the composite of a cutting surface is serious, and efficiency loss of more than 0.3% can be brought to the HJT battery usually.
However, the conventional edge passivation method requires a long-time deposition at a high temperature to form a passivation layer, and the high temperature causes the structure of the amorphous silicon thin film of the HJT cell to be damaged, thereby greatly reducing the passivation effect of the HJT cell, and thus the prior art cannot realize the edge passivation of the HJT cell.
Disclosure of Invention
The invention aims to solve the technical problem of providing an edge passivation method of an HJT battery, which has the advantages of simple and convenient operation and high production efficiency and can realize the edge passivation of the HJT battery.
In order to achieve the technical effects, the invention provides an edge passivation method of an HJT battery, which comprises the following steps:
(1) slicing the whole HJT battery to obtain a HJT battery slice;
(2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
(3) placing the wafer box into PECVD equipment, and depositing on the edge of the HJT cell to form an intrinsic amorphous silicon layer;
(4) sorting, testing and packaging the HJT battery piece;
wherein, in the step (3), the deposition temperature for depositing the intrinsic amorphous silicon layer is 180-230 ℃, and the deposition time is 20-200 s.
As an improvement of the above, SiH was introduced under 3Torr4And H2And depositing an intrinsic amorphous silicon layer at the edge of the HJT cell slice.
As an improvement on the above, the SiH4The gas flow rate of (1) is 300-2400sccm, and the gas flow rate of (H) is H2The gas flow rate of (1) is 3000-.
As an improvement of the scheme, in the step (1), the HJT battery is sliced by adopting laser scribing and mechanical splitting to obtain a plurality of independent HJT battery slices; the HJT cell segment has at least one cutting face.
As an improvement of the above scheme, the HJT cells in the cell stack are placed in the same direction, and the cutting surface of each HJT cell is placed upward; the upward cutting surfaces are all in the same plane to form a deposition surface of the cell stack; the HJT battery pieces are tightly stacked.
As an improvement of the above scheme, the cell stack is vertically placed in a wafer box, and the deposition surface faces upwards; the height of the deposition surface is less than or equal to the height of the upper end surface of the wafer box.
As an improvement of the scheme, the deposition thickness of the intrinsic amorphous silicon layer is 10-50 nm.
As a modification of the scheme, the cell stack comprises 10-500 HJT cell plates.
As an improvement of the scheme, the wafer box is made of high-temperature resistant materials.
Correspondingly, the invention discloses the HJT battery prepared by the method.
The implementation of the invention has the following beneficial effects:
the intrinsic amorphous silicon layer is deposited on the edge of the HJT cell piece by adopting PECVD equipment, the deposition temperature for depositing the intrinsic amorphous silicon layer is low, the deposition time is short, the problem that the passivation effect of the HJT cell is influenced because the structure of the amorphous silicon layer in the HJT cell piece is damaged by high temperature can be avoided, and the conversion efficiency of the HJT cell piece is improved; the intrinsic amorphous silicon layer has an efficient passivation effect, can introduce hydrogen atoms to repair defects formed by laser, and greatly reduces the HJT cell edge recombination caused by the laser, so that the HJT cell efficiency and the component power loss caused by laser slicing are reduced, and the conversion efficiency of the HJT cell is improved.
The method comprises the steps of stacking HJT battery pieces to form a battery stack, wherein any cutting surface of each HJT battery piece is placed upwards to form a deposition surface of the battery stack; and stacking the cells into a wafer box, wherein the deposition surface faces upwards, so that the deposition of the deposition surface is realized, and the edge intrinsic amorphous silicon layer is formed. Because a plurality of HJT battery pieces can be placed in the box, the HJT battery pieces can be deposited at one time, the production efficiency is effectively improved, and the yield is improved. In addition, the spool box can effectively protect the HJT battery piece, can reduce the mechanical fish tail and the contact pollution to the HJT battery piece.
In the invention, the height of the deposition surface is less than or equal to the height of the upper end surface of the wafer box, so that the influence on the front and back surfaces of the HJT cell piece can be avoided when the intrinsic amorphous silicon layer is deposited on the cutting surface of the HJT cell piece. The intrinsic amorphous silicon layer deposited and formed at the edge does not influence the light absorption of the HJT cell piece, and the short wave effect of the cell is not reduced due to the excessively thick thickness; therefore, when the intrinsic amorphous silicon layer is deposited subsequently, the deposition thickness can be set to be thicker, so that the intrinsic amorphous silicon layer with stronger passivation effect can be obtained.
The method has the advantages of simple operation and high production efficiency, and can realize the edge passivation of the HJT battery to obtain the HJT battery with good passivation effect and high conversion efficiency.
Drawings
FIG. 1 is a flow chart of the method of edge passivation of an HJT cell of the present invention;
FIG. 2 is a schematic diagram of the structure of a cell stack of the present invention;
fig. 3 is a schematic view showing the structure of a cell stack cassette according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, the present invention provides an edge passivation method for an HJT cell, including:
s1, slicing the whole HJT battery to obtain a HJT battery slice;
slicing the HJT battery by adopting laser scribing and mechanical splitting to obtain a plurality of independent HJT battery pieces; the HJT cell segment has at least one cutting face.
S2, stacking the HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
stacking HJT battery pieces to form a battery stack, wherein the HJT battery pieces in the battery stack are placed in the same direction, and the cutting surface of each HJT battery piece is placed upwards; the HJT battery pieces are tightly stacked, so that gaps among the HJT battery pieces are reduced, and the influence on the welding of subsequent components caused by the fact that subsequently deposited intrinsic amorphous silicon layers are deposited on the front side and the back side of the HJT battery pieces is prevented.
The tight stacking means that the gap between two adjacent HJT battery pieces is controlled within a predetermined range, preferably 35 μm or less, but not limited thereto.
Vertically placing the stack in a cassette with the deposition side facing up; the height of the deposition surface is less than or equal to that of the upper end surface of the wafer box, so that the influence on the front and back surfaces of the HJT cell piece is avoided when the intrinsic amorphous silicon layer is deposited on the deposition surface. The intrinsic amorphous silicon layer deposited and formed at the edge does not influence the light absorption of the HJT cell piece, and the short wave effect of the cell is not reduced due to the excessively thick thickness; therefore, when the intrinsic amorphous silicon layer is deposited subsequently, the deposition thickness can be set to be thicker, so that the intrinsic amorphous silicon layer with stronger passivation effect can be obtained.
Specifically, as shown in fig. 2 and 3, the cell stack 1 includes a plurality of HJT cells 2, and the number of the HJT cells 2 is 10 to 500. The HJT battery pieces 2 in the battery stack 1 are placed in the same direction, and the cutting surface of each HJT battery piece 2 is placed upwards; the upward cutting surfaces are all in the same plane to form a deposition surface 3 of the cell stack 1; the HJT battery pieces 2 are tightly stacked, so that gaps among the HJT battery pieces 2 are avoided, and the influence on the welding of subsequent components due to the fact that the subsequent deposition is carried out on the front side and the back side of the HJT battery pieces 2 is avoided.
The battery box 4 is of a cuboid box-shaped structure with an opening at the top, a containing cavity for containing the battery stack 1 is formed by enclosing the side walls of the battery box 4, and the battery stack 1 is vertically placed in the containing cavity; the deposition face 3 of the stack 1 is placed towards the opening and exposed in the opening for the next deposition; the height of the deposition surface is less than or equal to the height of the upper end surface of the wafer box, so that the influence on the front and back surfaces of the HJT cell piece is avoided when the deposition surface 3 deposits the intrinsic amorphous silicon layer.
Because a plurality of HJT battery pieces 2 can be placed in the box 4, a plurality of HJT battery pieces 2 can be deposited at one time, the production efficiency is effectively improved, and the yield of the HJT battery pieces is improved. In addition, the sheet box 4 can effectively protect the HJT cell pieces 2, can reduce mechanical scratches and contact pollution to the HJT cell pieces 2, and can prevent deposition influence on the front and back surfaces of the HJT cell pieces 2, which is beneficial to improving the quality of the battery.
The cassette 4 is made of a high temperature resistant material, and preferably, the cassette 4 is made of a quartz material or a ceramic material.
S3, placing the wafer box into PECVD equipment, and depositing on the edge of the HJT cell to form an intrinsic amorphous silicon layer;
introducing SiH by adopting PECVD equipment under the conditions that the working power is 300-4And H2Depositing an intrinsic amorphous silicon layer at the edge of the HJT cell piece; the SiH4The gas flow rate of (1) is 300-2400sccm, and the gas flow rate of (H) is H2The gas flow rate of (1) is 3000-.
The intrinsic amorphous silicon layer is adopted for edge passivation, so that the low-temperature edge passivation of the HJT battery can be realized, the passivation effect of the HJT battery is prevented from being influenced by the fact that the structure of the amorphous silicon layer in the HJT battery piece is damaged by high temperature, and the conversion efficiency of the HJT battery piece is improved;
specifically, the deposition temperature for depositing the intrinsic amorphous silicon layer is 180-230 ℃, and the deposition time is 20-200 s;
the deposition temperature is controlled to be 180 ℃ and 230 ℃, so that the thermal stress and the mechanical stress of a fracture surface can be repaired, the HJT battery piece is prevented from being subfissure in the using process, and the quality of the HJT battery piece is improved.
Preferably, the deposition temperature is 190-225 ℃, more preferably 195-220 ℃, and specifically can be 198 ℃, 200 ℃, 212 ℃, 214 ℃, 216 ℃, 218 ℃ and the like, but is not limited thereto.
The deposition time is controlled to be 20-200s, so that the deposition thickness can reach a preset value, the influence of temperature on the HJT battery piece is reduced, and the effect of reducing the production cost is achieved.
Preferably, the deposition time is 30 to 150s, more preferably 50 to 120s, and specifically, 50s, 60s, 70s, 80s, 90s, 100s, 110s, 120s, etc., but is not limited thereto.
The intrinsic amorphous silicon layer deposited on the cutting surface does not influence the light absorption of the HJT cell piece, and the short wave effect of the cell is not reduced due to the excessively thick thickness; therefore, the deposition thickness of the intrinsic amorphous silicon layer can be thicker than that of the intrinsic amorphous silicon layer deposited on the front side and the back side of the HJT cell piece, specifically, the deposition thickness of the intrinsic amorphous silicon layer is 10-50nm, and a better passivation effect can be obtained under the deposition thickness, so that the conversion efficiency of the cell is improved.
The intrinsic amorphous silicon layer is deposited on the cutting surface of the HJT cell piece, hydrogen atoms can be introduced to repair the defects formed by laser, and the edge recombination of the HJT cell piece caused by the laser is greatly reduced, so that the HJT cell efficiency and the component power loss caused by laser slicing are reduced, and the conversion efficiency of the HJT cell piece is improved; in addition, the intrinsic amorphous silicon layer can also increase the edge passivation effect of the HJT cell piece, improve the open-circuit voltage and the filling factor of the HJT cell piece, thereby improving the conversion efficiency, and meanwhile, the intrinsic amorphous silicon layer can prevent the side leakage of the HJT cell piece and improve the performance of the HJT cell piece.
S4, sorting, testing and packaging the HJT battery piece;
specifically, the HJT battery pieces are sorted and tested, and then packaged into a half battery assembly.
The invention is further illustrated by the following specific examples
Example 1
(1) Slicing the whole HJT battery to obtain a HJT battery slice;
(2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
(3) placing the wafer box into PECVD equipment, and introducing SiH under the conditions that the working power is 2000W and the pressure of a chamber is 3Torr4And H2Depositing an intrinsic amorphous silicon layer at the edge of the HJT cell piece, wherein the deposition temperature is 230 ℃, and the deposition time is 200 s; obtaining the intrinsic amorphous silicon layer with the thickness of 50 nm;
(4) and (4) sorting, testing and packaging the HJT battery piece.
Example 2
(1) Slicing the whole HJT battery to obtain a HJT battery slice;
(2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
(3) placing the wafer box into PECVD equipment, and introducing SiH under the conditions that the working power is 800W and the pressure of a chamber is 1Torr4And H2Depositing an intrinsic amorphous silicon layer on the edge of the HJT cell piece, wherein the deposition temperature is 180 ℃, and the deposition time is 20 s; obtaining the intrinsic amorphous silicon layer with the thickness of 10 nm;
(4) and (4) sorting, testing and packaging the HJT battery piece.
Example 3
(1) Slicing the whole HJT battery to obtain a HJT battery slice;
(2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
(3) placing the wafer box into PECVD equipment, and introducing SiH under the conditions that the working power is 1000W and the pressure of a chamber is 2Torr4And H2Depositing an intrinsic amorphous silicon layer at the edge of the HJT cell piece, wherein the deposition temperature is 200 ℃, and the deposition time is 80 s; the thickness of the obtained intrinsic amorphous silicon layer is 30 nm;
(4) and (4) sorting, testing and packaging the HJT battery piece.
Example 4
(1) Slicing the whole HJT battery to obtain a HJT battery slice;
(2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
(3) placing the wafer box into PECVD equipment, and introducing SiH under the conditions that the working power is 1500W and the pressure of a chamber is 2.5Torr4And H2Depositing an intrinsic amorphous silicon layer on the edge of the HJT cell piece, wherein the deposition temperature is 180 ℃, and the deposition time is 90 s; the thickness of the obtained intrinsic amorphous silicon layer is 35 nm;
(4) and (4) sorting, testing and packaging the HJT battery piece.
Comparative example
(1) Slicing the whole HJT battery to obtain a HJT battery slice;
(2) and (4) sorting, testing and packaging the HJT battery piece.
The comparative example differs from examples 1-4 in that the comparative example did not undergo edge passivation after slicing; the battery modules obtained after the encapsulation of the comparative example and examples 1to 4 were subjected to battery electrical property tests, and the results are shown in table 1.
Table 1 cell electrical performance test results
From the above results, it can be seen that the conversion efficiency, the open circuit voltage, and the short circuit current of examples 1, 2, 3, and 4 are all higher than the comparative example, i.e., the cells produced by HJT cells subjected to edge passivation have better passivation effect, higher cell conversion efficiency, and better quality.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A method of edge passivation for an HJT cell, comprising:
(1) slicing the whole HJT battery to obtain a HJT battery slice;
(2) stacking HJT battery pieces to form a battery stack, and vertically placing the battery stack into a piece box;
(3) placing the wafer box into PECVD equipment, and depositing on the edge of the HJT cell to form an intrinsic amorphous silicon layer;
(4) sorting, testing and packaging the HJT battery piece;
wherein, in the step (3), the deposition temperature for depositing the intrinsic amorphous silicon layer is 180-230 ℃, and the deposition time is 20-200 s.
2. The method for passivating the edge of an HJT cell as defined in claim 1, wherein in the step (3), SiH is introduced into the cell by using a PECVD apparatus under the conditions of a working power of 300-4And H2And depositing an intrinsic amorphous silicon layer at the edge of the HJT cell slice.
3. The method of claim 2, wherein the SiH is used to passivate the edges of the HJT cell4The gas flow rate of (1) is 300-2400sccm, and the gas flow rate of (H) is H2The gas flow rate of (1) is 3000-.
4. The method of claim 1, wherein in step (1), the HJT cell is sliced using laser scribing and mechanical breaking to obtain a plurality of individual HJT cells; the HJT cell segment has at least one cutting face.
5. The method of claim 4, wherein the HJT cells in the stack are placed in the same direction, and each HJT cell is placed with its cut side facing upward; the upward cutting surfaces are all in the same plane to form a deposition surface of the cell stack; the HJT battery pieces are tightly stacked.
6. The method of claim 5, wherein the cell stack is placed in a cassette with the deposition side facing up; the height of the deposition surface is less than or equal to the height of the upper end surface of the wafer box.
7. The method of claim 1, wherein the intrinsic amorphous silicon layer is deposited to a thickness of 10-50 nm.
8. The method of claim 1, wherein the HJT cell stack comprises 10-500 HJT cells.
9. The method of claim 1, wherein the cassette is made of a high temperature resistant material.
10. An HJT cell made by the method of edge passivation of an HJT cell according to any of claims 1to 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117153898A (en) * | 2023-09-13 | 2023-12-01 | 理想晶延半导体设备(上海)股份有限公司 | Cut battery piece and component thereof and passivation coating method for side section of battery piece |
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