CN112699062A - High speed data storage system - Google Patents
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
The application relates to a data high-speed storage system, which comprises a CPU (central processing unit) module, a storage module, an interaction module, a cache control module, a DDR (double data rate) module and a storage control module which are integrated in the same FPGA platform, wherein embedded soft cores are arranged in the modules integrated in the FPGA platform and realize different functions under the control of the CPU module so as to support data caching and data writing, the FPGA platform and the CPU module adopt a heterogeneous multi-core architecture, the CPU module can flexibly control each embedded soft core in the FPGA platform and further give full play to the processing capacity of the embedded soft cores, the defect of weak processing capacity of the soft cores on a single FPGA platform in the prior art is overcome, and the high-speed storage of data is realized.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a high-speed data storage system.
Background
The information technology is developed at a high speed, the throughput of data processing is higher and higher, and the demand for high-speed storage is higher and higher, so the high-speed storage technology is more and more important.
The quality of a storage system is evaluated, mainly considering the speed and storage capacity of the stored data. Under the condition of ensuring stability, the data read-write speed and the storage capacity are improved as much as possible so as to meet the requirements of modern industrial science research on the storage speed and the storage capacity of the system. In the conventional technology, in order to realize high-speed storage, a plurality of CPUs and a memory with a large capacity are generally integrated to realize data storage, and it is desirable to improve the efficiency of data storage through an increase in hardware resources.
Although the data storage efficiency can be improved to a certain extent by stacking the hardware resources in a 'rough' manner, when the data volume is large, particularly when high-speed storage is required, the storage efficiency is improved due to the fact that the hardware storage resources cannot be fully utilized in the manner, and high-speed storage of big data cannot be achieved.
Disclosure of Invention
In view of the above, it is necessary to provide a system capable of realizing high-speed data storage in response to the above technical problems.
A data high-speed storage system comprises a CPU module, an interaction module, a cache control module, a DDR module, a storage control module and a storage module, wherein the interaction module, the cache control module, the DDR module and the storage control module are integrated on the same FPGA platform;
the CPU module is connected with the interaction module, the interaction module is connected with the DDR module, the DDR module is connected with the cache control module and the storage control module, and the storage control module is connected with the storage module;
the interaction module, the cache control module and the storage control module are internally provided with embedded soft cores, the embedded soft cores in different modules realize different functions under the control of the CPU module, and the FPGA platform and the CPU module form a heterogeneous multi-core architecture.
In one embodiment, the interaction module includes a first embedded soft core and a multi-point access unit connected to each other, and the multi-point access unit is connected to the CPU module and the DDR module, respectively.
In one embodiment, the memory control module comprises a first memory control unit, a second memory control unit, a third memory control unit and a fourth memory control unit which are respectively connected with the DDR module;
the first storage control unit, the second storage control unit, the third storage control unit and the fourth storage control unit are respectively provided with an embedded soft core therein, and the first storage control unit, the second storage control unit, the third storage control unit and the fourth storage control unit are respectively connected with the storage module.
In one embodiment, the embedded soft cores arranged in the first storage control unit, the second storage control unit, the third storage control unit and the fourth storage control unit respectively obtain SATA control linked lists issued by the CPU module, and control data streams to interact between the DDR module and the storage module according to the SATA control linked lists.
In one embodiment, the first storage control unit includes a second embedded soft core and a first data read-write control unit that are connected to each other, the second storage control unit includes a third embedded soft core and a second data read-write control unit that are connected to each other, the third storage control unit includes a fourth embedded soft core and a third data read-write control unit that are connected to each other, and the fourth storage control unit includes a fifth embedded soft core and a fourth data read-write control unit that are connected to each other;
the first data read-write control unit, the second data read-write control unit, the third data read-write control unit and the fourth data read-write control unit are respectively connected with the DDR module and the storage module.
In one embodiment, the cache control module includes a first cache control unit, a second cache control unit, and a third cache control unit, where the first cache control unit, the second cache control unit, and the third cache control unit are respectively connected to the DDR module, and embedded soft cores are disposed in the first cache control unit, the second cache control unit, and the third cache control unit.
In one embodiment, the embedded soft cores arranged in the first cache control unit, the second cache control unit and the third cache control unit respectively obtain the data source control linked list issued by the CPU module, and control data to be cached to the DDR module according to the data source control linked list.
In one embodiment, the first cache control unit comprises a first real-time cache component, and a first high-speed interface and a sixth embedded soft core which are respectively connected with the first real-time cache component; the second cache control unit comprises a second real-time cache component, a second high-speed interface and a seventh embedded soft core, wherein the second high-speed interface and the seventh embedded soft core are respectively connected with the second real-time cache component; the third cache control unit comprises a third real-time cache component, a third high-speed interface and an eighth embedded soft core which are respectively connected with the third real-time cache component;
the first real-time cache component, the second real-time cache component and the third real-time cache component are respectively connected with the DDR module, and the first real-time cache component, the second real-time cache component and the third real-time cache component realize direct data storage access to the DDR module through logic design.
In one embodiment, the DDR module comprises at least two groups of DDR units, and data flow caching is achieved between the DDR units in a ping-pong mode.
In one embodiment, the data high-speed storage system further comprises an MB _ TO _ MB module, and the MB _ TO _ MB module is used for realizing communication among different embedded soft cores.
The data high-speed storage system comprises a CPU module, a storage module, an interaction module, a cache control module, a DDR module and a storage control module, wherein the interaction module, the cache control module, the DDR module and the storage control module are integrated in the same FPGA platform, embedded soft cores are arranged in the modules integrated in the FPGA platform and realize different functions under the control of the CPU module so as to support data caching and data writing, the FPGA platform and the CPU module adopt a heterogeneous multi-core architecture, the CPU module can flexibly control each embedded soft core in the FPGA platform and further give full play to the processing capacity of the embedded soft cores, the defect that the processing capacity of the soft cores on a single FPGA platform is not strong in the prior art is overcome, and high-speed storage of data is realized.
Drawings
FIG. 1 is a schematic diagram of a data cache system according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a high-speed data storage system according to another embodiment of the present application;
FIG. 3 is a schematic structural diagram of a data high-speed storage system according to the present application in an exemplary application;
FIG. 4 is a schematic diagram of data interaction of a data high-speed storage system according to the present application in an application example.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
As shown in fig. 1, the present application provides a data high-speed storage system, which includes a CPU module 100, an interaction module 200, a cache control module 300, a DDR module 400, a storage control module 500, and a storage module 600, where the interaction module 200, the cache control module 300, the DDR module 400, and the storage control module 500 are integrated on the same FPGA platform;
the CPU module 100 is connected with the interaction module 200, the interaction module 200 is connected with the DDR module 400, the DDR module 400 is connected with the cache control module 300 and the storage control module 500, and the storage control module 500 is connected with the storage module 600;
embedded soft cores are arranged in the interaction module 200, the cache control module 300 and the storage control module 500, the embedded soft cores in different modules realize different functions under the control of the CPU module 100, and the FPGA platform and the CPU module 100 form a heterogeneous multi-core architecture.
The CPU module 100 serves as a control instruction output module, and issues a control instruction to an embedded soft core (MicroBlaze core) in a centralized module of the FPGA platform to control the embedded soft core to execute a corresponding function. Specifically, for the cache control module 300, the CPU module 100 may issue a data source control linked list, and for the storage control module 500, the CPU module 100 may issue an SATA (SATA hard disk) control linked list. The CPU can be pre-loaded with a software control program, and after responding to user operation, the pre-loaded program is directly executed to issue a control instruction to each embedded soft core in the FPGA platform. More specifically, the CPU module 100 may include a domestic CPU chip, where internal storage control software (APP _ STORE) implements a file system, and multiple MicroBlaze core scheduling, DDR cache addresses, and data file storage management are implemented by interaction of a storage control instruction chain table.
In practical applications, the storage control instruction chain table is specifically shown in table 1 below.
TABLE 1 store control instruction Linked List
The interaction module 200 is used to implement data receiving and forwarding, specifically, to issue data such as an instruction/linked list issued by the CPU module 100, and to upload data fed back by each module to the CPU module 100. In order to improve the performance, an embedded soft core can be arranged in the device to support high-speed interactive transmission of data. The interaction module 200 may specifically be a PCIE (peripheral component interconnect express, high speed serial computer extended bus standard) interaction module 200.
The cache control module 300 is used for receiving and caching externally input high-speed data. In order to implement the cache, embedded control cores are disposed in the cache control module 300, and the embedded control cores execute corresponding functions under the control instruction of the CPU module 100, specifically, receive the data source control linked list issued by the CPU module 100. In order to achieve higher efficiency of receiving and caching, the cache control module 300 may specifically include a plurality of cache control units, each of which is provided with an embedded control core, and the cache control units may cooperate with each other to complete caching of data.
The DDR module 400 is configured to cache information such as an address corresponding to data, and may specifically include DDR 3. Further, the DDR module 400 may include multiple sets of DDR units, which are connected to each other and implement the data pipeline cache in a ping-pong manner, for example, the DDR module 400 may include 2 sets of DDR3, each set having a bit width of 64b, and implement the data pipeline cache in a ping-pong manner.
The memory control module 500 is used to write high speed data to the memory module 600. In order to realize high-speed disk writing, embedded control cores are provided in the storage control module 500, and these embedded controls execute corresponding functions under the control instruction of the CPU module 100, specifically, receive the SATA control linked list issued by the CPU module 100. In order to implement efficient disk writing, the storage control module 500 may include a plurality of storage control units, each of which is provided with an embedded control core, and the storage control units may employ a high-speed disk writing method that cooperates with each other to complete data writing.
The storage module 600 is used to provide disk space for storing large amounts of data. Specifically, the storage module 600 may be a SATA-protocol-based solid state storage carrier (SATA _ GROUP), each GROUP includes 8 SATA3.0 solid state disks, and a single SATA3.0 solid state disk may be configured; multiple SATA _ GROUP GROUPs can also be configured; the capacity of the SATA3.0 solid state disk is supported to be 64GB, 128GB, 256GB, 512GB, 1TB, 2TB and the like.
The data high-speed storage system comprises a CPU (central processing unit) module 100, a storage module 600, an interaction module 200, a cache control module 300, a DDR (double data rate) module 400 and a storage control module 500 which are integrated in the same FPGA platform, wherein embedded soft cores are arranged in the modules integrated in the FPGA platform and realize different functions under the control of the CPU module 100 so as to support data caching and data writing, the FPGA platform and the CPU module 100 adopt a heterogeneous multi-core architecture, the CPU module 100 can flexibly control each embedded soft core in the FPGA platform and further give full play to the processing capacity of the embedded soft cores, the defect that the processing capacity of the soft cores on a single FPGA platform is not strong in the prior art is overcome, and the high-speed storage of data is realized.
In one embodiment, the interaction module 200 includes a first embedded soft core and a multi-point access unit connected to each other, and the multi-point access unit is connected to the CPU module 100 and the DDR module 400, respectively.
In this embodiment, the interaction module 200 is internally provided with a first embedded soft core and a multi-point access unit, so as to implement efficient uploading and issuing of data. The PCIE interaction module may be specifically a PCIE _ MB implemented based on an FPGA, and the PCIE portion may adopt a hard core multi-point access (XDMA IP) design, and interact with MicroBlaze core management and storage control software (APP _ STORE) preloaded in the CPU module 100; the interactive information is a storage control instruction linked list, and linked list information is issued in a preprocessing mode, so that the problem of upper computer information issuing delay is solved. The structure of the first embedded soft core and the multi-point access unit and the connection relationship between the first embedded soft core and the multi-point access unit and the external device can be seen in fig. 3.
As shown in FIG. 2, in one embodiment, the memory control module 500 includes a first memory control unit 510, a second memory control unit 520, a third memory control unit 530, and a fourth memory control unit 540, respectively connected to the DDR module 400; the first storage control unit 510, the second storage control unit 520, the third storage control unit 530 and the fourth storage control unit 540 are respectively provided with an embedded soft core therein, and the first storage control unit 510, the second storage control unit 520, the third storage control unit 530 and the fourth storage control unit 540 are respectively connected with the storage module 600.
In this embodiment, the storage control module 500 is composed of 4 parallel storage control units, each of which is provided with an embedded soft core, so as to implement independent control and independent processing capability, and support data streams to be written into the storage module 600 through different storage control units. The functions of the embedded soft cores in the 4 storage control units may be similar or identical, and the embedded soft cores may acquire the SATA control linked list issued by the CPU module 100, and control data streams to interact between the DDR module 400 and the storage module 600 according to the SATA control linked list. As shown in fig. 2 and fig. 3, the storage module 600 may correspondingly include 4 storage units, each storage unit is connected to one storage control unit, and each storage unit includes 8 SATA3.0 solid state disks. In practical applications, the SATA control chain table contains specific data as shown in table 2 below.
Table 2 shows the SATA control chain table
In one embodiment, the first storage control unit 510 includes a second embedded soft core and a first data read-write control unit connected to each other, the second storage control unit 520 includes a third embedded soft core and a second data read-write control unit connected to each other, the third storage control unit 530 includes a fourth embedded soft core and a third data read-write control unit connected to each other, and the fourth storage control unit 540 includes a fifth embedded soft core and a fourth data read-write control unit connected to each other; the first data read-write control unit, the second data read-write control unit, the third data read-write control unit and the fourth data read-write control unit are respectively connected with the DDR module 400 and the memory module 600.
In this embodiment, each storage control unit includes an embedded soft core and a data read-write control unit, and the two units work in coordination to realize data caching. Specifically, the data read/write control unit may be designed based on the SATA controller implemented based on FPGA logic, and complete transmission of data streams between the DDR module 400 and the memory module 600 by using a DMA method. In practical applications, as shown in fig. 3, the storage control module 500(SATA _ CTR _ CORE) is composed of 1 MicroBlaze CORE and a data read-write control unit (SATA _ RW _ CTR); the data read-write control unit (SATA _ RW _ CTR) realizes the design based on the SATA controller based on FPGA logic, and adopts a DMA mode to complete the transmission of data stream between the DDR cache and the SATA _ GROUP; the MicroBlaze core is responsible for communicating with PCIE _ MB, acquiring an SATA control linked list, issuing information such as operation type, DDR cache address, sector address required by the SATA controller, data size and the like according to the SATA control linked list, and reporting after the read-write operation of SATA _ GROUP is completed.
As shown in fig. 2, in one embodiment, the cache control module 300 includes a first cache control unit 310, a second cache control unit 320, and a third cache control unit 330, the first cache control unit 310, the second cache control unit 320, and the third cache control unit 330 are respectively connected to the DDR module 400, and embedded soft cores are disposed in the first cache control unit 310, the second cache control unit 320, and the third cache control unit 330.
In this embodiment, the cache control module 300 is composed of 3 parallel cache control units, and each cache control unit is provided with an embedded soft core, so as to implement independent control and independent processing capability, and support the high-speed data to be received and cached by different cache control units. The functions of the embedded soft cores in the 3 cache control units may be similar or identical, and may obtain a data source control linked list issued by the CPU module 100, and control the receiving and caching of the high-speed data according to the data source control linked list. In practical applications, the data source control linked list contains specific data as shown in table 3 below.
Table 3 shows the data source control chain table
In one embodiment, the first cache control unit comprises a first real-time cache component, and a first high-speed interface and a sixth embedded soft core which are respectively connected with the first real-time cache component; the second cache control unit comprises a second real-time cache component, a second high-speed interface and a seventh embedded soft core, wherein the second high-speed interface and the seventh embedded soft core are respectively connected with the second real-time cache component; the third cache control unit comprises a third real-time cache component, a third high-speed interface and an eighth embedded soft core which are respectively connected with the third real-time cache component; the first real-time cache component, the second real-time cache component and the third real-time cache component are respectively connected with the DDR module, and the first real-time cache component, the second real-time cache component and the third real-time cache component realize direct data storage access to the DDR module through logic design.
Different cache control units respectively comprise a real-time cache component, a high-speed interface and an embedded soft core, wherein the real-time cache component is used for being matched with a DDR module to realize high-efficiency cache of high-speed data, and the real-time cache component can specifically realize direct storage access of the data to the DDR module through logic design, so that the defects that waiting is needed when the embedded soft core is adopted to call CDMA/DMAIP, and nesting is easily interrupted are overcome. The first high-speed interface, the second high-speed interface and the third high-speed interface may be high-speed interfaces respectively supporting different protocols, for example, may support the reception of data of Aurora, 10G _ ETH and SRIO protocols respectively. The specific structure of the cache control unit can be seen in fig. 3.
As shown in fig. 3, in an application example, the cache control module (GT _ CTR _ BUF) has 3 high-speed interfaces, and can implement data receiving and caching for 3 different protocols, where the specific data interfaces include Aurora, 10G _ ETH, and SRIO. The number of each interface can be configured, and the line rates of Aurora and SRIO can be configured; the cache control module is matched with a DATA _ CTR _ BUF (DATA _ CTR _ BUF) to realize the fast and efficient cache of high-speed DATA to the DDR by a MicroBlaze core and the real-time DATA cache component; the real-time DATA cache component (DATA _ CTR _ BUF) realizes DATA DMA (Direct Memory Access) to a DDR cache by logic design, and solves the problems that waiting is needed and nesting is easy to interrupt when a MicroBlaze calls CDMA/DMA IP; the MicroBlaze core is responsible for communicating with the PCIE _ MB, acquiring a DATA source control linked list, acquiring channel start-stop information, DATA record playback information, DDR cache addresses and the like, and simultaneously reporting the DATA type and quantity and issuing the DDR cache addresses to a real-time DATA cache module (DATA _ CTR _ BUF).
As shown in fig. 3, in one embodiment, the data high-speed storage system of the present application further includes an MB _ TO _ MB module, where the MB _ TO _ MB module is used TO implement communication between different embedded soft cores.
The MB _ TO _ MB module specifically comprises a plurality of MB _ TO _ MB modules, wherein the MB _ TO _ MB modules are MicroBlaze core and MicroBlaze core communication components developed based on FPGA logic, and the mark AXI4 bus is adopted TO realize high-efficiency communication between the MicroBlaze core and the MicroBlaze core.
In practical application, different embedded soft cores (hereinafter referred to as MicroBlaze cores) complete different data processing, including communication with a CPU, data source data management, SATA read-write disk data management, and communication between MicroBlaze and MicroBlaze.
As shown in fig. 3, specifically, the MicroBlaze _0 implements interaction and analysis between the PCIE _ MB and the storage control instruction linked list of the CPU; the SATA control linked list interaction between MicroBlaze _0 and MicroBlaze _1/MicroBlaze _2/MicroBlaze _3/MicroBlaze _4 is realized; and realizing the interaction of the data source control linked list between MicroBlaze _0 and MicroBlaze _5/MicroBlaze _6/MicroBlaze _ 7.
The MicroBlaze _1 realizes the interaction with the SATA control linked list between MicroBlaze _0, issues information such as operation type, DDR cache address, sector address required by the SATA controller, data size and the like according to the SATA control linked list, and reports MicroBlaze _0 after the read-write operation of SATA _ GROUP0 is completed.
The MicroBlaze _2 realizes the interaction with the SATA control linked list between MicroBlaze _0, issues information such as operation type, DDR cache address, sector address required by the SATA controller, data size and the like according to the SATA control linked list, and reports MicroBlaze _0 after the read-write operation of SATA _ GROUP1 is completed.
The MicroBlaze _3 realizes the interaction with the SATA control linked list between MicroBlaze _0, issues information such as operation type, DDR cache address, sector address required by the SATA controller, data size and the like according to the SATA control linked list, and reports MicroBlaze _0 after the read-write operation of SATA _ GROUP2 is completed.
The MicroBlaze _4 realizes the interaction with the SATA control linked list between MicroBlaze _0, issues information such as operation type, DDR cache address, sector address required by the SATA controller, data size and the like according to the SATA control linked list, and reports MicroBlaze _0 after the read-write operation of SATA _ GROUP3 is completed.
The MicroBlaze _5 realizes the interaction of a DATA source control linked list with MicroBlaze _0, simultaneously reports the DATA type and the DATA quantity according to the acquired Aurora channel start-stop information, DATA record playback information, DDR cache address and the like, and sends the DDR cache address to a real-time DATA cache module (DATA _ CTR _ BUF), and reports MicroBlaze _0 after the GT _ CTR _ BUF 0 operation is finished.
The MicroBlaze _6 realizes the interaction with a DATA source control linked list between MicroBlaze _0, simultaneously reports the DATA type and the quantity according to the acquired SRIO channel start-stop information, DATA record playback information, DDR cache address and the like, and sends the DDR cache address to a real-time DATA cache module (DATA _ CTR _ BUF), and reports MicroBlaze _0 after the GT _ CTR _ BUF 0 operation is finished.
The MicroBlaze _7 realizes the interaction with a DATA source control linked list between MicroBlaze _1, and reports the DATA type, the DATA quantity and the DDR cache address to a real-time DATA cache module (DATA _ CTR _ BUF) according to the acquired 10G _ ETH channel start-stop information, the DATA record playback information, the DDR cache address and the like, and reports MicroBlaze _0 after the GT _ CTR _ BUF 2 operation is finished.
When recording data, the data flow direction is depicted by the black solid arrow in fig. 3: Aurora/SRIO/10G _ ETH- - > DATA _ CTR _ BUF- - > DDR- - > SATA _ RW _ CTR- - > GT- - > SATA _ GROUP; when data is played back, the data flow direction is depicted by the black solid arrow in fig. 3: SATA _ GROUP- > GT- - > SATA _ RW _ CTR- - > DDR- - > DATA _ CTR _ BUF- - > Aurora/SRIO/10G _ ETH.
The whole data interaction process will be described in detail in conjunction with fig. 4, and for the convenience of explanation, the following reference numerals are used for some data appearing in fig. 4: the storage control instruction linked list is composed of
Represents; data source control linked list consists of (a), (b), (c) and (c)
Represents; sixthly, the SATA control chain table is seventeenth,
and
and (4) showing.
A data recording step:
a) and (4) issuing a storage control instruction linked list, and issuing a domestic CPU (APP _ STORE).
b) The SATA control linked list is issued, and the MicroBlaze _0 receives and analyzes the storage control instruction linked list; and (6) sequentially issuing the (b) MicroBlaze _0, the (c) MicroBlaze _1, the (b) MicroBlaze _2, the (b) MicroBlaze _3 and the (b) MicroBlaze _ 4.
c) And (3) issuing the data source control linked list, and issuing the MicroBlaze _0, the third and the fourth to MicroBlaze _5, MicroBlaze _6 and MicroBlaze _ 7.
d) Starting recording, the MicroBlaze _5 cache area is full, starting another cache area cache data of the DDR, reporting nine to MicroBlaze _0 by MicroBlaze _5, and receiving nine by MicroBlaze _0
Reporting to the CPU, and finishing one-time data source DDR cache address interaction at the moment; starting recording, MicroBlaze _6 buffer is full, starting another buffer of DDR to buffer data, at the same time MicroBlaze _6 will report to MicroBlaze _0 on the R, MicroBlaze _0 will receive the R
Reporting to the CPU, and finishing one-time data source DDR cache address interaction at the moment; starting to record, the MicroBlaze _7 buffer is full, another buffer of DDR is started to buffer data, and the MicroBlaze _7 buffer will store the data
Reporting to MicroBlaze _0, and MicroBlaze _0 receiving
Then will
Reporting to the CPU, and finishing one-time data source DDR cache address interaction at the moment.
e) Storing the data in a disk, and after ninthly, sending the data to MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _4 in sequence; after the MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _4 are received, the disk storage operation is started, and after the disk storage operation is completed, MicroBlaze _0 waits for
And
all receive then
Reporting to the CPU, finishing a data storage operation at the moment, and finishing a SATA address interaction; storing data in disk, after receiving the data, MicroBlaze _0 sends down (C) to MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _ 4; after the MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _4 are received, the disk storage operation is started, and after the disk storage operation is completed, MicroBlaze _0 waits for
And
all receive then
Reporting to the CPU, finishing a data storage operation at the moment, and finishing a SATA address interaction; data storage, MicroBlaze _0 reception
Then, the fifth, the sixth, the seventh and the seventh are issued to MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _4 in sequence; MicroBlaze _1, MicroBlaze _2, MicroBlazee _3, after the MicroBlaze _4 is received, the disk storage operation is started, and after the disk storage operation is finished, the MicroBlaze _0 waits
And
all receive then
Reporting to CPU, finishing one data storage operation and one SATA address interaction.
f) Stopping data recording: a domestic CPU (APP _ STORE) issues a first step, wherein the first step comprises a channel shutdown instruction; the MicroBlaze _0 issues the second, third and fourth to MicroBlaze _5, MicroBlaze _6 and MicroBlaze _7 to turn off the channel; MicroBlaze _0 receives a ninthly; the fifth, the sixth, the seventh and the eighth parts of MicroBlaze _0 are sequentially issued to MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _ 4; MicroBlaze _0 will wait
And
all receive then
Reporting to the CPU to complete one SATA address interaction; MicroBlaze _0 receives r; the fifth, the sixth, the seventh and the eighth parts of MicroBlaze _0 are sequentially issued to MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _ 4; MicroBlaze _0 will wait
And
all receive then
Report to CPU, finishing one SATA address interaction; MicroBlaze _0 reception
The fifth, the sixth, the seventh and the eighth parts of MicroBlaze _0 are sequentially issued to MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _ 4; MicroBlaze _0 will wait
And
all receive then
Reporting to CPU to complete SATA address interaction.
g) CPU (APP _ STORE) reception
And updating the file system in real time to wait for the next read-write operation.
The data playback flow is similar to recording and will not be repeated here.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A data high-speed storage system is characterized by comprising a CPU module, an interaction module, a cache control module, a DDR module, a storage control module and a storage module, wherein the interaction module, the cache control module, the DDR module and the storage control module are integrated on the same FPGA platform;
the CPU module is connected with the interaction module, the interaction module is connected with the DDR module, the DDR module is connected with the cache control module and the storage control module, and the storage control module is connected with the storage module;
the interaction module, the cache control module and the storage control module are internally provided with embedded soft cores, the embedded soft cores in different modules realize different functions under the control of the CPU module, and the FPGA platform and the CPU module form a heterogeneous multi-core architecture.
2. The system of claim 1, wherein the interaction module comprises a first embedded soft core and a multi-point access unit connected to each other, and the multi-point access unit is connected to the CPU module and the DDR module, respectively.
3. The system of claim 1, wherein the memory control module comprises a first memory control unit, a second memory control unit, a third memory control unit, and a fourth memory control unit respectively connected to the DDR module;
the first storage control unit, the second storage control unit, the third storage control unit and the fourth storage control unit are respectively provided with an embedded soft core therein, and the first storage control unit, the second storage control unit, the third storage control unit and the fourth storage control unit are respectively connected with the storage module.
4. The system of claim 3, wherein embedded soft cores arranged in the first storage control unit, the second storage control unit, the third storage control unit, and the fourth storage control unit respectively obtain SATA control linked lists issued by the CPU module, and control data streams to interact between the DDR module and the storage module according to the SATA control linked lists.
5. The system of claim 3, wherein the first storage control unit comprises a second embedded soft core and a first data read-write control unit which are connected with each other, the second storage control unit comprises a third embedded soft core and a second data read-write control unit which are connected with each other, the third storage control unit comprises a fourth embedded soft core and a third data read-write control unit which are connected with each other, and the fourth storage control unit comprises a fifth embedded soft core and a fourth data read-write control unit which are connected with each other;
the first data read-write control unit, the second data read-write control unit, the third data read-write control unit and the fourth data read-write control unit are respectively connected with the DDR module and the storage module.
6. The system of claim 1, wherein the cache control module comprises a first cache control unit, a second cache control unit, and a third cache control unit, the first cache control unit, the second cache control unit, and the third cache control unit are respectively connected to the DDR module, and embedded soft cores are disposed in the first cache control unit, the second cache control unit, and the third cache control unit.
7. The system of claim 6, wherein embedded soft cores disposed in the first, second, and third cache control units respectively obtain a data source control linked list issued by the CPU module, and control data caching to the DDR module according to the data source control linked list.
8. The system of claim 6, wherein the first cache control unit comprises a first real-time cache component, and a first high-speed interface and a sixth embedded soft core respectively connected to the first real-time cache component; the second cache control unit comprises a second real-time cache component, a second high-speed interface and a seventh embedded soft core, wherein the second high-speed interface and the seventh embedded soft core are respectively connected with the second real-time cache component; the third cache control unit comprises a third real-time cache component, a third high-speed interface and an eighth embedded soft core which are respectively connected with the third real-time cache component;
the first real-time cache component, the second real-time cache component and the third real-time cache component are respectively connected with the DDR module, and the first real-time cache component, the second real-time cache component and the third real-time cache component realize direct data storage access to the DDR module through logic design.
9. The system of claim 1, wherein the DDR module comprises at least two sets of DDR units, and wherein data flow buffering is implemented between the DDR units in a ping-pong manner.
10. The system of claim 1, further comprising an MB _ TO _ MB module configured TO enable communication between different embedded soft cores.
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