CN112697842B - ASIC for measuring fA-pA magnitude weak current - Google Patents
ASIC for measuring fA-pA magnitude weak current Download PDFInfo
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- CN112697842B CN112697842B CN202011430106.7A CN202011430106A CN112697842B CN 112697842 B CN112697842 B CN 112697842B CN 202011430106 A CN202011430106 A CN 202011430106A CN 112697842 B CN112697842 B CN 112697842B
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Abstract
The invention relates to an ASIC for measuring fA-pA magnitude weak current, which is provided with ten pins, wherein the first pin is a signal input pin and is used for inputting current to be measured; the seventh pin is a power ground pin; the tenth pin is a power supply positive electrode pin; the second, third, fourth, fifth, sixth, eighth and ninth pins are functional pins and are used for connecting ASIC peripheral elements; the fifth pin is used as a signal output pin for outputting the amplified voltage and is connected to the input end of the intermediate amplifier; the ASIC comprises an amplifying circuit consisting of two CMOS operational amplifiers, four CMOS transmission gates, seven CMOS inverters, three resistors and two capacitors; the seventh pin of the ASIC is connected to the ground end of the power supply, and the tenth pin of the ASIC is connected to the positive end of the power supply; the ASIC first pin is a current signal input end to be detected and is used for inputting current to be detected; and the fifth pin of the ASIC is an amplified voltage signal output end and is used for inputting an amplified voltage signal.
Description
Technical Field
The invention relates to an ASIC, in particular to an ASIC for measuring fA-pA magnitude weak current.
Background
The application is a divisional application of CN 2019100945901.
The nano film is a film material formed by attaching a substrate with the size of nano magnitude (1-100 nm), and has the advantages of both the traditional composite material and the modern nano material. In the research and application of various high-insulation nano thin film materials, the leakage current characteristic of the nano thin film, namely a voltage-current characteristic curve, is often required to be tested and mastered. However, the electrical properties of the nano-film having a thickness of 1 to 100nm are difficult to measure:
because the thickness of the nanometer film is extremely thin, the mechanical strength is low, and the puncture and pressure resistance is poor, when the probe contacts the electrode of the nanometer film, the traditional probe station often causes the failure of the frequent measurement of the electrical property because the needle point punctures the electrode and the nanometer film material. In order to avoid the probe of the probe station from puncturing the film during the test, some manufacturers have also provided some elastic test probes with miniature springs in the needle tubes, and the probes can reduce the damage of the needle tips to the film because the miniature springs can provide a certain elastic stroke when the probes contact and puncture the film. However, although the test probe has a certain elasticity, the test probe is generally only suitable for a film with a thickness of micron and submicron order, and for a nano film with a thickness of 1-100 nm, especially for a film with a thickness of tens of nanometers to a few nanometers, the thickness of the test probe is only tens of atomic layers, and the elasticity test probe with the built-in micro spring still appears careless, and can often puncture the nano film or penetrate into the film, so that the electrical property measurement of the film is very difficult.
There are also foreign instrument manufacturers that provide probe stations for such electrical measurement of nano-films, such as an automatic probe test bed of a flat-motor type x-y stage (also called a magnetic air-floating stage) represented by the american EG company and an automatic probe test bed of an x-y stage type using a precise ball screw pair and a linear guide structure produced in japan and europe. However, these probe stations are quite complex and delicate in construction, extremely expensive, difficult to operate and maintain, and high end models limit export.
The probe is a contact medium for electrical test and is a high-end precise electronic hardware component. Microelectronic test probes: the core technology of the wafer test or chip IC detection probe is still mastered in foreign companies, and domestic manufacturers actively participate in research and development, but only a small part of the probes are successfully produced. Typically customized for a small number of customers who make large test machines, such as the terraced (Teradyne) and Agilent (Agilent).
The existing probe can only be used for a film with the thickness of micron and submicron level, but can not be used for a nano film.
In addition, most of the nanoscale insulating films have extremely weak leakage currents, typically several tens of fA (10)-15A) To tens of pA (10)-12A) In the case of a dielectric thin film having a high impurity content and a poor insulation property, the leakage current is generally only nA (10)-9A) Magnitude. For such weak current signals, the measurement current cannot be directly measured, and an amplifier circuit with a conventional structure cannot be used for accurately measuring the leakage current characteristic of the insulating film, i.e., a voltage-current characteristic curve.
In another application of the same date we propose a solution, but in this solution, a relatively large number of discrete components and two operational amplifiers are used, and in practical applications, such a solution still has some disadvantages:
the circuit is built by adopting discrete elements, the integration level is not high, various difficulties are brought to debugging the circuit, the design cost is high, and the reliability of the system is still to be improved. Moreover, when discrete components are adopted, the values of various resistors and capacitors have dispersion, and even if the values of the resistors or capacitors have the same nominal value, the difference between the values is 20-5%, when a measurement system is produced, the components need to be selected precisely, and the debugging work is heavy and easy to be wrong.
Disclosure of Invention
In order to solve the problems of the prior art, the present invention is directed to provide an ASIC, which can accurately measure a leakage current characteristic, i.e., a voltage-current characteristic curve, of a nano-film having a thickness of 1 to 100 nm.
The specific technical scheme for realizing the purpose of the invention is as follows:
a voltage-current characteristic measuring system of a nanometer insulating film comprises a probe station, an electrical testing device and a computer;
the probe platform comprises a sample platform, an optical microscope, two XYZ three-way probe moving platforms and two conductive test probes, wherein the XYZ three-way probe moving platforms comprise probe holders and XYZ three-way precise moving mechanisms, the probe holders are used for holding and fixing the conductive test probes, and the XYZ three-way probe moving platforms are used for adjusting the positions of the conductive test probes in X, Y, Z three directions; the sample table is used for placing a nano-scale film sample; the two conductive test probes are used for being electrically connected to the two electrodes on the film sample; the optical microscope is used for observing the position of the tip of the conductive test probe, and accurately moving and reliably contacting the two electrodes on the nano film sample; one end of the conductive test probe is held in the probe holder in an inclined manner.
A conductive test probe characterized by: the conductive test probe is composed of a hollow metal probe needle sleeve, a copper wire and a micro indium ball, and the inner aperture of the metal probe needle sleeve is matched with the diameter of the copper wire, so that the copper wire can just penetrate through the metal probe needle sleeve without shaking; the length of the copper silk thread is greater than that of the metal probe needle sleeve, so that a part of the copper silk thread passing through the metal probe needle sleeve is still exposed out of the metal probe needle sleeve; the copper silk thread penetrates through the metal probe needle sleeve, and the tail end of the metal probe needle sleeve is pressed by a mechanical clamp and then slightly flattened, so that the copper silk thread is fixed in the metal probe needle sleeve and cannot slide out; the copper wire is exposed out of one end of the metal probe needle sleeve and welded with a micro indium ball, and the micro indium ball is contacted with an electrode of the nano film during testing.
The diameter (thickness) of the copper wire and the diameter (mass) of the micro indium ball are selected so that the copper wire exposed out of the metal probe needle sheath can keep a shape without bending down under the gravity action of the micro indium ball when the conductive test probe is fixed in the probe holder in an inclined manner.
Preferably, the diameter of the copper wire is 20-80 microns, namely 0.02-0.08 mm;
preferably, the diameter of the micro indium balls is 150-500 microns, namely 0.15-0.5 mm;
preferably, the length of the part of the copper wire exposed out of the metal probe needle sleeve is 8-20 mm.
Preferably, the conductive test probes are fixed in the probe holders in an inclined manner, and the included angle between the conductive test probes and the horizontal plane is 30-60 °.
The conductive test probes are held in the probe holder in a tilted manner to facilitate observation of their tip position with an optical microscope during adjustment.
The diameter of the copper wire is 20-80 microns, so that the copper wire can keep proper flexibility and is not too rigid, and the copper wire is too small in diameter, so that the copper wire is not rigid and cannot support the micro indium balls to droop automatically; the copper wire with an excessively large diameter has an excessively large rigidity, and the nano film is still damaged during testing.
The length of the part of the copper silk thread exposed out of the metal probe needle sleeve is 8-20 mm, and if the part of the copper silk thread exposed out of the metal probe needle sleeve is too long, the copper silk thread is insufficient in rigidity and cannot support the micro indium ball to droop automatically; if the part of the metal probe needle sleeve is too short, the rigidity of the metal probe needle sleeve is too high, and the nano film can still be damaged during testing.
Because the metal indium is extremely soft, and when the micro indium balls are contacted with the electrodes of the nano film, the micro indium balls are not the traditional sharp probe tips, and are assisted by copper wires, a large number of experiments show that the microspheres made of the material are matched with the dimensional specification parameters, so that the damage to the nano film can be really avoided. None of the existing conductive test probes can damage the film.
The electrical testing apparatus comprises: the voltage signal source is controlled by a computer through the computer interface circuit to generate and output a test voltage signal, the pre-transimpedance amplifier is used for amplifying a weak current passing through a sample to be tested, the input end of the pre-transimpedance amplifier is electrically connected to two electrodes on the sample to be tested through a test cable, and the output end of the pre-transimpedance amplifier is electrically connected to the current measuring device; the current measuring device is used for measuring weak current passing through a sample to be measured, converting an analog measuring result into a digital measuring result through the A/D converter, and feeding the digital measuring result back to the computer through a computer interface circuit of the electrical testing device;
the computer is used for controlling the electrical testing device and receiving and recording the measurement data returned by the electrical testing device.
The pre-transimpedance amplifier comprises: an ASIC, an intermediate voltage amplifier and a rear end voltage amplifier which are used for measuring fA-pA magnitude weak current;
ASIC for measuring fA-pA level weak current, characterized in that: has ten pins; the first pin is a signal input pin and is used for inputting current to be detected; the seventh pin is a power ground pin; the tenth pin is a power supply positive electrode pin; the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the eighth pin and the ninth pin are functional pins and are used for connecting an ASIC peripheral element; the fifth pin is also used as a signal output pin, is used for outputting the amplified voltage and is electrically connected to the input end of the intermediate amplifier;
in the ASIC, two CMOS operational amplifiers, four CMOS transmission gates, seven CMOS inverters, three resistors and two capacitors are included, the amplifying circuit is cut into two paths according to time slice turns through a high-frequency turn-cutting circuit, one path of the amplifying circuit contains signals to be detected and various offset signals, the other path of the amplifying circuit only contains various offset signals, the two paths are multiplexed into one path through a subtraction circuit, the signals to be detected are obtained, various offset signals are eliminated, and various offset signals are effectively filtered out from a signal source by utilizing the method.
Specifically, inside the ASIC, a signal input terminal of the first CMOS transmission gate and a signal input terminal of the third CMOS transmission gate are both electrically connected to a first pin of the ASIC; the signal output end of the third CMOS transmission gate is electrically connected to the power ground end; the signal output end of the first CMOS transmission gate and the inverting input end of the first CMOS operational amplifier are both electrically connected to the second pin of the ASIC, and the third resistor is electrically connected between the non-inverting input end of the first CMOS operational amplifier and the power ground; the signal output end of the first CMOS operational amplifier, the signal input end of the second CMOS transmission gate and the signal input end of the fourth CMOS transmission gate are electrically connected to a third pin of the ASIC; the second CMOS transmission gate is connected with the first resistor in series, the other end of the first resistor and the inverting input end of the second CMOS operational amplifier are both electrically connected to a fourth pin of the ASIC, and the first capacitor is electrically connected between the common end of the second CMOS transmission gate and the first resistor and the power ground end; the signal output end of the second CMOS operational amplifier is electrically connected to the fifth pin of the ASIC; the fourth CMOS transmission gate is connected with the second resistor in series, the other end of the second resistor and the non-inverting input end of the second CMOS operational amplifier are both electrically connected to the sixth pin of the ASIC, and the power ground end is electrically connected to the seventh pin of the ASIC; the first CMOS inverter, the second CMOS inverter, the third CMOS inverter, the fourth CMOS inverter, the fifth CMOS inverter, the sixth CMOS inverter and the seventh CMOS inverter are sequentially connected in series, the input end of the first CMOS inverter is electrically connected to the eighth pin of the ASIC, and the output end of the first CMOS inverter and the input end of the second CMOS inverter are both electrically connected to the ninth pin of the ASIC; the output end of the third CMOS inverter is also electrically connected to the inverting control end of the third CMOS transmission gate; the output end of the fourth CMOS inverter is also electrically connected to the positive phase control end of the first CMOS transmission gate; the output end of the sixth CMOS inverter is also electrically connected to the positive phase control end of the second CMOS transmission gate; the output end of the seventh CMOS inverter is also electrically connected to the inverting control end of the fourth CMOS transmission gate; the positive power supply terminal is electrically connected to the tenth pin of the ASIC.
In actual operation, a resistor with M omega magnitude and a crystal oscillator are connected in parallel between the input end and the output end of the first CMOS inverter, namely between the eighth pin and the ninth pin of the ASIC, the resistor with M omega magnitude is in an amplification area through feedback action to force the first CMOS inverter to be incapable of normally operating in a switch state, and is not used as a digital circuit, the resistor has the effect that the operating point of the first CMOS inverter is basically half of the power voltage, so that the first CMOS inverter is located in a linear amplification area to form an amplifier with large amplification factor to generate oscillation, and the oscillation frequency depends on the resonance frequency of the crystal oscillator.
A seventh pin of the ASIC is connected to the power ground terminal, and a tenth pin of the ASIC is connected to the positive power terminal; a first pin of the ASIC is used as a current signal input end to be detected and used for inputting current to be detected; a fifth pin of the ASIC is used as an amplified voltage signal output end and used for inputting an amplified voltage signal; a first feedback resistor is connected between a second pin and a third pin of the ASIC in parallel, a second feedback resistor is connected between a fourth pin and a fifth pin of the ASIC in parallel, and a third feedback resistor is connected between a sixth pin of the ASIC and a power ground in series.
The resonance frequency of the crystal oscillator is in the order of MHz, preferably the resonance frequency of the crystal oscillator is 1-100MHz, more preferably the resonance frequency of the crystal oscillator is 10-100 MHz; according to the circuit simulation result, when the frequency of an external clock signal is too low, various offset signals and noise signals are difficult to effectively eliminate; when the frequency of an external clock signal is too high, extra digital noise is brought to a following circuit, the switching characteristic of each CMOS transmission gate under ultrahigh frequency is poor, the frequency response characteristic of an operational amplifier is also poor, and the signal output begins to obviously deviate from an ideal state; CMOS circuits using ultra-high frequencies can overcome the above problems to some extent, but at a significant cost increase. In general, a more preferred crystal oscillator has a resonant frequency of 10-100 MHz.
More preferably, the ASIC is removed from the electrical testing apparatus and integrated into the XYZ three-way probe translation stage of the probe station.
By adopting the pre-amplification circuit, the amplification circuit is cut into two paths according to the time slice by the high-frequency cutting circuit, and then the two paths are combined into one by the subtraction circuit, so that the interference signals are effectively filtered from the signal source by using the mode, the useful signal to be detected is extracted and amplified as much as possible, the signal-to-noise ratio is improved, the noise is effectively inhibited, and the leakage current characteristic of the insulating film, namely the voltage-current characteristic curve is accurately measured and obtained.
Meanwhile, the ASIC specially designed in the invention is adopted in the fA-pA magnitude weak current insulation film measuring system, so that on one hand, the integration level of devices is improved, and various difficulties caused by adopting discrete elements to build a circuit and debug the circuit are avoided.
The ASIC chip has the advantages that the unique advantages of the CMOS process can be utilized to strictly proportion the resistance and capacitance elements involved in the chip, and the output signal is ensured to strictly accord with the theoretical analysis value. When discrete components are adopted, values of various resistors and capacitors have dispersity, even if the values of the resistors or capacitors with the same nominal value have a difference of 20-5%, when a measurement system is produced, the components need to be selected accurately, the debugging work is heavy and easy to get wrong, and the accuracy of an output result is difficult to ensure.
Matters not specifically described in the present specification are within the routine skill of those skilled in the art and need not be further disclosed.
Description of the drawings:
FIG. 1: the invention discloses a schematic diagram of a system for measuring the voltage-current characteristics of a nanometer insulating film;
FIG. 2: the conductive test probe of the present invention;
FIG. 3: a practical application circuit diagram of an ASIC in the electrical test apparatus of the present invention;
FIG. 4: an internal circuit diagram of an ASIC in an electrical test apparatus of the present invention.
Detailed Description
For the convenience of understanding, the technical scheme of the invention is specifically described by combining the examples.
As shown in fig. 1, a system for measuring voltage-current characteristics of a nano-scale insulation film comprises a probe station, an electrical testing device and a computer;
the probe platform comprises a sample platform, an optical microscope, two XYZ three-way probe moving platforms and two conductive test probes, wherein the XYZ three-way probe moving platforms comprise probe holders and XYZ three-way precise moving mechanisms, the probe holders are used for holding and fixing the conductive test probes, and the XYZ three-way probe moving platforms are used for adjusting the positions of the conductive test probes in X, Y, Z three directions; the sample table is used for placing a nano-scale film sample; the two conductive test probes are used for being electrically connected to the two electrodes on the film sample; the optical microscope is used for observing the position of the tip of the conductive test probe, and accurately moving and reliably contacting the two electrodes on the nano film sample; one end of the conductive test probe is held in the probe holder in an inclined manner.
As shown in fig. 2, the conductive test probe is composed of a hollow metal probe needle sleeve a, a copper wire B and a micro indium ball C, and the inner aperture of the metal probe needle sleeve is matched with the diameter of the copper wire, so that the copper wire just passes through the metal probe needle sleeve without shaking; the length of the copper silk thread is greater than that of the metal probe needle sleeve, so that a part of the copper silk thread passing through the metal probe needle sleeve is still exposed out of the metal probe needle sleeve; the copper silk thread penetrates through the metal probe needle sleeve, and the tail end of the metal probe needle sleeve is pressed by a mechanical clamp and then slightly flattened, so that the copper silk thread is fixed in the metal probe needle sleeve and cannot slide out, as indicated by an arrow in fig. 2; the copper wire is exposed out of one end of the metal probe needle sleeve and welded with a micro indium ball, and the micro indium ball is contacted with an electrode of the nano film during testing.
The diameter (thickness) of the copper wire and the diameter (mass) of the micro indium ball are selected so that the copper wire exposed out of the metal probe needle sheath can keep a shape without bending down under the gravity action of the micro indium ball when the conductive test probe is fixed in the probe holder in an inclined manner.
In one embodiment, the copper wire has a diameter of 50 microns, i.e. 0.05 mm;
in one embodiment, the micro indium balls have a diameter of 250 microns, i.e., 0.25 mm;
in one embodiment, the length of the portion of the copper wire exposed out of the needle sheath of the metal probe is 10 mm.
In one embodiment, the conductive test probes are held in the probe holder in an inclined manner, with the conductive test probes being at an angle of 50 ° to the horizontal.
During testing, the XYZ three-way probe moving platform is firstly adjusted through observation of an optical microscope, when the micro indium balls of the conductive testing probe just reach the electrode of the nano film, the three-way probe moving platform is slightly adjusted to move downwards in the Z direction, the micro indium balls stop moving slightly in the horizontal plane of the electrode surface of the nano film, and then the electrical testing is started.
The electrical testing apparatus comprises: the voltage signal source is controlled by a computer through the computer interface circuit to generate and output a test voltage signal, the pre-transimpedance amplifier is used for amplifying a weak current passing through a sample to be tested, the input end of the pre-transimpedance amplifier is electrically connected to two electrodes on the sample to be tested through a test cable, and the output end of the pre-transimpedance amplifier is electrically connected to the current measuring device; the current measuring device is used for measuring weak current passing through a sample to be measured, converting an analog measuring result into a digital measuring result through the A/D converter, and feeding the digital measuring result back to the computer through a computer interface circuit of the electrical testing device;
as shown in fig. 3, the ASIC for measuring weak current in the fA-pA order is characterized in that: has ten pins; the first pin is a signal input pin and is used for inputting current to be detected; the seventh pin is a power ground pin; the tenth pin is a power supply positive electrode pin; the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the eighth pin and the ninth pin are functional pins and are used for connecting an ASIC peripheral element; the fifth pin is also used as a signal output pin for outputting the amplified voltage and is electrically connected to the input end of the intermediate amplifier.
When the ASIC is used for measuring fA-pA magnitude weak current, the circuit connection mode is as follows: the eighth pin and the ninth pin of the ASIC are respectively connected with a capacitor C3、C4And a resistor R in the M omega magnitude and a crystal oscillator are connected between the eighth pin and the ninth pin of the ASIC in parallel, and the resistor R in the M omega magnitude can force the first CMOS inverter inside the ASIC to be in an amplification region through a feedback effect, and the amplification region is shown in figure 4. The resistor is used for making the working point of the first CMOS inverter be substantially half of the power supply voltage, so that the first CMOS inverter is located in a linear amplification area to form an amplifier with large amplification factor and generate oscillation, and the oscillation frequency is dependent on the resonance frequency of the crystal oscillator.
A seventh pin of the ASIC is connected to the power ground terminal, and a tenth pin of the ASIC is connected to the positive power terminal; a first pin of the ASIC is used as a current signal input end to be detected and used for inputting current to be detected; a fifth pin of the ASIC is used as an amplified voltage signal output end and used for inputting an amplified voltage signal; a first feedback resistor R is connected in parallel between the second pin and the third pin of the ASICf1The fourth pin and the fifth pin of the ASIC are connected in parallelSecond feedback resistor Rf2A third feedback resistor R is connected between the sixth pin of the ASIC and the power ground in seriesf3。
Therefore, the ASIC of the invention needs few peripheral elements, greatly reduces the design cost, improves the design speed of the measurement system and greatly improves the reliability of the system.
As shown in fig. 4, the ASIC includes two CMOS operational amplifiers, four CMOS transmission gates, seven CMOS inverters, three resistors, and two capacitors, the amplifying circuit is switched into two paths by the high-frequency switch circuit according to the time slice, one path includes a signal to be measured and various offset signals, the other path includes various offset signals, and the two paths are multiplexed into one by the subtraction circuit to obtain the signal to be measured, thereby eliminating various offset signals.
Specifically, inside the ASIC, a signal input terminal of the first CMOS transmission gate and a signal input terminal of the third CMOS transmission gate are both electrically connected to a first pin of the ASIC; the signal output end of the third CMOS transmission gate is electrically connected to the power ground end; the signal output end of the first CMOS transmission gate and the inverting input end of the first CMOS operational amplifier A1 are both electrically connected to the second pin of the ASIC, and the third resistor is electrically connected between the non-inverting input end of the first CMOS operational amplifier A1 and the power ground; the signal output end of the first CMOS operational amplifier A1, the signal input end of the second CMOS transmission gate and the signal input end of the fourth CMOS transmission gate are electrically connected to a third pin of the ASIC; the second CMOS transmission gate is connected with the first resistor in series, the other end of the first resistor and the inverting input end of the second CMOS operational amplifier are both electrically connected to a fourth pin of the ASIC, and the first capacitor is electrically connected between the common end of the second CMOS transmission gate and the first resistor and the power ground end; the signal output end of the second CMOS operational amplifier is electrically connected to the fifth pin of the ASIC; the fourth CMOS transmission gate is connected with the second resistor in series, the other end of the second resistor and the non-inverting input end of the second CMOS operational amplifier are both electrically connected to the sixth pin of the ASIC, and the power ground end is electrically connected to the seventh pin of the ASIC; the first CMOS inverter, the second CMOS inverter, the third CMOS inverter, the fourth CMOS inverter, the fifth CMOS inverter, the sixth CMOS inverter and the seventh CMOS inverter are sequentially connected in series, the input end of the first CMOS inverter is electrically connected to the eighth pin of the ASIC, and the output end of the first CMOS inverter and the input end of the second CMOS inverter are both electrically connected to the ninth pin of the ASIC; the output end of the third CMOS inverter is also electrically connected to the inverting control end of the third CMOS transmission gate; the output end of the fourth CMOS inverter is also electrically connected to the positive phase control end of the first CMOS transmission gate; the output end of the sixth CMOS inverter is also electrically connected to the positive phase control end of the second CMOS transmission gate; the output end of the seventh CMOS inverter is also electrically connected to the inverting control end of the fourth CMOS transmission gate; the positive power supply terminal is electrically connected to the tenth pin of the ASIC.
The four CMOS transmission gates work in an on-off state; under the condition of not considering the transmission time delay of each inverter, the first CMOS transmission gate and the second CMOS transmission gate are simultaneously opened or closed, the third CMOS transmission gate and the fourth CMOS transmission gate are simultaneously closed or opened, and the on-off states of the first CMOS transmission gate and the second CMOS transmission gate are always opposite to the on-off states of the third CMOS transmission gate and the CMOS transmission gate, namely when the first CMOS transmission gate and the second CMOS transmission gate are in an on low-resistance state, the third CMOS transmission gate and the fourth CMOS transmission gate are both in an off state, and vice versa.
Optionally, 2N series-connected CMOS inverters may be further added between the fifth CMOS inverter and the sixth CMOS inverter, where N is a positive integer, and a value of N is determined by an actual response speed of the first CMOS operational amplifier a 1.
As shown in fig. 4, the virtual equivalent model of the first CMOS operational amplifier A1a1 is shown in the large dashed box, and the ideal operational amplifier A1' is shown in the small dashed box, and the virtual equivalent offset voltage UI0, the virtual input bias current Ib-, Ib + of the virtual first CMOS operational amplifier A1, and the virtual input bias current Ib-, Ib + of the virtual first CMOS operational amplifier are shown in the virtual equivalent modelfilmIs the leakage current to be measured in the insulating film.
When the first CMOS transmission gate TG1And a second CMOS transmission gate TG2Simultaneously in a conducting low-resistance state and a third CMOS transmission gate TG3And a fourth CMOS transmission gate TG4When both are in the cut-off state, the first capacitor C1The voltages on are:
UCl＝-IfilmRf1+UI0+Ib+R3+Ib-Rf1(1)
when the first CMOS transmission gate TG1And a second CMOS transmission gate TG2Third CMOS transmission gate TG being in cut-off state at the same time3And a fourth CMOS transmission gate TG4When the two capacitors are in a conducting low-resistance state, the second capacitor C2The voltages on are:
UC2＝-UI0+Ib+R3+Ib-Rf1(2)
in ASIC manufacture process, the first capacitance C is determined by reasonably selecting CMOS process1A second capacitor C2A first resistor R1A second resistor R2A third resistor R3The values of (a) satisfy the following conditions:
reasonably selecting the first capacitor C1A second capacitor C2A first resistor R1A second resistor R2A third resistor R3A first feedback resistor Rf1A second feedback resistor Rf2And a third feedback resistor R3Of the first capacitor C during one clock cycle1A second capacitor C2Substantially constant in value. Therefore, the output voltage value of the second CMOS operational amplifier a2 is:
and get
A first capacitor C1A second capacitor C2After being processed by the second CMOS operational amplifier a2, the output voltage can be obtained by simple calculation as follows:
it can be seen that, by using the pre-transimpedance amplifier according to the present invention,various input offset voltages and input bias currents of the operational amplifier are eliminated. Under a given circuit, the output voltage signal value of the pre-transimpedance amplifier is proportional to the leakage current of the insulating film. The leakage current of the insulating film is usually in the range of several tens of fA (10)-15A) To tens of pA (10)- 12A) The output voltage of the preposed trans-impedance amplifier can reach several mu V to dozens of mu V by reasonably selecting the value of an external element, the output voltage signal is successively amplified by the middle voltage amplifier and the rear voltage amplifier, can be accurately measured by the current measuring device, and finally is sent back to the computer for processing and displaying.
The computer controls the voltage signal source through the software control program to generate a series of voltage signals to be applied on the film sample, the electric testing device measures the leakage current value of the film sample under the series of voltage signals and transmits the leakage current value back to the computer, the computer stores the measured values, and the leakage current characteristic of the insulating film, namely a voltage-current characteristic curve, is displayed on the screen.
A more preferred embodiment is to integrate the ASIC described above in the XYZ three-way probe translation stage of the probe station.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and it should be noted that any equivalent substitution, obvious modification made by those skilled in the art under the teaching of the present specification are within the spirit scope of the present specification, and the present invention should be protected.
Claims (6)
1. An ASIC for measuring fA-pA magnitude weak current, characterized in that:
the ASIC has ten pins; the first pin is a signal input pin and is used for inputting current to be detected; the seventh pin is a power ground pin; the tenth pin is a power supply positive electrode pin; the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the eighth pin and the ninth pin are functional pins and are used for connecting an ASIC peripheral element; the fifth pin is also used as a signal output pin, is used for outputting the amplified voltage and is electrically connected to the input end of the intermediate amplifier;
the ASIC comprises an amplifying circuit consisting of two CMOS operational amplifiers, four CMOS transmission gates, seven CMOS inverters, three resistors and two capacitors; a seventh pin of the ASIC is connected to the power ground terminal, and a tenth pin of the ASIC is connected to the positive power terminal; a first pin of the ASIC is used as a current signal input end to be detected and used for inputting current to be detected; a fifth pin of the ASIC is used as an amplified voltage signal output end and used for inputting an amplified voltage signal; a first feedback resistor is connected between a second pin and a third pin of the ASIC in parallel, a second feedback resistor is connected between a fourth pin and a fifth pin of the ASIC in parallel, and a third feedback resistor is connected between a sixth pin of the ASIC and a power ground in series; a resistor with M omega magnitude is connected between the eighth pin and the ninth pin of the ASIC in parallel and a crystal oscillator, the resistor with M omega magnitude enables the first CMOS inverter to be in a linear amplification region to form an amplifier to generate oscillation, and the oscillation frequency depends on the resonance frequency of the crystal oscillator;
the amplifying circuit is cut into two paths according to the time slice by a high-frequency cutting circuit, wherein one path of output signals comprises current signals to be detected and interference signals, and the other path of output signals only comprises the interference signals and does not comprise the current signals to be detected; and then the signal is multiplied into one by a subtraction circuit, so that interference signals are filtered, useful signals to be measured are extracted and amplified, the signal-to-noise ratio is improved, noise is effectively inhibited, and the current value to be measured is accurately measured.
2. The ASIC of claim 1, wherein:
inside the ASIC, the signal input end of the first CMOS transmission gate and the signal input end of the third CMOS transmission gate are both electrically connected to the first pin of the ASIC; the first CMOS inverter, the second CMOS inverter, the third CMOS inverter, the fourth CMOS inverter, the fifth CMOS inverter, the sixth CMOS inverter and the seventh CMOS inverter are sequentially connected in series, the input end of the first CMOS inverter is electrically connected to the eighth pin of the ASIC, and the output end of the first CMOS inverter and the input end of the second CMOS inverter are both electrically connected to the ninth pin of the ASIC; the signal output end of the second CMOS operational amplifier is electrically connected to the fifth pin of the ASIC; the signal output end of the first CMOS transmission gate and the inverting input end of the first CMOS operational amplifier are both electrically connected to the second pin of the ASIC, and the third resistor is electrically connected between the non-inverting input end of the first CMOS operational amplifier and the power ground; the signal output end of the first CMOS operational amplifier, the signal input end of the second CMOS transmission gate and the signal input end of the fourth CMOS transmission gate are electrically connected to a third pin of the ASIC; the second CMOS transmission gate is connected with the first resistor in series, the other end of the first resistor and the inverting input end of the second CMOS operational amplifier are both electrically connected to a fourth pin of the ASIC, and the first capacitor is electrically connected between the common end of the second CMOS transmission gate and the first resistor and the power ground end; the signal output end of the third CMOS transmission gate is electrically connected to the power ground end; the fourth CMOS transmission gate is connected with the second resistor in series, the other end of the second resistor and the non-inverting input end of the second CMOS operational amplifier are both electrically connected to the sixth pin of the ASIC, and the power ground end is electrically connected to the seventh pin of the ASIC; the output end of the third CMOS inverter is also electrically connected to the inverting control end of the third CMOS transmission gate; the output end of the fourth CMOS inverter is also electrically connected to the positive phase control end of the first CMOS transmission gate; the output end of the sixth CMOS inverter is also electrically connected to the positive phase control end of the second CMOS transmission gate; the output end of the seventh CMOS inverter is also electrically connected to the inverting control end of the fourth CMOS transmission gate; the positive power supply terminal is electrically connected to the tenth pin of the ASIC.
3. The ASIC of claim 2, wherein:
2N CMOS inverters connected in series are arranged between the fifth CMOS inverter and the sixth CMOS inverter, N is a positive integer, and the value of N enables the overall response speed of all the CMOS inverters to be matched with the response speed of the first CMOS operational amplifier.
4. The ASIC of claim 2, wherein:
the first CMOS transmission gate and the second CMOS transmission gate are opened or closed at the same time, the third CMOS transmission gate and the fourth CMOS transmission gate are closed or opened at the same time, and the switching states of the first CMOS transmission gate and the second CMOS transmission gate are always opposite to the switching states of the third CMOS transmission gate and the CMOS transmission gate, namely when the first CMOS transmission gate and the second CMOS transmission gate are in a conducting low-resistance state, the third CMOS transmission gate and the fourth CMOS transmission gate are both in a stopping state, and vice versa.
5. The ASIC of claim 2, wherein:
when the CMOS transmission gate works, the four CMOS transmission gates work in an on-off state; an M omega-level resistor and a crystal oscillator are connected in parallel between the input end and the output end of the first CMOS inverter, namely between the eighth pin and the ninth pin of the ASIC, the M omega-level resistor enables the first CMOS inverter to be positioned in a linear amplification area to form an amplifier to generate oscillation, and the oscillation frequency depends on the resonant frequency of the crystal oscillator; the resonant frequency of the crystal oscillator is in the order of MHz.
6. A voltage-current characteristic measurement system of a nanometer insulating film is characterized in that:
the measurement system comprises an electrical test device comprising an ASIC according to any of claims 1-5.
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| CN201910094590.1A CN109781788B (en) | 2019-01-30 | 2019-01-30 | Nano-scale insulating film voltage-current characteristic measuring system |
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| CN109781788B (en) | 2021-02-26 |
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