CN112688709A - FPGA interface unit, FPGA interface module and FPGA interface system - Google Patents
FPGA interface unit, FPGA interface module and FPGA interface system Download PDFInfo
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- CN112688709A CN112688709A CN202011505041.8A CN202011505041A CN112688709A CN 112688709 A CN112688709 A CN 112688709A CN 202011505041 A CN202011505041 A CN 202011505041A CN 112688709 A CN112688709 A CN 112688709A
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Abstract
The invention provides an FPGA interface unit, which comprises a first sending and receiving channel, a second sending and receiving channel and a clock management unit, wherein the clock management unit is connected with the first sending and receiving channel and the second sending and receiving channel so as to drive the first sending and receiving channel and the second sending and receiving channel. The FPGA interface unit comprises a first sending and receiving channel, a second sending and receiving channel and a clock management unit, wherein the clock management unit is connected with the first sending and receiving channel and the second sending and receiving channel so as to drive the first sending and receiving channel and the second sending and receiving channel, and the two sending and receiving channels share one clock management unit, so that the flexibility of adapting to different protocol standards of the sending and receiving channels is improved. The invention also provides an FPGA interface module and an FPGA interface system.
Description
Technical Field
The invention relates to the technical field of FPGA, in particular to an FPGA interface unit, an FPGA interface module and an FPGA interface system.
Background
In a Field Programmable Gate Array (FPGA), four sending and receiving paths are generally used to share one Clock Management Unit (CMU) to implement a high-speed interface, and each sending and receiving path shares a high-speed Clock signal generated by the Clock management Unit, so as to achieve the purposes of saving the overhead of the Clock management Unit and reducing the power consumption and the area of a system. However, the FPGA is a general-purpose device and needs flexibility to adapt to different protocol standards, and the traditional way of sharing one clock management unit by four transmitting and receiving paths limits the flexibility of application to a certain extent.
Therefore, there is a need to provide a novel FPGA interface unit, a novel FPGA interface module, and a novel FPGA interface system to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide an FPGA interface unit, an FPGA interface module and an FPGA interface system so as to improve the flexibility of adapting a sending channel and a receiving channel to different protocol standards.
In order to achieve the above object, the FPGA interface unit of the present invention includes:
a first transmit and receive path;
a second transmit and receive path; and
and a clock management unit connected to the first transmit and receive path and the second transmit and receive path to drive the first transmit and receive path and the second transmit and receive path.
The FPGA interface unit has the advantages that: the clock management unit is connected with the first sending and receiving channel and the second sending and receiving channel to drive the first sending and receiving channel and the second sending and receiving channel, and the two sending and receiving channels share one clock management unit, so that the flexibility of adapting to different protocol standards of the sending and receiving channels is improved.
Preferably, the FPGA interface unit further includes a first clock recovery unit, a second clock recovery unit, a recovered clock selection unit, and a clock buffer unit, one end of the first clock recovery unit is connected to the first transmitting and receiving path, the other end of the first clock recovery unit is connected to the first input end of the recovered clock selection unit, one end of the second clock recovery unit is connected to the second transmitting and receiving path, the other end of the second clock recovery unit is connected to the second input end of the recovered clock selection unit, the output end of the recovered clock selection unit is connected to the input end of the clock buffer unit, and the output end of the clock buffer unit is used for outputting a recovered clock. The beneficial effects are that: and the output interface resource is saved.
Preferably, the FPGA interface unit further includes a first clock recovery unit, a second clock recovery unit, a first clock buffer unit, and a second clock buffer unit, one end of the first clock recovery unit is connected to the first transmitting and receiving path, the other end of the first clock recovery unit is connected to the input end of the first clock buffer unit, one end of the second clock recovery unit is connected to the second transmitting and receiving path, the other end of the second clock recovery unit is connected to the second clock buffer unit, and the output end of the first clock buffer unit and the output end of the second clock buffer unit are used for outputting a recovered clock. The beneficial effects are that: the method is convenient for saving output interface resources and can simultaneously output the recovered clocks of the first sending and receiving path and the second sending and receiving path.
Preferably, the first transmit and receive path and the second transmit and receive path each include a transmit path and a receive path.
The invention also provides an FPGA interface module, comprising:
the number of the FPGA interface units is 2; and
and the clock selection unit is connected with the two FPGA interface units.
The FPGA interface module has the beneficial effects that: the clock selection unit is connected with the two FPGA interface units, and the clocks of the two FPGA units are the same or different, so that the flexibility of adapting to different protocol standards of the sending and receiving channels is improved.
Preferably, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the output end of the first selection unit is connected with the clock management unit of one FPGA interface unit and the first input end of the fourth selection unit, the first input terminal of the first selection unit and the second input terminal of the third selection unit are connected with the same or different off-chip clock units, the second input end of the first selection unit is connected with the output end of the second selection unit, the first input end of the second selection unit and the second input end of the fourth selection unit are connected with the same or different on-chip clock units, the output end of the third selection unit is connected with the clock management unit of another FPGA interface unit and the second input end of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
Preferably, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the output end of the first selection unit is connected with the clock management unit of one FPGA interface unit and the first input end of the fourth selection unit, the first input end of the first selection unit and the second input end of the third selection unit are connected with the same or different on-chip clock units, the second input end of the first selection unit is connected with the output end of the second selection unit, the first input end of the second selection unit and the second input end of the fourth selection unit are connected with the same or different off-chip clock units, the output end of the third selection unit is connected with the clock management unit of another FPGA interface unit and the second input end of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
Preferably, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the output end of the first selection unit is connected with the clock management unit of one FPGA interface unit and the first input end of the fourth selection unit, the first input end of the first selection unit and the second input end of the fourth selection unit are connected with the same or different on-chip clock units, the second input end of the first selection unit is connected with the output end of the second selection unit, the second input end of the third selection unit and the first input end of the second selection unit are connected with the same or different off-chip clock units, the output end of the third selection unit is connected with the clock management unit of another FPGA interface unit and the second input end of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
Preferably, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the output end of the first selection unit is connected with the clock management unit of one FPGA interface unit and the first input end of the fourth selection unit, the first input terminal of the first selection unit and the second input terminal of the fourth selection unit are connected with the same or different off-chip clock units, the second input end of the first selection unit is connected with the output end of the second selection unit, the second input end of the third selection unit and the first input end of the second selection unit are connected with the same or different on-chip clock units, the output end of the third selection unit is connected with the clock management unit of another FPGA interface unit and the second input end of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
The invention also provides an FPGA interface system which comprises at least one FPGA interface module.
The FPGA interface system has the advantages that: the FPGA interface module is used for improving the flexibility of adapting to different protocol standards of a transmitting and receiving channel in the FPGA.
Drawings
FIG. 1 is a block diagram of an FPGA interface system in some embodiments of the present invention;
FIG. 2 is a block diagram of an FPGA interface module in some embodiments of the present invention;
FIG. 3 is a schematic circuit diagram of a clock selection unit according to some embodiments of the present invention;
FIG. 4 is a block diagram of an FPGA interface unit in some embodiments of the present invention;
FIG. 5 is a block diagram of an FPGA interface unit in accordance with still further embodiments of the present invention;
fig. 6 is a block diagram of an FPGA interface unit according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides an FPGA interface system, and referring to fig. 1, the FPGA interface system 10 includes at least one FPGA interface module 101.
Fig. 2 is a block diagram of an FPGA interface module in some embodiments of the invention. Referring to fig. 2, the FPGA interface module 101 includes FPGA interface units 1011 and clock selection units 1012, the number of the FPGA interface units 1011 is 2, the number of the clock selection units 1012 is 1, and both the FPGA interface units 1011 are connected to the clock selection units 1012.
Fig. 3 is a circuit diagram of a clock selection unit according to some embodiments of the invention. Referring to fig. 3, the clock selection unit 1012 includes a first selection unit 10121, a second selection unit 10122, a third selection unit 10123, and a fourth selection unit 10124, an output terminal of the first selection unit 10121 is connected to a clock management unit (not shown) of one of the FPGA interface units and a first input terminal of the fourth selection unit 10124, a first input terminal of the first selection unit 12121 and a second input terminal of the third selection unit 10123 are connected to the same or different off-chip clock units, a second input terminal of the first selection unit 10121 is connected to an output terminal of the second selection unit 10122, a first input terminal of the second selection unit 10122 and a second input terminal of the fourth selection unit 10124 are connected to the same or different on-chip clock units, an output terminal of the third selection unit 10123 is connected to a clock management unit (not shown) of another FPGA interface unit and a second input terminal of the second selection unit 10122, a first input of the third selection unit 10123 is connected to an output of the fourth selection unit 10124.
In some further specific embodiments, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, an output end of the first selection unit is connected to a clock management unit of one of the FPGA interface units and a first input end of the fourth selection unit, a first input end of the first selection unit and a second input end of the third selection unit are connected to the same or different on-chip clock units, a second input end of the first selection unit is connected to an output end of the second selection unit, a first input end of the second selection unit and a second input end of the fourth selection unit are connected to the same or different off-chip clock units, an output end of the third selection unit is connected to a clock management unit of another FPGA interface unit and a second input end of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
In other specific embodiments, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit, and a fourth selection unit, an output end of the first selection unit is connected to a clock management unit of one of the FPGA interface units and a first input end of the fourth selection unit, a first input end of the first selection unit and a second input end of the fourth selection unit are connected to the same or different on-chip clock units, a second input end of the first selection unit is connected to an output end of the second selection unit, a second input end of the third selection unit and a first input end of the second selection unit are connected to the same or different off-chip clock units, and an output end of the third selection unit is connected to a second input end of the clock management unit and the second selection unit of another FPGA interface unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
In still other specific embodiments, the clock selection unit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, an output end of the first selection unit is connected to a clock management unit of one of the FPGA interface units and a first input end of the fourth selection unit, a first input end of the first selection unit and a second input end of the fourth selection unit are connected to the same or different off-chip clock units, a second input end of the first selection unit is connected to an output end of the second selection unit, a second input end of the third selection unit and a first input end of the second selection unit are connected to the same or different on-chip clock units, and an output end of the third selection unit is connected to a second input end of the second selection unit and a clock management unit of another FPGA interface unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
In some embodiments, the control terminals of the first selecting unit, the second selecting unit, the third selecting unit and the fourth selecting unit are used for accessing a reference clock selecting signal.
Fig. 4 is a block diagram of an FPGA interface unit in some embodiments of the invention. Referring to fig. 4, the FPGA interface unit 1011 includes a first transmitting and receiving path 10111, a second transmitting and receiving path 10112, and a clock management unit 10113, and the clock management unit 10113 is connected to the first transmitting and receiving path 10111 and the second transmitting and receiving path 10112 to drive the first transmitting and receiving path 10111 and the second transmitting and receiving path 10112.
Fig. 5 is a block diagram of an FPGA interface unit in further embodiments of the present invention. Referring to fig. 5, the FPGA interface unit 1011 includes a first transmitting and receiving path 10111, a second transmitting and receiving path 10112, a clock management unit 10113, a first clock recovery unit 10114, a second clock recovery unit 10115, a recovered clock selection unit 10116, and a clock buffer unit 10117, the clock management unit 10113 is connected to the first transmitting and receiving path 10111 and the second transmitting and receiving path 10112 to realize driving of the first transmitting and receiving path 10111 and the second transmitting and receiving path 10112, one end of the first clock recovery unit 10114 is connected to the first transmitting and receiving path 10111, the other end of the first clock recovery unit 10114 is connected to a first input terminal of the recovered clock selection unit 10116, one end of the second clock recovery unit 10115 is connected to the second transmitting and receiving path 10112, and the other end of the second clock recovery unit 10115 is connected to a second input terminal of the recovered clock selection unit 10116, an output terminal of the recovered clock selecting unit 10116 is connected to an input terminal of the clock buffering unit 10117, and an output terminal of the clock buffering unit 10117 is used for outputting a recovered clock, wherein the clock buffering unit 10117 has a positive output terminal and a negative output terminal. Specifically, the first clock recovery unit 10114 and the second clock recovery unit 10115 recover clocks from input data of the first transmission and reception path 10111 and the second transmission and reception path 10112 through a clock data recovery algorithm (CDR).
Fig. 6 is a block diagram of an FPGA interface unit according to another embodiment of the present invention. Referring to fig. 6, the FPGA interface unit 1011 includes a first transmitting and receiving path 10111, a second transmitting and receiving path 10112, a clock management unit 10113, a first clock recovery unit 10114, a second clock recovery unit 10115, a first clock buffer unit 10118, and a second clock buffer unit 10119, the clock management unit 10113 is connected to the first transmitting and receiving path 10111 and the second transmitting and receiving path 10112 to drive the first transmitting and receiving path 10111 and the second transmitting and receiving path 10112, one end of the first clock recovery unit 10114 is connected to the first transmitting and receiving path 10111, the other end of the first clock recovery unit 10114 is connected to an input end of the first clock buffer unit 10118, one end of the second clock recovery unit 10115 is connected to the second transmitting and receiving path 10112, and the other end of the second clock recovery unit 10115 is connected to the second clock buffer unit 10119, an output terminal of the first clock buffer unit 10118 and an output terminal of the second clock buffer unit 10119 are used for outputting a recovered clock, wherein the first clock buffer unit 10118 and the second clock buffer unit 10119 each have a positive output terminal and a negative output terminal. Specifically, the first clock recovery unit 10114 and the second clock recovery unit 10115 recover clocks from input data of the first transmission and reception path 10111 and the second transmission and reception path 10112 through a clock data recovery algorithm (CDR).
In some embodiments, the first transmit and receive path and the second transmit and receive path each comprise a transmit path and a receive path.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. An FPGA interface cell, comprising:
a first transmit and receive path;
a second transmit and receive path; and
and a clock management unit connected to the first transmit and receive path and the second transmit and receive path to drive the first transmit and receive path and the second transmit and receive path.
2. The FPGA interface unit of claim 1, further comprising a first clock recovery unit, a second clock recovery unit, a recovered clock selection unit, and a clock buffer unit, wherein one end of the first clock recovery unit is connected to the first transmitting and receiving path, the other end of the first clock recovery unit is connected to the first input end of the recovered clock selection unit, one end of the second clock recovery unit is connected to the second transmitting and receiving path, the other end of the second clock recovery unit is connected to the second input end of the recovered clock selection unit, the output end of the recovered clock selection unit is connected to the input end of the clock buffer unit, and the output end of the clock buffer unit is used for outputting a recovered clock.
3. The FPGA interface unit of claim 1, further comprising a first clock recovery unit, a second clock recovery unit, a first clock buffer unit, and a second clock buffer unit, wherein one end of the first clock recovery unit is connected to the first transmitting and receiving path, the other end of the first clock recovery unit is connected to an input end of the first clock buffer unit, one end of the second clock recovery unit is connected to the second transmitting and receiving path, the other end of the second clock recovery unit is connected to the second clock buffer unit, and an output end of the first clock buffer unit and an output end of the second clock buffer unit are used for outputting a recovered clock.
4. The FPGA interface unit of any one of claims 1-3, wherein the first and second transmit and receive paths each comprise a transmit path and a receive path.
5. An FPGA interface module, comprising:
the FPGA interface unit of any one of claims 1-4, the number of the FPGA interface units being 2; and
and the clock selection unit is connected with the two FPGA interface units.
6. The FPGA interface module of claim 5, wherein the clock selection unit comprises a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, an output terminal of the first selection unit is connected to a clock management unit of one FPGA interface unit and a first input terminal of the fourth selection unit, the first input terminal of the first selection unit and a second input terminal of the third selection unit are connected to the same or different off-chip clock units, the second input terminal of the first selection unit is connected to an output terminal of the second selection unit, the first input terminal of the second selection unit and a second input terminal of the fourth selection unit are connected to the same or different on-chip clock units, and an output terminal of the third selection unit is connected to a clock management unit of another FPGA interface unit and a second input terminal of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
7. The FPGA interface module of claim 5, wherein the clock selection unit comprises a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, an output terminal of the first selection unit is connected to a clock management unit of one FPGA interface unit and a first input terminal of the fourth selection unit, the first input terminal of the first selection unit and a second input terminal of the third selection unit are connected to the same or different on-chip clock units, the second input terminal of the first selection unit is connected to an output terminal of the second selection unit, the first input terminal of the second selection unit and a second input terminal of the fourth selection unit are connected to the same or different off-chip clock units, and an output terminal of the third selection unit is connected to a clock management unit of another FPGA interface unit and a second input terminal of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
8. The FPGA interface module of claim 5, wherein the clock selection unit comprises a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, an output terminal of the first selection unit is connected to a clock management unit of one FPGA interface unit and a first input terminal of the fourth selection unit, the first input terminal of the first selection unit and a second input terminal of the fourth selection unit are connected to the same or different on-chip clock units, the second input terminal of the first selection unit is connected to an output terminal of the second selection unit, the second input terminal of the third selection unit and the first input terminal of the second selection unit are connected to the same or different off-chip clock units, and an output terminal of the third selection unit is connected to a clock management unit of another FPGA interface unit and a second input terminal of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
9. The FPGA interface module of claim 5, wherein the clock selection unit comprises a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, an output terminal of the first selection unit is connected to a clock management unit of one FPGA interface unit and a first input terminal of the fourth selection unit, a first input terminal of the first selection unit and a second input terminal of the fourth selection unit are connected to the same or different off-chip clock units, a second input terminal of the first selection unit is connected to an output terminal of the second selection unit, a second input terminal of the third selection unit and a first input terminal of the second selection unit are connected to the same or different on-chip clock units, and an output terminal of the third selection unit is connected to a clock management unit of another FPGA interface unit and a second input terminal of the second selection unit, and the first input end of the third selection unit is connected with the output end of the fourth selection unit.
10. An FPGA interface system comprising at least one FPGA interface module according to any one of claims 5 to 9.
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