CN111105744A - Embedded display port implementation method and system based on programmable logic - Google Patents
Embedded display port implementation method and system based on programmable logic Download PDFInfo
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- CN111105744A CN111105744A CN201911416045.6A CN201911416045A CN111105744A CN 111105744 A CN111105744 A CN 111105744A CN 201911416045 A CN201911416045 A CN 201911416045A CN 111105744 A CN111105744 A CN 111105744A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The invention discloses a method and a system for realizing an embedded display port interface based on programmable logic, wherein the method comprises the following steps: preprocessing link training and establishing connection with a receiving end; selecting a link training mode to realize switching of different training modes of the embedded display port; packaging the video frames; serially transmitting data, controlling a hard core IP high-speed serial transceiver by using a programmable logic device, realizing the function of an embedded display port physical layer, starting 8B/10B coding, notifying to transmit a video data packet after system resetting, and performing data acquisition on the video data packet by using a clock generated by a gigabit high-speed transceiver; meanwhile, the problem of inconsistent electrical interfaces is solved by processing the voltage swing and the pre-emphasis. The embedded display port implementation method and system based on the programmable logic can reduce the utilization rate of logic resources and reduce power loss at the same time. The invention can not only operate the high-speed signal transceiver, but also flexibly process the service flow under different environments.
Description
Technical Field
The invention belongs to the technical field of data communication, relates to an interface implementation method, and particularly relates to an embedded display port interface implementation method and system based on programmable logic.
Background
The current video resolution has entered the 4K/8K high definition field; the maximum transmission rate of each channel of the embedded display port (a communication interface of the liquid crystal display) can reach 5.4 Gbps/lanes. The electrical performance consistency cannot be guaranteed due to the embedded displayport physical link and is unpredictable in view of the external environment. The link training is required before video transmission to ensure that effective video transmission can be realized under the set bandwidth and the limited channel number.
For the embedded display port, not only the flow control and various flow effect evaluations of each link of link training are considered, but also the high-speed signal operation is carried out on the main link; the existing embedded display port implementation mode can not meet two requirements at the same time.
In view of the above, there is a need to design an embedded displayport implementation so as to overcome the above-mentioned drawbacks of the existing embedded displayport implementation.
Disclosure of Invention
The invention provides a method and a system for realizing an embedded display port based on programmable logic, which can reduce the utilization rate of logic resources and reduce power loss.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a method for realizing an embedded display port based on programmable logic comprises the following steps:
step S1, preprocessing the link training and establishing connection with the receiving end;
step S2, selecting a link training mode to realize the switching of different training modes of the embedded display port;
step S3, packaging the video frame; the packet content comprises idle frame insertion, attribute data packet insertion, transmission unit packet insertion, data scrambling and adjacent channel inclination;
s4, serially transmitting data, controlling a hardmac IP high-speed serial transceiver by using a programmable logic device to realize the function of an embedded display port physical layer, starting 8B/10B coding, notifying to transmit a video data packet after system reset, and performing data acquisition on the video data packet by using a clock generated by a gigabit high-speed transceiver; meanwhile, the problem of inconsistent electrical interfaces is solved by processing the voltage swing and the pre-emphasis.
In an embodiment of the present invention, in step S1, the two state machines are respectively sent to the EDID parsing module and the DPCD parsing module; the two analysis modules perform analysis processing, and the optimal communication mode of the receiving end is selected to establish connection; to improve transmission efficiency performance, the EDID state machine and DPCD state machine may be skipped for fast link training if the embedded displayport resolution is known. The design mode jumps out of complex and tedious communication interaction between the sending end and the receiving end, and saves training time.
In one embodiment of the present invention, in step S2, the first training mode and the second training mode are transmitted as default states. And when the third training mode is detected to be effective, sending the first training mode and the third training mode. And integrating the three training mode sending data into a frame packaging module. The first two steps are effective to run the third step.
In one embodiment of the present invention, a pipeline processing method is used in step S3.
In one embodiment of the present invention, the steps S3 and S4 are performed simultaneously.
According to another aspect of the invention, the following technical scheme is adopted: a programmable logic based embedded displayport system, the embedded displayport system comprising:
the first IP soft core is used for preprocessing the link training; the embedded display port auxiliary channel is realized, the connection between the sending end and the receiving end equipment is established, and the function detection, the effect evaluation and the power consumption control of the channel are realized;
the second IP soft core is used for selecting a link training mode and realizing the switching of different training modes of the embedded display port;
the interface link module is used for realizing an embedded display port link layer, and the functions of the link layer comprise a data frame wrapper, a scrambler and a buffer;
the high-speed serial transceiver is used for realizing an embedded display port physical layer data channel; the characteristics of physical layer coding, system reset generation and electrical appliance interface inconsistency control are realized.
As an embodiment of the present invention, the preprocessing process of the first IP soft core designs two state machines, which are respectively a decoding EDID state and a decoding DPCD state; and analyzing the receiving end capability of the embedded display port respectively, evaluating, and selecting an optimal mode to carry out parameter configuration.
As an embodiment of the present invention, the link training process of the second IP soft core designs two state machines: a training mode state, a backlight control state;
switching different training modes through a state machine according to different transmission rates; judging signals of clock recovery, symbol locking and channel alignment; and when the training mode is finished, switching the backlight control state, and judging whether to switch the backlight according to the data sent by the main chain so as to reduce the power consumption.
As an embodiment of the present invention, the interface link module configures an attribute data packet of a main link, and designs a pipeline encapsulation manner.
As an implementation mode of the invention, the high-speed serial transceiver uses a gigabit high-speed transceiver to complete 8B/10B encoder, system reset, channel equalizer, clock phase-locked loop, and different voltage swing and pre-emphasis control modes are generated according to the inconsistency of the electrical interfaces of each channel.
The invention has the beneficial effects that: the embedded display port implementation method and system based on the programmable logic can reduce the utilization rate of logic resources and reduce power loss at the same time. The invention can not only operate the high-speed signal transceiver, but also flexibly process the service flow under different environments.
Drawings
Fig. 1 is a flowchart illustrating an implementation method of an embedded displayport according to an embodiment of the present invention.
FIG. 2 is another flowchart of an implementation method of an embedded DisplayPort in accordance with an embodiment of the present invention.
FIG. 3 is a flowchart illustrating steps of pipeline video frame packing according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
The invention discloses a method for realizing an embedded display port based on programmable logic, and fig. 1 and 2 are flow charts of the method for realizing the embedded display port in one embodiment of the invention; referring to fig. 1 and fig. 2, in an embodiment of the present invention, the method includes:
step S1, preprocessing the link training and establishing connection with a receiving end;
in an embodiment of the invention, the two state machines are respectively sent to the EDID analysis module and the DPCD analysis module; the two analysis modules perform analysis processing, and the optimal communication mode of the receiving end is selected to establish connection. To improve transmission efficiency performance, the EDID state machine and DPCD state machine may be skipped for fast link training if the embedded displayport resolution is known. The design mode jumps out of complex and tedious communication interaction between the sending end and the receiving end, and saves training time.
Step S2, a link training mode is selected to realize switching between different training modes of the embedded displayport.
In an embodiment of the present invention, the default state may send a training mode one and a training mode two. And when the third training mode is detected to be effective, sending the first training mode and the third training mode. And integrating the three training mode sending data into a frame packaging module. The first two steps are effective to run the third step. Of course, other training patterns may be selected.
Step S3, the video frame is wrapped. FIG. 3 is a flowchart of the steps of pipeline video frame packing according to an embodiment of the present invention; referring to fig. 3, in an embodiment of the present invention, the packet content includes idle frame insertion, attribute data packet insertion, transmission unit packet insertion, data scrambling, and adjacent channel skewing. In an embodiment of the present invention, a pipeline encapsulation manner is used, which can improve transmission efficiency and reduce data buffering.
Step S4, serially sending data, controlling a hardmac IP high-speed serial transceiver by using a programmable logic device, realizing the function of an embedded display port physical layer, starting 8B/10B coding, notifying to send a video data packet after system reset, and carrying out data acquisition on the video data packet by using a clock generated by a gigabit high-speed transceiver; meanwhile, the problem of inconsistent electrical interfaces is solved by processing the voltage swing and the pre-emphasis. In an embodiment of the invention, the steps S3 and S4 may be performed simultaneously.
The invention also discloses an embedded display port system based on programmable logic, which comprises: the system comprises a first IP soft core, a second IP soft core, an interface link module and a high-speed serial transceiver. The first IP soft core is used for preprocessing link training; the embedded display port auxiliary channel is realized, the connection between the sending end and the receiving end equipment is established, and the channel function detection, the effect evaluation and the power consumption control are realized. The second IP soft core is used for selecting a link training mode to realize the switching of different training modes of the embedded display port. The interface link module is used for realizing an embedded display port link layer, and the functions of the link layer comprise a data frame wrapper, a scrambler and a buffer. The high-speed serial transceiver is used for realizing an embedded display port physical layer data channel; the characteristics of physical layer coding, system reset generation and electrical appliance interface inconsistency control are realized.
In an embodiment of the present invention, the preprocessing process of the first IP soft core designs two state machines, and the two state machines are respectively a decoding EDID state and a decoding DPCD state; and analyzing the receiving end capability of the embedded display port respectively, evaluating, and selecting an optimal mode to carry out parameter configuration.
In an embodiment of the present invention, the link training process of the second IP soft core designs two state machines: a training mode state, a backlight control state; switching different training modes through a state machine according to different transmission rates; judging signals of clock recovery, symbol locking and channel alignment; and when the training mode is finished, switching the backlight control state, and judging whether to switch the backlight according to the data sent by the main chain so as to reduce the power consumption.
In an embodiment of the present invention, the interface link module configures an attribute data packet of a main link, and adopts a pipeline packet mode.
In an embodiment of the present invention, the high-speed serial transceiver uses a gigabit high-speed transceiver to complete 8B/10B encoder, system reset, channel equalizer, clock phase-locked loop, and generate different voltage swing and pre-emphasis control modes according to the inconsistency of electrical interfaces of each channel.
In summary, the method and system for implementing an embedded display port based on programmable logic according to the present invention can reduce the utilization rate of logic resources and reduce power consumption. The invention can not only operate the high-speed signal transceiver, but also flexibly process the service flow under different environments.
The invention simplifies the complex communication protocol of the auxiliary channel by combining the first IP soft core and the second IP soft core, improves the interaction efficiency of the sending end and the receiving end and reduces the resource utilization rate. Meanwhile, the auxiliary communication protocol can be added by the user to improve the flexibility of the embedded display port. A packing mode of a production line is provided, and data transmission efficiency is improved.
The use of the hardcore module of the hardcore high-speed serial transceiver which adopts the technologies of current type logic circuit, clock data recovery, 8b10b line coding, pre-emphasis and the like can greatly reduce the influence of clock distortion, signal attenuation and line noise on the receiving performance, thereby improving the transmission rate to be more than 10 Gbps.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (9)
1. A method for realizing an embedded display port based on programmable logic is characterized by comprising the following steps:
step S1, preprocessing the link training and establishing connection with the receiving end;
step S2, selecting a link training mode to realize the switching of different training modes of the embedded display port interface;
step S3, packaging the video frame; the packet content comprises idle frame insertion, attribute data packet insertion, transmission unit packet insertion, data scrambling and adjacent channel inclination;
s4, serially transmitting data, controlling a hardmac IP high-speed serial transceiver by using a programmable logic device to realize the function of an embedded display port physical layer, starting 8B/10B coding, notifying to transmit a video data packet after system reset, and performing data acquisition on the video data packet by using a clock generated by a gigabit high-speed transceiver; meanwhile, the problem of inconsistent electrical interfaces is solved by processing the voltage swing and the pre-emphasis.
2. The embedded displayport interface implementation method based on programmable logic according to claim 1, characterized in that:
in step S1, the two state machines are respectively sent to the EDID analysis module and the DPCD analysis module; the two analysis modules perform analysis processing, and the optimal communication mode of the receiving end is selected to establish connection; if the embedded displayport resolution is known, skipping the EDID state machine and the DPCD state machine, and performing fast link training.
3. The embedded displayport interface implementation method based on programmable logic according to claim 1, characterized in that:
in step S3, a pipeline processing method is used.
4. The embedded displayport interface implementation method based on programmable logic according to claim 1, characterized in that:
the step S3 and the step S4 are performed simultaneously.
5. An embedded displayport system based on programmable logic, the embedded displayport system comprising:
the first IP soft core is used for preprocessing the link training; the embedded display port auxiliary channel is realized, the connection between the sending end and the receiving end equipment is established, and the function detection, the effect evaluation and the power consumption control of the channel are realized;
the second IP soft core is used for selecting a link training mode and realizing the switching of different training modes of the embedded display port;
the interface link module is used for realizing an embedded display port link layer, and the functions of the link layer comprise a data frame wrapper, a scrambler and a buffer;
the high-speed serial transceiver is used for realizing an embedded display port physical layer data channel; the characteristics of physical layer coding, system reset generation and electrical appliance interface inconsistency control are realized.
6. The programmable logic based embedded displayport system of claim 5, wherein:
two state machines are designed in the preprocessing process of the first IP soft core, wherein the two state machines are a decoding EDID state and a decoding DPCD state respectively; and analyzing the receiving end capability of the embedded display port respectively, evaluating, and selecting an optimal mode to carry out parameter configuration.
7. The programmable logic based embedded displayport system of claim 5, wherein:
the link training process of the second IP soft core designs two state machines: a training mode state, a backlight control state;
switching different training modes through a state machine according to different transmission rates; judging signals of clock recovery, symbol locking and channel alignment; and when the training mode is finished, switching the backlight control state, and judging whether to switch the backlight according to the data sent by the main chain so as to reduce the power consumption.
8. The programmable logic based embedded displayport system of claim 5, wherein:
the interface link module configures an attribute data packet of a main link and designs a pipeline packaging mode.
9. The programmable logic based embedded displayport system of claim 5, wherein:
the high-speed serial transceiver uses a gigabit high-speed transceiver to complete 8B/10B encoder, system reset, a channel equalizer, a clock phase-locked loop and different voltage swing and pre-emphasis control modes according to the inconsistency of electrical interfaces of each channel.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114490477A (en) * | 2022-01-28 | 2022-05-13 | 重庆惠科金扬科技有限公司 | Interface switching circuit, method, liquid crystal display screen and storage medium |
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