CN104536924A - Multi-channel delay deviation correction method and device for board-level high-speed transmission bus - Google Patents

Multi-channel delay deviation correction method and device for board-level high-speed transmission bus Download PDF

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Publication number
CN104536924A
CN104536924A CN201410755221.XA CN201410755221A CN104536924A CN 104536924 A CN104536924 A CN 104536924A CN 201410755221 A CN201410755221 A CN 201410755221A CN 104536924 A CN104536924 A CN 104536924A
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synchronously
asynchronous fifo
com
passage
queue
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CN104536924B (en
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周宏伟
邓让钰
李永进
晏小波
张英
杨乾明
冯权友
曾坤
戴泽福
王勇
窦强
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National University of Defense Technology
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National University of Defense Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

Abstract

The invention discloses a multi-channel delay deviation correction method for a board-level high-speed transmission bus and a multi-channel delay deviation correction device for the board-level high-speed transmission bus. The method comprises the following steps: an asynchronous FIFO (first in, first out) queue is in advance increased for each passageway, the queue outlet data is monitored by each clock tick, when a COM (component object model) synchronization symbol is discovered, the clock tick begins to count, under a preset condition, queue heads in all asynchronous FIFO queues are judged whether the COM synchronization symbol is simultaneously discovered, if so, delay deviation for all channel is successfully corrected, the COM synchronization symbols of the queue heads corresponding to all channels are removed, and the data of all asynchronous FIFO queues is synchronously read; if not, the delay deviation is unsuccessfully corrected and deflection correction is again executed; the device comprises multiple asynchronous FIFO queues and a delay deviation correction control module for controlling said multiple asynchronous FIFO queues, reading, writing and emptying the data. According to the method and the device, the delay deviation correction is low in delay cost and the correction is fast and efficient, and the hardware resource occupancy is low.

Description

Hyperchannel towards plate level high-speed transfer bus postpones oblique deflection correction method and device
Technical field
The present invention relates to plate level high-speed transfer bus delay and bandwidth optimization technical field, be specifically related to a kind of hyperchannel towards plate level high-speed transfer bus and postpone oblique deflection correction method and device.
Background technology
Along with the development of high-performance server and super way computer, the requirement of system designer to plate level high-speed transfer bus is more and more higher, and how making that the data transfer delay of chip chamber is less, bandwidth is higher is the major issue needing to solve.Plate level high-speed transfer bus is mainly divided three classes at present: a class is that its Typical Representative is pci bus, DDR bus, DDR2 bus, DDR3 bus and DDR4 bus based on source simultaneous techniques with up and down along the parallel transmission bus of Sampling techniques; Another kind of is serial transmission bus based on clock encoding and decoding technique, and its Typical Representative is industry ethernet and InfiniBand bus; 3rd class is the New Bus that existing universal serial bus feature has again parallel bus feature, and Typical Representative is PCI-Express bus, the HyperTransport bus of AMD and the QPI bus of Intel.Traditional parallel bussing technique adopts single-ended (single-end) signal wire transmission data, a clock cable and some parallel data signal lines transmit signals to take over party from transmit leg simultaneously, take over party uses clock signal to control reading data signal and samples, when transmission frequency is brought up to a certain degree, deflection is postponed owing to existing between data signal line, data sampling window is caused more to come also less, therefore, the figure place of the data signal line that transmission frequency and clock signal can control all is restricted, thus limits the raising of parallel bus bandwidth.Serial data transmission mode adopts differential signal serially-transmitted data, transmission line is few, and antijamming capability is strong, and higher frequency therefore can be used to carry out data transmission, improve data transfer bandwidth by improving transmission frequency, shortcoming is that clock encoding-decoding process needs extra delay expense.
In order to meet the more and more higher bandwidth requirement of plate DBMS transmission, by multi-set parallel bus or differential serial bus parallel use again, each group is as a passage (lane), and multiple passage transmits data in a parallel fashion, can realize higher bandwidth.Plate DBMS transfer bus for main flow: the parallel bus of high-bit width is divided into multiple groups usually when specific implementation, each group comprises independently clock signal and one group of parallel data line, this group signal is referred to as a passage, adopts the mode of multi-channel parallel to transmit data between multiple groups; In PCI-Express bus, every single data transmission line adopts differential signal serially-transmitted data, clock signal passes through clock encoding and decoding technique with data sharing one data lines, therefore a differential data line is exactly a passage, and many transmission lines and multiple passage can transmitting data in parallel; In HyperTransport bus, every root transmission data line adopts differential signal mode serially-transmitted data, but adopt independently source synchronous clock line transfer clock, therefore clock line forms a passage together with differential data line, and same employing many transmission lines realize multi-channel parallel transmission data.To sum up, channel transmission technology is widely used as the effective means improving plate level bus transfer bandwidth.
In plate level high-speed transfer bus, adopt multichannel technology can run into interchannel delay deflection (skew) problem.Its producing cause is: each passage has its respective delay, the delay of this barrel leg and the transmission delay etc. on PCB when these postpone to comprise chip package, probably cause the delay on each passage different when chip package and PCB design, in addition in order to reduce the complexity of encapsulation and the design of PCB line, also need the delay variance can tolerated between passage to a certain degree, generally the delay difference between different passage is called channel delay deflection.Under the impact of channel delay deflection, receiving end from different channel reception to data cannot normally according to send beat assembled, cause each channel data asynchronous.
The device postponing skew problems between current Solving Multichannel usually adopts and first does clock zone synchronously, then does the mode postponing deflection rectify correction.The principle of which is: first, no matter be adopt independent clock signal mode or adopt clock code encoding/decoding mode, the clock that each passage is used for data sampling take over party is different, and each passage uses the tranmitting data register of oneself to carry out data receiver sampling.Take over party in order to can by the data syn-chronization on each passage, first need to each channel reception to data carry out clock zone conversion, each passage completes respective sending clock-domain and changes to the clock zone of the data-signal of receiving clock-domain; Secondly, data-signal through clock domain conversion still directly can not combine to form and receive data, because each channel delay is different, the time of clock zone conversion is also different, cause between each channel data after conversion and there is delay deflection, need to carry out delay to correct, guarantee that the data simultaneously entering into each passage at transmit leg can receive take over party simultaneously, merge the data that the data that just send with transmit leg so completely the same.Postpone deflection rectify correction device between traditional hyperchannel and be divided into two parts: Part I is that each passage has an asynchronous FIFO queue, for clock zone change-over circuit; Part II is the register that each passage has one group of cascade, for realizing transmission delay deflection rectify correction circuit between line, suppose that bus has 8 passages, interchannel delay deflection is 6 clock period to the maximum, then postpone deflection rectify correction circuit and need 8 × 6=48 register altogether.The shortcoming of traditional interchannel delay deflection rectify correction device is asynchronous clock domain change-over circuit and link delay deflection rectify correction circuit is each self-separation, on the one hand owing to postponing to be the delay sum of two independent circuits, therefore postpone longer, on the other hand because two circuit are with having used the register circuit of storer and cascade respectively, particularly the number of the register circuit of cascade is many, and therefore hardware logic resource occupation is higher.
Summary of the invention
The technical problem to be solved in the present invention be to provide a kind of postpone oblique deflection correction postpone expense low, correct rapidly and efficiently, hardware resource takies the low hyperchannel towards plate level high-speed transfer bus and postpones oblique deflection correction method and device.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is:
Hyperchannel towards plate level high-speed transfer bus postpones an oblique deflection correction method, and implementation step is as follows:
1) in advance for each passage of plate level high-speed transfer bus increases by one for carrying out the asynchronous FIFO queue of clock zone conversion to the data received in passage, the write clock of described asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, and described asynchronous FIFO queue is preserved according to the order of first-in first-out the multiple data received and completed the conversion of clock zone from tranmitting data register to receive clock;
2) the queue heads data of the asynchronous FIFO queue of each passage are read, whether the queue heads data that each timeticks monitors the asynchronous FIFO queue of all passages are synchronously accord with as the COM postponing tiltedly mark partially, when the queue heads of the asynchronous FIFO at any one passage finds that COM synchronously accords with, then clock cycle count from this COM synchronously accords with, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages synchronously accords with, the synchronous data reading all asynchronous FIFO queues afterwards, otherwise carry out Synchronization timeout counting how many times, if the value of Synchronization timeout number of times has not exceeded setting threshold value, then empty asynchronous FIFO queue corresponding to all passages and redirect execution step 2) re-start delay correction, Synchronization timeout number of times exceedes the then decision delay deflection rectify correction failure of setting threshold value else if.
Further, described step 2) detailed step as follows:
2.1) foundation is read the asynchronous FIFO queue of each passage for controlling, write, null clear operation is to realize the state machine of the calibration of multiple interchannel delay deflection, described state machine is read asynchronous FIFO queue according to receiving to send from the status information of each passage asynchronous FIFO, write, the control signal of null clear operation, the status information of described each passage asynchronous FIFO comprises idle condition, wait for that any passage receives COM and synchronously accords with state, wait for some clock period states, reset fifo status, wait for that all channel C OM synchronously accord with arrival state, remove COM and synchronously accord with state, time-out empties fifo status totally 7 states, the state of init state machine is idle condition, and initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out,
2.2) in an idle state, state machine judges whether that receiving hyperchannel postpones oblique deflection correction enable signal, if receive hyperchannel to postpone oblique deflection correction enable signal, then state machine enters and waits for that any passage receives COM and synchronously accords with state and redirect execution step 2.3);
2.3) COM is received synchronously under symbol state at any passage of wait, the each timeticks of state machine monitors the queue heads data of the asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads data of asynchronous FIFO queue corresponding to any one passage, then state machine enters and waits for some clock period states and redirect performs step 2.4);
2.4) under the some clock period states of wait, from the queue heads data of asynchronous FIFO queue corresponding to described passage, find that COM synchronously accords with beginning clock cycle count data, when clock cycle count reaches the depth value of asynchronous FIFO queue, state machine enters reset fifo status and redirect performs step 2.5);
2.5) under reset fifo status, the asynchronous FIFO queue that each passage that resets is corresponding, by forbidding that write operation reads data in asynchronous FIFO queue until the mode that asynchronous FIFO queue is sky removes all the elements of asynchronous FIFO queue simultaneously continuously, after the asynchronous FIFO queue of each passage is all cleared, state machine enters waits for that all channel C OM synchronously accord with arrival state and redirect performs step 2.6);
2.6) under all channel C OM of wait synchronously accord with arrival state, receive clock cycle count COM synchronously accords with from any one passage and wait for that all channel C OM synchronously accord with arrival, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge all channel delay deflection rectify corrections success, state machine enter remove COM synchronously accord with state and redirect perform step 2.7); COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues not yet in the clock cycle count time being greater than configuration maximal value else if, now receive asynchronous FIFO queue that COM synchronously accords with at first full and will overflow in the next clock period, cannot proceed synchronous, now judge all Channel Synchronous time-out, the value of Synchronization timeout number of times is added 1, and state machine enters time-out and empties fifo status and redirect execution step 2.8);
2.7) removing COM synchronously under symbol state, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages in the timeticks of specifying synchronously accords with, and state machine enters idle condition and redirect performs step 2.2);
2.8) under time-out empties fifo status, remove all the elements of asynchronous FIFO queue corresponding to each passage, judge whether the value of Synchronization timeout number of times exceedes setting threshold value, if have not exceeded setting threshold value, then state machine enters and waits for that all channel C OM synchronously accord with arrival state and redirect performs step 2.6); If exceed setting threshold value, then decision delay deflection rectify correction failure, state machine enters idle condition and redirect performs step 2.2).
Further, described step 2.1) middle initialization is for recording the Synchronization timeout number of times of delay deflection rectify correction time-out with when setting threshold value, and the initialization value of Synchronization timeout number of times is 0, and the initialization value of setting threshold value is 8.
Further, described step 2.7) in the timeticks of specifying be 1 timeticks.
The present invention also provides a kind of hyperchannel towards plate level high-speed transfer bus to postpone oblique deflection correction device, comprising:
Multiple asynchronous FIFO queue, for carrying out clock zone conversion to the data received in passage, with each passage one_to_one corresponding of plate level high-speed transfer bus, the write clock of described asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, and described asynchronous FIFO queue is preserved according to the order of first-in first-out the multiple data received and completed the conversion of clock zone from tranmitting data register to receive clock;
Postpone oblique deflection correction control module, for reading the queue heads data of the asynchronous FIFO queue of each passage, whether the queue heads data that each timeticks monitors the asynchronous FIFO queue of all passages are synchronously accord with as the COM postponing tiltedly mark partially, when the queue heads of the asynchronous FIFO at any one passage finds that COM synchronously accords with, then clock cycle count from this COM synchronously accords with, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages synchronously accords with, the synchronous data reading all asynchronous FIFO queues afterwards, otherwise carry out Synchronization timeout counting how many times, if the value of Synchronization timeout number of times has not exceeded setting threshold value, then empty asynchronous FIFO queue corresponding to all passages and re-start and postpone to correct, Synchronization timeout number of times exceedes the then decision delay deflection rectify correction failure of setting threshold value else if.
Further, the oblique deflection correction control module of described delay specifically comprises to be read the asynchronous FIFO queue of each passage for controlling, write, null clear operation is to realize the state machine of the calibration of multiple interchannel delay deflection, described state machine is read asynchronous FIFO queue according to receiving to send from the status information of each passage asynchronous FIFO, write, the control signal of null clear operation, the status information of described each passage asynchronous FIFO comprises idle condition, wait for that any passage receives COM and synchronously accords with state, wait for some clock period states, reset fifo status, wait for that all channel C OM synchronously accord with arrival state, remove COM and synchronously accord with state, time-out empties fifo status totally 7 states, the state of init state machine is idle condition, and initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, described state machine comprises:
Idle condition execution module, for in an idle state, state machine judges whether that receiving hyperchannel postpones oblique deflection correction enable signal, if receive hyperchannel to postpone oblique deflection correction enable signal, then state machine enters and waits for that any passage receives COM and synchronously accords with state and redirect performs and waits for that any passage receives COM and synchronously accords with state execution module;
Wait for that any passage receives COM and synchronously accords with state execution module, for receiving COM synchronously under symbol state at any passage of wait, the each timeticks of state machine monitors the queue heads data of the asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads data of asynchronous FIFO queue corresponding to any one passage, then state machine enters and waits for some clock period states and redirect performs and waits for some clock period state execution modules;
Wait for some clock period state execution modules, for under the some clock period states of wait, from the queue heads data of asynchronous FIFO queue corresponding to described passage, find that COM synchronously accords with beginning clock cycle count data, when clock cycle count reaches the depth value of asynchronous FIFO queue, state machine enters reset fifo status and redirect performs reset fifo status execution module;
Reset fifo status execution module, for under reset fifo status, the asynchronous FIFO queue that each passage that resets is corresponding, by forbidding that write operation reads data in asynchronous FIFO queue until the mode that asynchronous FIFO queue is sky removes all the elements of asynchronous FIFO queue simultaneously continuously, after the asynchronous FIFO queue of each passage is all cleared, state machine enters waits for that all channel C OM synchronously accord with arrival state and redirect execution waits for that all channel C OM synchronously accord with arrival state execution module;
Wait for that all channel C OM synchronously accord with arrival state execution module, under synchronously according with arrival state at all channel C OM of wait, receive clock cycle count COM synchronously accords with from any one passage and wait for that all channel C OM synchronously accord with arrival, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, state machine enters and removes COM and synchronously accord with state and redirect performs and removes COM and synchronously accord with state execution module; COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues not yet in the clock cycle count time being greater than configuration maximal value else if, now receive asynchronous FIFO queue that COM synchronously accords with at first full and will overflow in the next clock period, cannot proceed synchronous, now judge all Channel Synchronous time-out, the value of Synchronization timeout number of times is added 1, state machine enter time-out empty fifo status and redirect perform time-out empty fifo status execution module;
Remove COM and synchronously accord with state execution module, for removing COM synchronously under symbol state, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages in the timeticks of specifying synchronously accords with, and state machine enters idle condition and redirect performs idle condition execution module;
Time-out empties fifo status execution module, under emptying fifo status in time-out, remove all the elements of asynchronous FIFO queue corresponding to each passage, judge whether the value of Synchronization timeout number of times exceedes setting threshold value, if have not exceeded setting threshold value, then state machine enters and waits for that all channel C OM synchronously accord with arrival state and redirect execution waits for that all channel C OM synchronously accord with arrival state execution module; If exceed setting threshold value, then decision delay deflection rectify correction failure, state machine enters idle condition and redirect performs idle condition execution module.
Further, when described state machine initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, the initialization value of Synchronization timeout number of times is 0, and the initialization value of setting threshold value is 8.
Further, removing COM described in, synchronously to accord with the timeticks that state execution module specifies be 1 timeticks.
The present invention postpones oblique deflection correction method towards the hyperchannel of plate level high-speed transfer bus and has following technique effect:
1, the present invention devises multi-functional asynchronous FIFO queue, asynchronous FIFO queue has two major functions, a function carries out clock zone conversion to the data received in passage, the write clock of asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, and reading clock is the receive clock of each passage from take over party, another one function preserves multiple data received according to the order of first-in first-out, based under the control of state, by reading fifo queue, write, null clear operation, realize the calibration of multiple interchannel delay deflection, the asynchronous FIFO queue of simple function and the register of cascade in traditional delay deflection rectify correction device is instead of by asynchronous FIFO queue, two steps that advanced row clock territory conversion in classic method carries out postponing calibration are again merged into a step, take over party receives data are only asynchronous FIFO queue the slowest in each passage clock zone switching time to the delay of the reception data obtaining alignment from each passage, save in classic method and be specifically designed to the extra delay expense of the register logical of cascade carrying out postponing deflection rectify correction, the clock periodicity of maximum saving is the maximum-delay skew clock periodicity of each passage.
2, the present invention is by devising asynchronous FIFO queue, by asynchronous FIFO queue, clock zone conversion is carried out to the data received in passage, the write clock of asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, the asynchronous FIFO queue being only used for doing clock zone conversion in traditional delay deflection rectify correction device and the register that is only used for the cascade carrying out delay deflection rectify correction are united two into one, can not only delay be reduced, also avoid the waste of hardware logic resource.For the bus of 8 passages, be at least 3 according to asynchronous FIFO queue depth, interchannel delay deflection is 6 calculating to the maximum, traditional delay deflection rectify correction device needs 8 × 3=24 register to be used for clock zone conversion, need 8 × 6=48 register for postponing deflection rectify correction, and the present invention only needs the asynchronous FIFO queue for each channels designs 6 degree of depth just can complete clock zone conversion and postpone deflection rectify correction, only need 8 × 6=48 register, save the register resources of 1/3rd than classic method.
It is postpone device corresponding to oblique deflection correction method with the present invention towards the hyperchannel of plate level high-speed transfer bus that the present invention postpones oblique deflection correction device towards the hyperchannel of plate level high-speed transfer bus, therefore also just there is the present invention to postpone the identical technique effect of oblique deflection correction method towards the hyperchannel of plate level high-speed transfer bus, therefore do not repeat them here.
Accompanying drawing explanation
Fig. 1 is the basic procedure schematic diagram of embodiment of the present invention method.
Fig. 2 is the state transition diagram of state machine in embodiment of the present invention method.
Fig. 3 is the basic procedure schematic diagram of embodiment of the present invention device.
Embodiment
As shown in Figure 1, the present embodiment step of postponing oblique deflection correction method towards the hyperchannel of plate level high-speed transfer bus is as follows:
1) in advance for each passage of plate level high-speed transfer bus increases by one for carrying out the asynchronous FIFO queue of clock zone conversion to the data received in passage, the write clock of asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, and asynchronous FIFO queue is preserved according to the order of first-in first-out the multiple data received and completed the conversion of clock zone from tranmitting data register to receive clock;
2) the queue heads data of the asynchronous FIFO queue of each passage are read, whether the queue heads data that each timeticks monitors the asynchronous FIFO queue of all passages are synchronously accord with as the COM postponing tiltedly mark partially, when the queue heads of the asynchronous FIFO at any one passage finds that COM synchronously accords with, then clock cycle count from this COM synchronously accords with, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages synchronously accords with, the synchronous data reading all asynchronous FIFO queues afterwards, otherwise carry out Synchronization timeout counting how many times, if the value of Synchronization timeout number of times has not exceeded setting threshold value, then empty asynchronous FIFO queue corresponding to all passages and redirect execution step 2) re-start delay correction, Synchronization timeout number of times exceedes the then decision delay deflection rectify correction failure of setting threshold value else if.
See Fig. 2, the present embodiment step 2) detailed step as follows:
2.1) foundation is read the asynchronous FIFO queue of each passage for controlling, write, null clear operation is to realize the state machine of the calibration of multiple interchannel delay deflection, state machine is read asynchronous FIFO queue according to receiving to send from the status information of each passage asynchronous FIFO, write, the control signal of null clear operation, the status information of each passage asynchronous FIFO comprises idle condition (IDLE), wait for that any passage receives COM and synchronously accords with state (WAIT_COM_IN_ANY_LANE), wait for some clock period states (WAIT_SEVERAL_CYCLES), reset fifo status (RST_FIFO), wait for that all channel C OM synchronously accord with arrival state (WAIT_ALL_COM_DONE), remove COM and synchronously accord with state (REMOVE_COM), time-out empties fifo status (CLR_FIFO_FOR_TIMETOUT) totally 7 states, the state of init state machine is idle condition, and initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, in the present embodiment, step 2.1) middle initialization is for recording the Synchronization timeout number of times of delay deflection rectify correction time-out with when setting threshold value, and the initialization value of Synchronization timeout number of times is 0, and the initialization value of setting threshold value is 8.
2.2) under idle condition (IDLE), state machine judges whether that receiving hyperchannel postpones oblique deflection correction enable signal, if receive hyperchannel to postpone oblique deflection correction enable signal, then state machine enters and waits for that any passage receives COM and synchronously accords with state and redirect execution step 2.3).
2.3) receive under COM synchronously accords with state (WAIT_COM_IN_ANY_LANE) at any passage of wait, the each timeticks of state machine monitors the queue heads data of the asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads data of asynchronous FIFO queue corresponding to any one passage, then state machine enters and waits for some clock period states and redirect performs step 2.4).
2.4) under the some clock period states (WAIT_SEVERAL_CYCLES) of wait, from the queue heads data of asynchronous FIFO queue corresponding to passage, find that COM synchronously accords with beginning clock cycle count data, when clock cycle count reaches the depth value of asynchronous FIFO queue, state machine enters reset fifo status and redirect performs step 2.5).
2.5) under reset fifo status (RST_FIFO), the asynchronous FIFO queue that each passage that resets is corresponding, by forbidding that write operation reads data in asynchronous FIFO queue until the mode that asynchronous FIFO queue is sky removes all the elements of asynchronous FIFO queue simultaneously continuously, after the asynchronous FIFO queue of each passage is all cleared, state machine enters waits for that all channel C OM synchronously accord with arrival state and redirect performs step 2.6).
2.6) under all channel C OM of wait synchronously accord with arrival state (WAIT_ALL_COM_DONE), receive clock cycle count COM synchronously accords with from any one passage and wait for that all channel C OM synchronously accord with arrival, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge all channel delay deflection rectify corrections success, state machine enter remove COM synchronously accord with state and redirect perform step 2.7); COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues not yet in the clock cycle count time being greater than configuration maximal value else if, now receive asynchronous FIFO queue that COM synchronously accords with at first full and will overflow in the next clock period, cannot proceed synchronous, now judge all Channel Synchronous time-out, the value of Synchronization timeout number of times is added 1, and state machine enters time-out and empties fifo status and redirect execution step 2.8).
2.7) removing under COM synchronously accords with state (REMOVE_COM), the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages in the timeticks of specifying synchronously accords with, and state machine enters idle condition and redirect performs step 2.2); In the present embodiment, step 2.7) in the timeticks of specifying be 1 timeticks.
2.8) under time-out empties fifo status (CLR_FIFO_FOR_TIMETOUT), remove all the elements of asynchronous FIFO queue corresponding to each passage, judge whether the value of Synchronization timeout number of times exceedes setting threshold value, if have not exceeded setting threshold value, then state machine enters and waits for that all channel C OM synchronously accord with arrival state and redirect performs step 2.6); If exceed setting threshold value, then decision delay deflection rectify correction failure, state machine enters idle condition and redirect performs step 2.2).
See Fig. 2, in the present embodiment, state machine is read asynchronous FIFO queue, write, null clear operation comprises abovementioned steps 2.2 altogether) ~ 2.8) 7 states mentioning: idle condition (IDLE), wait for that any passage receives COM and synchronously accords with state (WAIT_COM_IN_ANY_LANE), wait for some clock period states (WAIT_SEVERAL_CYCLES), reset fifo status (RST_FIFO) waits for that all channel C OM synchronously accord with arrival state (WAIT_ALL_COM_DONE), remove COM and synchronously accord with state (REMOVE_COM), time-out empties fifo status (CLR_FIFO_FOR_TIMETOUT).
(a) idle condition (IDLE).Idle condition is the original state of state machine, upon system reset, state machine is placed in this state, when after the success of delay deflection rectify correction, finally also can get back to this state.
B () waits for that any passage receives COM and synchronously accords with state (WAIT_COM_IN_ANY_LANE).Wait for any passage receive COM synchronously accord with state for wait for any one passage asynchronous FIFO queue in receive COM and synchronously accord with.
C () waits for some clock period states (WAIT_SEVERAL_CYCLES).Wait for that some clock period states for receiving COM synchronously accords with from the asynchronous FIFO queue of any one passage, start clock cycle count, after count value reaches the degree of depth receiving asynchronous FIFO queue, wait for and terminating, enter NextState, the object of this state allows first COM on all passages synchronously accord be sent, and formal Link Skew correction operation will from second batch COM synchronously accords with, and the value of counter is the degree of depth of asynchronous FIFO queue.
D () reset fifo status (RST_FIFO) reset FIFO is for multi-functional asynchronous FIFO queue corresponding to each passage that resets, remove all the elements wherein, empty being operating as of data: forbid write operation, read data in these FIFO continuously until FIFO sky simultaneously.
E () waits for that all channel C OM synchronously accord with arrival state (WAIT_ALL_COM_DONE).Wait for that all channel C OM synchronously accord with arrival state for waiting for that each multi-functional asynchronous FIFO queue have received COM and synchronously accords with.
F () removes COM and synchronously accords with state (REMOVE_COM).Remove COM synchronously to accord with state and synchronously accord with for the COM of the queue heads position removing multi-functional asynchronous FIFO queue corresponding to all passages.
G () time-out empties fifo status (CLR_FIFO_FOR_TIMETOUT).Time-out empties fifo status for after postponing deflection rectify correction time-out, removes all the elements of multi-functional asynchronous FIFO queue corresponding to each passage.
See in Fig. 2, in the present embodiment state machine above-mentioned 7 states between state transition condition as follows:
State transition condition is 1.: idle condition (IDLE) receives to any passage of wait the state transition condition that COM synchronously accords with state (WAIT_COM_IN_ANY_LANE), when state machine receives channel delay deflection rectify correction enable signal, then condition is set up, otherwise is false.
State transition condition is 2.: this condition waits for that any passage receives COM and synchronously accords with state (WAIT_COM_IN_ANY_LANE) to the state transition condition waiting for some clock period states (WAIT_SEVERAL_CYCLES), the each timeticks of state machine monitors the data of the queue heads of the multi-functional asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads of asynchronous FIFO queue corresponding to any one passage, then condition is set up, otherwise is false.
State transition condition is 3.: this condition waits for the state transition condition of some clock period states (WAIT_SEVERAL_CYCLES) to reset fifo status (RST_FIFO), when the clock periodicity waited for reaches the depth value of multi-functional asynchronous FIFO queue, then condition is set up, otherwise is false.
State transition condition is 4.: this condition is that reset fifo status (RST_FIFO) is to waiting for that all channel C OM synchronously accord with the state transition condition of arrival state (WAIT_ALL_COM_DONE), when the multi-functional asynchronous FIFO queue of each passage is cleared, then condition is set up, otherwise condition is false.
State transition condition is 5.: this condition waits for that all channel C OM synchronously accord with arrival state (WAIT_ALL_COM_DONE) empties state transition condition from fifo status (CLR_FIFO_FOR_TIMETOUT) to time-out, if from any one passage receive COM synchronously accords with through clock periodicity be greater than configuration maximal value (by parameter configuration, be traditionally arranged to be the degree of depth of asynchronous FIFO queue) time, still can not see that COM synchronously accords with at the independent head of all asynchronous FIFO queues simultaneously, now first to receive the asynchronous FIFO queue that COM synchronously accords with full, the next clock period will overflow, cannot proceed synchronous, now think Synchronization timeout, this condition is set up, otherwise be false.
State transition condition is 6.: this condition is that time-out empties fifo status (CLR_FIFO_FOR_TIMETOUT) to waiting for that all channel C OM synchronously accord with the state transition condition of arrival state (WAIT_ALL_COM_DONE), the multi-functional asynchronous FIFO queue corresponding when each passage is all cleared, and total Synchronization timeout number of times does not exceed setting threshold value (arranging threshold value in the present embodiment is that 8 expressions allow at most expired times to be 8), then this condition is set up, otherwise is false.
State transition condition is 7.: this condition is that time-out empties the state transition condition of fifo status (CLR_FIFO_FOR_TIMETOUT) to idle condition (IDLE), the multi-functional asynchronous FIFO queue corresponding when each passage is all cleared, and total Synchronization timeout number of times exceedes setting threshold value (such as arranging threshold value is that 8 expressions allow at most expired times to be 8), then this condition is set up, otherwise is false.
State transition condition is 8.: this condition waits for that all channel C OM synchronously accord with arrival state (WAIT_ALL_COM_DONE) to the state transition condition removing COM and synchronously accord with state (REMOVE_COM), if from any one passage receive COM synchronously accords with through clock periodicity be less than or equal to configuration maximal value (maximal value is by parameter configuration, be traditionally arranged to be the degree of depth of asynchronous FIFO queue) time, can see that COM synchronously accords with at the independent head of all asynchronous FIFO queues simultaneously, then think and synchronously complete, this condition is set up, otherwise is false.
State transition condition is 9.: this condition removes COM synchronously to accord with the state transition condition of state (REMOVE_COM) to idle condition (IDLE), and accord with state 8 keep a bat when removing COM, then condition is set up, otherwise is false.
As shown in Figure 3, the present embodiment postpones oblique deflection correction device towards the hyperchannel of plate level high-speed transfer bus and comprises:
Multiple asynchronous FIFO queue (FIFO_1 ~ FIFO_N), for carrying out clock zone conversion to the data received in passage, with each passage (passage 1 ~ passage N) one_to_one corresponding of plate level high-speed transfer bus, the write clock of asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, and asynchronous FIFO queue is preserved according to the order of first-in first-out the multiple data received and completed the conversion of clock zone from tranmitting data register to receive clock;
Postpone oblique deflection correction control module, for reading the queue heads data of the asynchronous FIFO queue of each passage, whether the queue heads data that each timeticks monitors the asynchronous FIFO queue of all passages are synchronously accord with as the COM postponing tiltedly mark partially, when the queue heads of the asynchronous FIFO at any one passage finds that COM synchronously accords with, then clock cycle count from this COM synchronously accords with, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages synchronously accords with, the synchronous data reading all asynchronous FIFO queues afterwards, otherwise carry out Synchronization timeout counting how many times, if the value of Synchronization timeout number of times has not exceeded setting threshold value, then empty asynchronous FIFO queue corresponding to all passages and re-start and postpone to correct, Synchronization timeout number of times exceedes the then decision delay deflection rectify correction failure of setting threshold value else if.
See Fig. 3, each passage one_to_one corresponding of asynchronous FIFO queue and plate level high-speed transfer bus in the present embodiment, for each asynchronous FIFO queue, the input end of asynchronous FIFO queue receives the tranmitting data register signal lane from respective channel transmit leg i_ txclk and data-signal lane i_ data, wherein i is channel number and i ∈ [0, N], N are maximum channel number; The output terminal of asynchronous FIFO queue connects the receive clock signal rxclk of take over party, the data lane that each asynchronous FIFO queue exports inamely _ data_syn has formed the data after postponing oblique deflection correction; Meanwhile, asynchronous FIFO queue is also connected with the oblique deflection correction control module of delay respectively, to the status information postponing oblique deflection correction control module transmission oneself, and receives the control signal of the oblique deflection correction control module of self-dalay.Asynchronous FIFO queue has two major functions: a function carries out clock zone conversion to the data received in passage, the write clock of asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, and reading clock is the receive clock of each passage from take over party; Another one function preserves multiple data received according to the order of first-in first-out, under the control postponing oblique deflection correction control module, by reading and writing fifo queue, null clear operation, realizes the calibration of multiple interchannel delay deflection.Each passage has independently asynchronous FIFO queue, the degree of depth of fifo queue and maximum-delay skew clock periodicity two relating to parameters can tolerated between the clock frequency ratio of fifo queue writing and reading and hyperchannel, in order to prevent asynchronous FIFO from overflowing, the tranmitting data register frequency of receive clock frequency higher than transmit leg of take over party must be ensured.Postpone receive clock signal rxclk and each asynchronous FIFO queue that oblique deflection correction control module connects take over party, receive the status information from each asynchronous fifo queue and the control signal sent each asynchronous FIFO queue.The effect postponing oblique deflection correction control module monitors the asynchronous FIFO queue in all passages, check the full state of the sky of fifo queue, judge whether the data received in fifo queue are that the COM specified synchronously accords with (the special data being specifically designed to Channel Synchronous), according to monitor message, by reading and writing and null clear operation each asynchronous fifo queue, realize the calibration of multiple interchannel delay deflection.Postpone oblique deflection correction control module to monitor the multi-functional asynchronous FIFO queue in all passages, check the full state of the sky of fifo queue, judge whether the data received in fifo queue are special synchronous symbol, according to monitor message, by reading and writing and null clear operation each asynchronous fifo queue, realize the calibration of multiple interchannel delay deflection.
In the present embodiment, postpone oblique deflection correction control module specifically to refer to and to read the asynchronous FIFO queue of each passage for controlling, write, null clear operation is to realize the state machine of the calibration of multiple interchannel delay deflection, state machine is read asynchronous FIFO queue according to receiving to send from the status information of each passage asynchronous FIFO, write, the control signal of null clear operation, the status information of each passage asynchronous FIFO comprises idle condition (IDLE), wait for that any passage receives COM and synchronously accords with state (WAIT_COM_IN_ANY_LANE), wait for some clock period states (WAIT_SEVERAL_CYCLES), reset fifo status (RST_FIFO), wait for that all channel C OM synchronously accord with arrival state (WAIT_ALL_COM_DONE), remove COM and synchronously accord with state (REMOVE_COM), time-out empties fifo status (CLR_FIFO_FOR_TIMETOUT) totally 7 states, the init state of state machine is idle condition, and initialization has for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, state machine comprises:
Idle condition execution module, for in an idle state, state machine judges whether that receiving hyperchannel postpones oblique deflection correction enable signal, if receive hyperchannel to postpone oblique deflection correction enable signal, then state machine enters and waits for that any passage receives COM and synchronously accords with state and redirect performs and waits for that any passage receives COM and synchronously accords with state execution module;
Wait for that any passage receives COM and synchronously accords with state execution module, for receiving COM synchronously under symbol state at any passage of wait, the each timeticks of state machine monitors the queue heads data of the asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads data of asynchronous FIFO queue corresponding to any one passage, then state machine enters and waits for some clock period states and redirect performs and waits for some clock period state execution modules;
Wait for some clock period state execution modules, for under the some clock period states of wait, from the queue heads data of asynchronous FIFO queue corresponding to passage, find that COM synchronously accords with beginning clock cycle count data, when clock cycle count reaches the depth value of asynchronous FIFO queue, state machine enters reset fifo status and redirect performs reset fifo status execution module;
Reset fifo status execution module, for under reset fifo status, the asynchronous FIFO queue that each passage that resets is corresponding, by forbidding that write operation reads data in asynchronous FIFO queue until the mode that asynchronous FIFO queue is sky removes all the elements of asynchronous FIFO queue simultaneously continuously, after the asynchronous FIFO queue of each passage is all cleared, state machine enters waits for that all channel C OM synchronously accord with arrival state and redirect execution waits for that all channel C OM synchronously accord with arrival state execution module;
Wait for that all channel C OM synchronously accord with arrival state execution module, under synchronously according with arrival state at all channel C OM of wait, receive clock cycle count COM synchronously accords with from any one passage and wait for that all channel C OM synchronously accord with arrival, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, state machine enters and removes COM and synchronously accord with state and redirect performs and removes COM and synchronously accord with state execution module; COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues not yet in the clock cycle count time being greater than configuration maximal value else if, now receive asynchronous FIFO queue that COM synchronously accords with at first full and will overflow in the next clock period, cannot proceed synchronous, now judge all Channel Synchronous time-out, the value of Synchronization timeout number of times is added 1, state machine enter time-out empty fifo status and redirect perform time-out empty fifo status execution module;
Remove COM and synchronously accord with state execution module, for removing COM synchronously under symbol state, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages in the timeticks of specifying synchronously accords with, and state machine enters idle condition and redirect performs idle condition execution module;
Time-out empties fifo status execution module, under emptying fifo status in time-out, remove all the elements of asynchronous FIFO queue corresponding to each passage, judge whether the value of Synchronization timeout number of times exceedes setting threshold value, if have not exceeded setting threshold value, then state machine enters and waits for that all channel C OM synchronously accord with arrival state and redirect execution waits for that all channel C OM synchronously accord with arrival state execution module; If exceed setting threshold value, then decision delay deflection rectify correction failure, state machine enters idle condition and redirect performs idle condition execution module.
In the present embodiment, when state machine initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, the initialization value of Synchronization timeout number of times is 0, and the initialization value of setting threshold value is 8.
In the present embodiment, removing COM, synchronously to accord with the timeticks that state execution module specifies be 1 timeticks.
The above is only the preferred embodiment of the present invention, protection scope of the present invention be not only confined to above-described embodiment, and all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (8)

1. the hyperchannel towards plate level high-speed transfer bus postpones an oblique deflection correction method, it is characterized in that implementation step is as follows:
1) in advance for each passage of plate level high-speed transfer bus increases by one for carrying out the asynchronous FIFO queue of clock zone conversion to the data received in passage, the write clock of described asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, and described asynchronous FIFO queue is preserved according to the order of first-in first-out the multiple data received and completed the conversion of clock zone from tranmitting data register to receive clock;
2) the queue heads data of the asynchronous FIFO queue of each passage are read, whether the queue heads data that each timeticks monitors the asynchronous FIFO queue of all passages are synchronously accord with as the COM postponing tiltedly mark partially, when the queue heads of the asynchronous FIFO at any one passage finds that COM synchronously accords with, then clock cycle count from this COM synchronously accords with, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages synchronously accords with, the synchronous data reading all asynchronous FIFO queues afterwards, otherwise carry out Synchronization timeout counting how many times, if the value of Synchronization timeout number of times has not exceeded setting threshold value, then empty asynchronous FIFO queue corresponding to all passages and redirect execution step 2) re-start delay correction, Synchronization timeout number of times exceedes the then decision delay deflection rectify correction failure of setting threshold value else if.
2. the hyperchannel towards plate level high-speed transfer bus according to claim 1 postpones oblique deflection correction method, it is characterized in that, described step 2) detailed step as follows:
2.1) foundation is read the asynchronous FIFO queue of each passage for controlling, write, null clear operation is to realize the state machine of the calibration of multiple interchannel delay deflection, described state machine is read asynchronous FIFO queue according to receiving to send from the status information of each passage asynchronous FIFO, write, the control signal of null clear operation, the status information of described each passage asynchronous FIFO comprises idle condition, wait for that any passage receives COM and synchronously accords with state, wait for some clock period states, reset fifo status, wait for that all channel C OM synchronously accord with arrival state, remove COM and synchronously accord with state, time-out empties fifo status totally 7 states, the state of init state machine is idle condition, and initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out,
2.2) in an idle state, state machine judges whether that receiving hyperchannel postpones oblique deflection correction enable signal, if receive hyperchannel to postpone oblique deflection correction enable signal, then state machine enters and waits for that any passage receives COM and synchronously accords with state and redirect execution step 2.3);
2.3) COM is received synchronously under symbol state at any passage of wait, the each timeticks of state machine monitors the queue heads data of the asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads data of asynchronous FIFO queue corresponding to any one passage, then state machine enters and waits for some clock period states and redirect performs step 2.4);
2.4) under the some clock period states of wait, from the queue heads data of asynchronous FIFO queue corresponding to described passage, find that COM synchronously accords with beginning clock cycle count data, when clock cycle count reaches the depth value of asynchronous FIFO queue, state machine enters reset fifo status and redirect performs step 2.5);
2.5) under reset fifo status, the asynchronous FIFO queue that each passage that resets is corresponding, by forbidding that write operation reads data in asynchronous FIFO queue until the mode that asynchronous FIFO queue is sky removes all the elements of asynchronous FIFO queue simultaneously continuously, after the asynchronous FIFO queue of each passage is all cleared, state machine enters waits for that all channel C OM synchronously accord with arrival state and redirect performs step 2.6);
2.6) under all channel C OM of wait synchronously accord with arrival state, receive clock cycle count COM synchronously accords with from any one passage and wait for that all channel C OM synchronously accord with arrival, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge all channel delay deflection rectify corrections success, state machine enter remove COM synchronously accord with state and redirect perform step 2.7); COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues not yet in the clock cycle count time being greater than configuration maximal value else if, now receive asynchronous FIFO queue that COM synchronously accords with at first full and will overflow in the next clock period, cannot proceed synchronous, now judge all Channel Synchronous time-out, the value of Synchronization timeout number of times is added 1, and state machine enters time-out and empties fifo status and redirect execution step 2.8);
2.7) removing COM synchronously under symbol state, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages in the timeticks of specifying synchronously accords with, and state machine enters idle condition and redirect performs step 2.2);
2.8) under time-out empties fifo status, remove all the elements of asynchronous FIFO queue corresponding to each passage, judge whether the value of Synchronization timeout number of times exceedes setting threshold value, if have not exceeded setting threshold value, then state machine enters and waits for that all channel C OM synchronously accord with arrival state and redirect performs step 2.6); If exceed setting threshold value, then decision delay deflection rectify correction failure, state machine enters idle condition and redirect performs step 2.2).
3. the hyperchannel towards plate level high-speed transfer bus according to claim 2 postpones oblique deflection correction method, it is characterized in that: described step 2.1) in initialization for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out time, the initialization value of Synchronization timeout number of times is 0, and the initialization value of setting threshold value is 8.
4. the hyperchannel towards plate level high-speed transfer bus according to claim 3 postpones oblique deflection correction method, it is characterized in that: described step 2.7) in the timeticks of specifying be 1 timeticks.
5. the hyperchannel towards plate level high-speed transfer bus postpones an oblique deflection correction device, it is characterized in that comprising:
Multiple asynchronous FIFO queue, for carrying out clock zone conversion to the data received in passage, with each passage one_to_one corresponding of plate level high-speed transfer bus, the write clock of described asynchronous FIFO queue is the tranmitting data register of each passage from transmit leg, reading clock is the receive clock of each passage from take over party, and described asynchronous FIFO queue is preserved according to the order of first-in first-out the multiple data received and completed the conversion of clock zone from tranmitting data register to receive clock;
Postpone oblique deflection correction control module, for reading the queue heads data of the asynchronous FIFO queue of each passage, whether the queue heads data that each timeticks monitors the asynchronous FIFO queue of all passages are synchronously accord with as the COM postponing tiltedly mark partially, when the queue heads of the asynchronous FIFO at any one passage finds that COM synchronously accords with, then clock cycle count from this COM synchronously accords with, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages synchronously accords with, the synchronous data reading all asynchronous FIFO queues afterwards, otherwise carry out Synchronization timeout counting how many times, if the value of Synchronization timeout number of times has not exceeded setting threshold value, then empty asynchronous FIFO queue corresponding to all passages and re-start and postpone to correct, Synchronization timeout number of times exceedes the then decision delay deflection rectify correction failure of setting threshold value else if.
6. the hyperchannel towards plate level high-speed transfer bus according to claim 5 postpones oblique deflection correction device, it is characterized in that, the oblique deflection correction control module of described delay specifically comprises to be read the asynchronous FIFO queue of each passage for controlling, write, null clear operation is to realize the state machine of the calibration of multiple interchannel delay deflection, described state machine is read asynchronous FIFO queue according to receiving to send from the status information of each passage asynchronous FIFO, write, the control signal of null clear operation, the status information of described each passage asynchronous FIFO comprises idle condition, wait for that any passage receives COM and synchronously accords with state, wait for some clock period states, reset fifo status, wait for that all channel C OM synchronously accord with arrival state, remove COM and synchronously accord with state, time-out empties fifo status totally 7 states, the state of init state machine is idle condition, and initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, described state machine comprises:
Idle condition execution module, for in an idle state, state machine judges whether that receiving hyperchannel postpones oblique deflection correction enable signal, if receive hyperchannel to postpone oblique deflection correction enable signal, then state machine enters and waits for that any passage receives COM and synchronously accords with state and redirect performs and waits for that any passage receives COM and synchronously accords with state execution module;
Wait for that any passage receives COM and synchronously accords with state execution module, for receiving COM synchronously under symbol state at any passage of wait, the each timeticks of state machine monitors the queue heads data of the asynchronous FIFO queue of all passages, if find that COM synchronously accords with data in the queue heads data of asynchronous FIFO queue corresponding to any one passage, then state machine enters and waits for some clock period states and redirect performs and waits for some clock period state execution modules;
Wait for some clock period state execution modules, for under the some clock period states of wait, from the queue heads data of asynchronous FIFO queue corresponding to described passage, find that COM synchronously accords with beginning clock cycle count data, when clock cycle count reaches the depth value of asynchronous FIFO queue, state machine enters reset fifo status and redirect performs reset fifo status execution module;
Reset fifo status execution module, for under reset fifo status, the asynchronous FIFO queue that each passage that resets is corresponding, by forbidding that write operation reads data in asynchronous FIFO queue until the mode that asynchronous FIFO queue is sky removes all the elements of asynchronous FIFO queue simultaneously continuously, after the asynchronous FIFO queue of each passage is all cleared, state machine enters waits for that all channel C OM synchronously accord with arrival state and redirect execution waits for that all channel C OM synchronously accord with arrival state execution module;
Wait for that all channel C OM synchronously accord with arrival state execution module, under synchronously according with arrival state at all channel C OM of wait, receive clock cycle count COM synchronously accords with from any one passage and wait for that all channel C OM synchronously accord with arrival, if COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues within the clock cycle count time being less than or equal to configuration maximal value, then judge the success of all channel delay deflection rectify corrections, state machine enters and removes COM and synchronously accord with state and redirect performs and removes COM and synchronously accord with state execution module; COM can be found synchronously to accord with in the queue heads of all asynchronous FIFO queues not yet in the clock cycle count time being greater than configuration maximal value else if, now receive asynchronous FIFO queue that COM synchronously accords with at first full and will overflow in the next clock period, cannot proceed synchronous, now judge all Channel Synchronous time-out, the value of Synchronization timeout number of times is added 1, state machine enter time-out empty fifo status and redirect perform time-out empty fifo status execution module;
Remove COM and synchronously accord with state execution module, for removing COM synchronously under symbol state, the COM removing the queue heads position of asynchronous FIFO queue corresponding to all passages in the timeticks of specifying synchronously accords with, and state machine enters idle condition and redirect performs idle condition execution module;
Time-out empties fifo status execution module, under emptying fifo status in time-out, remove all the elements of asynchronous FIFO queue corresponding to each passage, judge whether the value of Synchronization timeout number of times exceedes setting threshold value, if have not exceeded setting threshold value, then state machine enters and waits for that all channel C OM synchronously accord with arrival state and redirect execution waits for that all channel C OM synchronously accord with arrival state execution module; If exceed setting threshold value, then decision delay deflection rectify correction failure, state machine enters idle condition and redirect performs idle condition execution module.
7. the hyperchannel towards plate level high-speed transfer bus according to claim 6 postpones oblique deflection correction device, it is characterized in that: when described state machine initialization is for recording the Synchronization timeout number of times and setting threshold value that postpone deflection rectify correction time-out, the initialization value of Synchronization timeout number of times is 0, and the initialization value of setting threshold value is 8.
8. the hyperchannel towards plate level high-speed transfer bus according to claim 7 postpones oblique deflection correction device, it is characterized in that: described in remove COM synchronously to accord with the timeticks that state execution module specifies be 1 timeticks.
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CN115834805B (en) * 2023-02-23 2023-04-18 北京数字光芯集成电路设计有限公司 MIPI DPHY skew elimination circuit and method

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