CN112667013A - Current comparison type clock generation circuit and chip - Google Patents
Current comparison type clock generation circuit and chip Download PDFInfo
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- CN112667013A CN112667013A CN202011552545.5A CN202011552545A CN112667013A CN 112667013 A CN112667013 A CN 112667013A CN 202011552545 A CN202011552545 A CN 202011552545A CN 112667013 A CN112667013 A CN 112667013A
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Abstract
The invention discloses a current comparison type clock generation circuit and a chip, wherein the clock generation circuit is used for generating a high level signal with a first duration and a low level signal with a second duration and comprises a biasing circuit and a trigger circuit, the biasing circuit comprises a resistor and a first MOS (metal oxide semiconductor) tube group for forming a first voltage difference at two ends of the resistor; the trigger circuit comprises a first capacitor, a second MOS tube group and a third MOS tube group, wherein a second voltage difference is formed at two ends of the first capacitor, a third voltage difference is formed at two ends of the second capacitor, and the first voltage difference, the second voltage difference and the third voltage difference are equal. The invention can generate the clock signal comprising a high level signal with a first duration and a low level signal with a second duration, wherein the first duration and the second duration are only related to the resistance values of the resistors and the capacitance values of the first capacitor and the second capacitor by arranging the corresponding MOS tubes, so that the first duration and the second duration are kept unchanged, and the whole clock period is ensured to be unchanged.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a current comparison type clock generation circuit and a chip.
Background
The clock generation circuit is a commonly used functional module, and the performance of the clock generation circuit has a great influence on the whole chip. The clock generating circuit is used for generating a square wave output with a stable period as a timing signal of the rest part of the chip, and the frequency of the generated square wave output is required to be as stable as possible and is not influenced by the voltage, the temperature and the like of a power supply. The accuracy of the clock generation circuit determines the accuracy of the time-related parameters in the chip.
The current comparison type clock generation circuit applies a bias current to a MOS (Metal-Oxide-Semiconductor) transistor group, and alternately outputs a clock signal according to a characteristic of the MOS transistor group. But the frequency of the output clock signal is seriously dependent on the threshold voltage of the MOS transistor and the precision degree of the bias current. Since the threshold voltage of the MOS transistor is likely to drift in mass production, the output clock signal may also deviate. If the current trimming circuit is additionally added, the circuit area is increased and more complicated test procedures are brought.
Disclosure of Invention
The invention provides a current comparison type clock generation circuit and a chip, aiming at overcoming the defect that the precision of a current comparison type clock circuit in the prior art is easily influenced by the voltage threshold of an MOS (metal oxide semiconductor) tube.
The invention solves the technical problems through the following technical scheme:
the invention provides a clock generating circuit of a current comparison type, which is used for generating a clock signal, wherein the clock signal comprises a high level signal with a first duration and a low level signal with a second duration;
the bias circuit comprises a resistor with a flowing current as the bias current and a first MOS tube group forming a first voltage difference at two ends of the resistor;
the trigger circuit comprises a first capacitor, a second MOS tube group and a third MOS tube group, wherein the first capacitor and the second capacitor take the bias current as a charging current, the second MOS tube group forms a second voltage difference at two ends of the first capacitor, and the third MOS tube group forms a third voltage difference at two ends of the second capacitor;
the first voltage difference, the second voltage difference, and the third voltage difference are equal.
Preferably, the first MOS tube group includes a seventh NMOS tube and an eighth NMOS tube, and the bias circuit further includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, and a sixth PMOS tube;
the drain electrode of the second PMOS tube is led out to be used as a first output end of the trigger circuit, and the drain electrode of the fourth PMOS tube is led out to be used as a second output end of the trigger circuit;
the second MOS tube group comprises a second NMOS tube and a fifth NMOS tube;
the third MOS tube group comprises a fourth NMOS tube and a sixth NMOS tube;
the trigger circuit further comprises a first NMOS transistor and a third NMOS transistor;
the source electrodes of the eighth NMOS tubes are all grounded; the drain electrode of the fifth PMOS tube is electrically connected with the drain electrode of the seventh NMOS tube; the drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the eighth NMOS tube; the grid electrode of the seventh NMOS tube is electrically connected with the grid electrode of the eighth NMOS tube; the source electrode of the seventh NMOS tube is electrically connected with one end of the resistor, and the other end of the resistor is grounded;
the grid electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are electrically connected;
the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected with a power supply;
the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube are both electrically connected to the first output end;
the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are both electrically connected to the second output end;
the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is grounded;
the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube respectively; the source electrode of the third NMOS tube is grounded;
the grid electrode of the second NMOS tube and the drain electrode of the fifth NMOS tube are respectively and electrically connected with two ends of the first capacitor, and the source electrode of the fifth NMOS tube is grounded;
the grid electrode of the fourth NMOS tube and the drain electrode of the sixth NMOS tube are respectively and electrically connected with two ends of the second capacitor, and the source electrode of the sixth NMOS tube is grounded;
the length-width ratios of the oxide layers of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are the same or proportional;
the length-width ratios of the oxide layers of the eighth NMOS transistor, the second NMOS transistor and the fifth NMOS transistor are the same or proportional;
the length-width ratios of the oxidation layers of the seventh NMOS tube, the fourth NMOS tube and the sixth NMOS tube are the same or proportional;
the length-width ratio of the oxide layers of the seventh NMOS tube and the eighth NMOS tube is the same or proportional.
Preferably, the clock generation circuit further includes a latch circuit and a signal output circuit, the latch circuit is electrically connected to the first output terminal, the second output terminal, the first input terminal and the second input terminal, respectively, and is configured to latch output signals of the first output terminal and the second output terminal and feed back signals to the first input terminal and the second input terminal;
the signal output circuit is electrically connected with the latch circuit and used for outputting the output signal of the latch circuit.
Preferably, the latch circuit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, and cross-coupled inverters;
the input end of the first inverter is electrically connected with the first output end of the trigger circuit;
the input end of the third inverter is electrically connected with the second output end of the trigger circuit;
the output end of the first phase inverter is electrically connected with the input end of the second phase inverter;
the output end of the second inverter is electrically connected with the main input end of the cross-coupling inverter;
the output end of the third inverter is electrically connected with the input end of the fourth inverter;
the output end of the fourth inverter is electrically connected with the secondary input end of the cross-coupling inverter;
the input end of the fifth inverter is electrically connected with the secondary output end of the cross-coupling inverter;
the output end of the fifth inverter is electrically connected with the input end of the sixth inverter and the first input end of the trigger circuit respectively;
the output end of the sixth inverter is electrically connected with the second input end of the trigger circuit;
and the main output end of the cross coupling reverser is electrically connected with the signal output circuit.
Preferably, the signal output circuit comprises a seventh inverter and an eighth inverter;
the input end of the seventh inverter is electrically connected with the main output end of the cross-coupling inverter; the output end of the seventh inverter is electrically connected with the input end of the eighth inverter; an output end of the eighth inverter alternately outputs the high level signal and the low level signal.
The invention also provides a chip which comprises the current comparison type clock generation circuit.
The positive progress effects of the invention are as follows: the invention can generate the clock signal comprising a high level signal of a first duration and a low level signal of a second duration, wherein the first duration and the second duration are only related to the resistance value of a resistor and the capacitance values of a first capacitor and a second capacitor by arranging the corresponding MOS transistor, the clock signal is not influenced by other device processes, and the first duration and the second duration can be ensured to be unchanged without loading a trimming circuit, so that the whole clock period is ensured to be unchanged, the controllability of a clock generating circuit is increased, and the layout space and the test time are saved.
Drawings
Fig. 1 is a schematic circuit structure diagram according to embodiment 1 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
Referring to fig. 1, the clock generation circuit of the present embodiment includes a flip-flop circuit 1, a bias circuit 2, a latch circuit 3, and a signal output circuit 4, wherein a group of MOS transistors used in cooperation is provided in the flip-flop circuit 1 and the bias circuit 2 to eliminate clock signal drift caused by process errors of MOS devices in a current comparison type circuit.
The bias circuit 2 is used for generating a bias current Ibias, and the bias circuit 2 comprises a resistor through which a current flows as the bias current Ibias and a first MOS (metal oxide semiconductor) tube group forming a first voltage difference between two ends of the resistor.
Specifically, the first MOS transistor group includes a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8, the current of the resistor is a bias current Ibias, and the voltage across the resistor is the difference between the gate-source voltages of the seventh NMOS transistor NM7 and the eighth NMOS transistor NM 8.
The bias circuit 2 further includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, and a sixth PMOS transistor PM 6.
The flip-flop circuit 1 comprises a first capacitor C1 and a second capacitor C2 which take bias current Ibias as charging current, a second MOS tube group which forms a second voltage difference at two ends of C1, a third MOS tube group which forms a third voltage difference at two ends of the C2, a first NMOS tube NM1 and a third NMOS tube NM 3.
Specifically, the second MOS transistor group includes a second NMOS transistor NM2 and a fifth NMOS transistor NM 5; the third MOS transistor group includes a fourth NMOS transistor NM4 and a sixth NMOS transistor NM 6.
The drain electrode of the second PMOS tube is led out to be used as a first output end of the trigger circuit 1, and the drain electrode of the fourth PMOS tube is led out to be used as a second output end of the trigger circuit 1.
The source electrode of the eighth NMOS tube is grounded; the drain electrode of the fifth PMOS tube is electrically connected with the drain electrode of the seventh NMOS tube; the drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the eighth NMOS tube; the grid electrode of the seventh NMOS tube is electrically connected with the grid electrode of the eighth NMOS tube; and the source electrode of the seventh NMOS tube is electrically connected with one end of the resistor, and the other end of the resistor is grounded.
The grid electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are electrically connected.
The source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected with a power supply.
The drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube are electrically connected to the first output end;
the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are electrically connected to the second output end;
the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is grounded;
the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube respectively; the source electrode of the third NMOS tube is grounded;
the grid electrode of the second NMOS tube and the drain electrode of the fifth NMOS tube are respectively and electrically connected with two ends of a first capacitor C1, and the source electrode of the fifth NMOS tube is grounded;
and a grid electrode of the fourth NMOS tube and a drain electrode of the sixth NMOS tube are respectively and electrically connected with two ends of the second capacitor, and a source electrode of the sixth NMOS tube is grounded.
The latch circuit 3 in this embodiment is electrically connected to the first output terminal, the second output terminal, the first input terminal, and the second input terminal of the flip-flop circuit 1, respectively, and is configured to latch output signals of the first output terminal and the second output terminal and feed back signals to the first input terminal and the second input terminal.
The signal output circuit 4 in the present embodiment is electrically connected to the latch circuit 3, and outputs an output signal of the latch circuit 3.
Specifically, the latch circuit 3 includes a first inverter Q1, a second inverter Q2, a third inverter Q3, a fourth inverter Q4, a fifth inverter Q5, a sixth inverter Q6, a cross-coupled inverter Q10;
the input end of the first inverter Q1 is electrically connected with the first output end of the flip-flop circuit 1; the input end of the third inverter Q3 is electrically connected with the second output end of the flip-flop circuit 1; the output end of the first inverter Q1 is electrically connected with the input end of the second inverter Q2; the output of the second inverter Q2 is electrically connected to the main input of the cross-coupled inverter Q10; the output end of the third inverter Q3 is electrically connected with the input end of the fourth inverter Q4; the output of the fourth inverter Q4 is electrically connected to the secondary input of the cross-coupled inverter Q10; an input terminal of the fifth inverter Q5 is electrically connected with a sub output terminal of the cross-coupled inverter Q10; the output end of the fifth inverter Q5 is respectively and electrically connected with the input end of the sixth inverter Q6 and the grid electrode of the first NMOS tube; the main output terminal of the cross-coupled inverter Q10 is electrically connected to the signal output circuit 4.
The signal output circuit 4 in the present embodiment includes a seventh inverter Q7 and an eighth inverter Q8;
an input terminal of the seventh inverter Q7 is electrically connected to the main output terminal of the cross-coupled inverter Q10; the output end of the seventh inverter Q7 is electrically connected with the input end of the eighth inverter Q8; the output terminal of the eighth inverter Q8 alternately outputs a high level signal and a low level signal.
The operation principle of the clock generation circuit of the present embodiment is explained below:
setting the first output end to be 1 at the beginning and the second output end to be 0 at the beginning, when the first input end is changed from 1 to 0, the NM1 is closed, the bias current Ibias charges C1 and raises the grid voltage of NM2, and when the grid voltage of NM2 is larger than the overturning voltage of NM2 after T1 time, the first output end is changed from 1 to 0, so that the output clock signal CLK OUT is overturned from 0 to 1; at the same time, the second input terminal changes from "1" to "0" and the first input terminal changes from "1" to "0", at which time the bias current Ibias starts to charge the second capacitor C2. After the time T2, similarly, when the gate voltage of NM4 is greater than the inversion voltage of NM4, the second output terminal changes from "1" to "0" so that the output clock signal CLK OUT is inverted from "1" to "0". Such cycling produces successive clock cycles.
In this embodiment, the flip-flop circuit on the side of the first capacitor C1 generates a high level signal with a duration of T1, and the side is taken as an example to illustrate the working principle: the length-width ratio (W/L) of the oxide layers of the first PMOS tube, the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube is the same or proportional; the length-width ratio (W/L) values of the oxide layers of the eighth NMOS tube and the second NMOS tube, and the seventh NMOS tube and the fifth NMOS tube are respectively the same or proportional. At this time, the first voltage difference between both sides of the resistor R is the same as the second voltage difference between both sides of the first capacitor C1 being charged.
Similarly, the length-width ratio (W/L) of the oxide layers of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube is the same or proportional; the length-width ratio (W/L) values of the oxide layers of the eighth NMOS transistor and the fourth NMOS transistor, the seventh NMOS transistor and the sixth NMOS transistor are respectively the same or proportional, wherein the length-width ratio (W/L) values of the oxide layers of the seventh NMOS transistor and the eighth NMOS transistor are the same or proportional, so that the first voltage difference and the third voltage difference are the same at the moment.
Taking the first duration T1 generated at one side of the first capacitor C1 as an example:
when the capacitor C1 is charged up,
simultaneous production of (1) and (2) gives:
therefore, T1 ═ C1 × R.
It can be seen that the first duration T1 is related only to the first capacitor C1 and the resistor R in the bias circuit, and is not related to the threshold voltage of NM 2. Similarly, the second duration T2 ═ C2 × R. Thus, the clock period of the final clock generation circuit output is (C1+ C2) × R, the process parameters of the MOS tube group are irrelevant, and the adjustment for the MOS process parameter drift is not needed.
In a preferred embodiment, the MOS transistors with the same or proportional aspect ratio of the oxide layer can be selected by selecting the MOS transistors with the same specification.
The current comparison type clock generation circuit provided by this embodiment enables the first duration and the second duration to be only related to the resistance of the resistor and the capacitance of the first capacitor and the second capacitor by setting the corresponding MOS transistor, and is not affected by other device processes, and the first duration and the second duration can be guaranteed to be unchanged without loading a trimming circuit, so that the whole clock cycle is guaranteed to be unchanged, the controllability of the clock generation circuit is increased, and the layout space and the test time are saved.
Example 2
The present embodiment provides a chip including the clock generation circuit in embodiment 1. The chip of the embodiment not only occupies a small area, but also can accurately output clock signals without depending on the quality of the MOS tube.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (6)
1. A clock generation circuit of a current comparison type for generating a clock signal including a high level signal of a first duration and a low level signal of a second duration, characterized in that the clock generation circuit includes a bias circuit for generating a bias current and a flip-flop circuit for alternately generating the high level signal and the low level signal;
the bias circuit comprises a resistor with a flowing current as the bias current and a first MOS tube group forming a first voltage difference at two ends of the resistor;
the trigger circuit comprises a first capacitor, a second MOS tube group and a third MOS tube group, wherein the first capacitor and the second capacitor take the bias current as a charging current, the second MOS tube group forms a second voltage difference at two ends of the first capacitor, and the third MOS tube group forms a third voltage difference at two ends of the second capacitor;
the first voltage difference, the second voltage difference, and the third voltage difference are equal.
2. The current comparison type clock generation circuit of claim 1, wherein the first MOS transistor group comprises a seventh NMOS transistor and an eighth NMOS transistor, and the bias circuit further comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;
the drain electrode of the second PMOS tube is led out to be used as a first output end of the trigger circuit, and the drain electrode of the fourth PMOS tube is led out to be used as a second output end of the trigger circuit;
the second MOS tube group comprises a second NMOS tube and a fifth NMOS tube;
the third MOS tube group comprises a fourth NMOS tube and a sixth NMOS tube;
the trigger circuit further comprises a first NMOS transistor and a third NMOS transistor;
the source electrode of the eighth NMOS tube is grounded; the drain electrode of the fifth PMOS tube is electrically connected with the drain electrode of the seventh NMOS tube; the drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the eighth NMOS tube; the grid electrode of the seventh NMOS tube is electrically connected with the grid electrode of the eighth NMOS tube; the source electrode of the seventh NMOS tube is electrically connected with one end of the resistor, and the other end of the resistor is grounded;
the grid electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are electrically connected;
the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected with a power supply;
the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube are both electrically connected to the first output end;
the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are both electrically connected to the second output end;
the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is grounded;
the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube respectively; the source electrode of the third NMOS tube is grounded;
the grid electrode of the second NMOS tube and the drain electrode of the fifth NMOS tube are respectively and electrically connected with two ends of the first capacitor, and the source electrode of the fifth NMOS tube is grounded;
the grid electrode of the fourth NMOS tube and the drain electrode of the sixth NMOS tube are respectively and electrically connected with two ends of the second capacitor, and the source electrode of the sixth NMOS tube is grounded;
the length-width ratios of the oxide layers of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are the same or proportional;
the length-width ratios of the oxide layers of the eighth NMOS transistor, the second NMOS transistor and the fifth NMOS transistor are the same or proportional;
the length-width ratios of the oxidation layers of the seventh NMOS tube, the fourth NMOS tube and the sixth NMOS tube are the same or proportional;
the length-width ratio of the oxide layers of the seventh NMOS tube and the eighth NMOS tube is the same or proportional.
3. The current-comparison type clock generation circuit according to claim 2, further comprising a latch circuit and a signal output circuit, the latch circuit being electrically connected to the first output terminal, the second output terminal, the first input terminal and the second input terminal, respectively, for latching output signals of the first output terminal and the second output terminal and feeding back signals to the first input terminal and the second input terminal;
the signal output circuit is electrically connected with the latch circuit and used for outputting the output signal of the latch circuit.
4. The current-comparison clock generation circuit of claim 3, wherein the latch circuit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a cross-coupled inverter;
the input end of the first inverter is electrically connected with the first output end of the trigger circuit;
the input end of the third inverter is electrically connected with the second output end of the trigger circuit;
the output end of the first phase inverter is electrically connected with the input end of the second phase inverter;
the output end of the second inverter is electrically connected with the main input end of the cross-coupling inverter;
the output end of the third inverter is electrically connected with the input end of the fourth inverter;
the output end of the fourth inverter is electrically connected with the secondary input end of the cross-coupling inverter;
the input end of the fifth inverter is electrically connected with the secondary output end of the cross-coupling inverter;
the output end of the fifth inverter is electrically connected with the input end of the sixth inverter and the first input end of the trigger circuit respectively;
the output end of the sixth inverter is electrically connected with the second input end of the trigger circuit;
and the main output end of the cross coupling reverser is electrically connected with the signal output circuit.
5. The current-comparison type clock generation circuit according to claim 4, wherein the signal output circuit includes a seventh inverter, an eighth inverter;
the input end of the seventh inverter is electrically connected with the main output end of the cross-coupling inverter; the output end of the seventh inverter is electrically connected with the input end of the eighth inverter; an output end of the eighth inverter alternately outputs the high level signal and the low level signal.
6. A chip characterized in that it comprises a clock generation circuit of the current comparison type according to any one of claims 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011552545.5A CN112667013B (en) | 2020-12-24 | 2020-12-24 | Current comparison type clock generation circuit and chip |
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| CN202011552545.5A CN112667013B (en) | 2020-12-24 | 2020-12-24 | Current comparison type clock generation circuit and chip |
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| CN112667013B CN112667013B (en) | 2022-06-14 |
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| US20090237135A1 (en) * | 2008-03-21 | 2009-09-24 | Ravindraraj Ramaraju | Schmitt trigger having variable hysteresis and method therefor |
| CN103701437A (en) * | 2013-12-10 | 2014-04-02 | 浙江大学 | Clock generator integrated in power electronic chip |
| CN104868880A (en) * | 2015-06-09 | 2015-08-26 | 圣邦微电子（北京）股份有限公司 | Clock signal producing circuit |
| CN105530002A (en) * | 2015-11-26 | 2016-04-27 | 北京中电华大电子设计有限责任公司 | Clock generation device and automatic checking circuit control module |
| CN106374881A (en) * | 2016-10-21 | 2017-02-01 | 深圳市汇春科技股份有限公司 | Quick-starting low-power-consumption clock oscillator |
| CN107248846A (en) * | 2017-08-11 | 2017-10-13 | 珠海格力电器股份有限公司 | A kind of biasing circuit, clock circuit, chip and electronic equipment |
| US20190028089A1 (en) * | 2017-07-21 | 2019-01-24 | Texas Instruments Incorporated | Ultra-low Energy per Cycle Oscillator Topology |
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2020
- 2020-12-24 CN CN202011552545.5A patent/CN112667013B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090237135A1 (en) * | 2008-03-21 | 2009-09-24 | Ravindraraj Ramaraju | Schmitt trigger having variable hysteresis and method therefor |
| CN103701437A (en) * | 2013-12-10 | 2014-04-02 | 浙江大学 | Clock generator integrated in power electronic chip |
| CN104868880A (en) * | 2015-06-09 | 2015-08-26 | 圣邦微电子（北京）股份有限公司 | Clock signal producing circuit |
| CN105530002A (en) * | 2015-11-26 | 2016-04-27 | 北京中电华大电子设计有限责任公司 | Clock generation device and automatic checking circuit control module |
| CN106374881A (en) * | 2016-10-21 | 2017-02-01 | 深圳市汇春科技股份有限公司 | Quick-starting low-power-consumption clock oscillator |
| US20190028089A1 (en) * | 2017-07-21 | 2019-01-24 | Texas Instruments Incorporated | Ultra-low Energy per Cycle Oscillator Topology |
| CN107248846A (en) * | 2017-08-11 | 2017-10-13 | 珠海格力电器股份有限公司 | A kind of biasing circuit, clock circuit, chip and electronic equipment |
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| CN112667013B (en) | 2022-06-14 |
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