CN112666447B - Board position identification circuit applied to dual-redundancy architecture equipment - Google Patents
Board position identification circuit applied to dual-redundancy architecture equipment Download PDFInfo
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- CN112666447B CN112666447B CN202011511707.0A CN202011511707A CN112666447B CN 112666447 B CN112666447 B CN 112666447B CN 202011511707 A CN202011511707 A CN 202011511707A CN 112666447 B CN112666447 B CN 112666447B
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Abstract
The invention relates to a board position identification circuit applied to double-redundancy architecture equipment, which comprises a mother board and N daughter boards, wherein the daughter boards adopt double-redundancy architecture, 2N board position identification daughter circuits are arranged on the mother board, and N is greater than or equal to the number of the daughter boards; each of which isThe board position identification sub-circuit comprises M point positions, 2 M N is more than or equal to each point position, each point position is reserved and connected with the pull-up circuit and the pull-down circuit, a plate position identification signal is output, M plate position identification signals are combined into a plate position identification signal bus, the plate position identification signal bus is connected to an interface of a sub-plate slot position, each two plate position identification sub-circuits are in double redundancy backup, and each two plate position identification sub-circuits are connected to the same sub-plate slot position; when the mother board is welded, according to the arrangement of the preset board position identification signal bus value, a pull-up resistor or a pull-down resistor is welded at each point position in the board position identification sub-circuit, and a unique board position identification signal bus value is output; and reading the board bit identification signal bus value by the daughter board inserted into the mother board to obtain the board bit corresponding to the daughter board.
Description
Technical Field
The invention relates to a production board clamping board position identification circuit applied to equipment with a double-redundancy framework, which has no single point in design, ensures that the equipment can normally work under the condition of one-time fault and can be applied to aerospace equipment with higher reliability requirements.
Background
In the devices composed of universal boards, most of them are composed of a motherboard and different functional daughter boards. The mother board is provided with more connectors as clamping grooves of the daughter board, and the mother board is fixed with the case; and selecting different functional daughter boards according to requirements, and plugging the daughter boards into the mother board card slots to form equipment with different functions. For the case of selecting a plurality of identical seed plates, the positions of the molecular plates are required. The following two schemes are generally adopted:
the first scheme is that a dial switch is arranged on the daughter board, and different daughter boards are arranged in a distinguishing mode through the dial switch. The disadvantage of this solution is that it is unreliable, the position of the dial switch is easily changed by mistake during the debugging or use of the device; moreover, the configuration is required to be powered on again each time, and hot plug is not supported;
the second solution is to configure different software for different sub-boards. The disadvantage of this solution is that the software has a low level of productization, the software is different between different sub-boards, and the modification and management of the software requires a lot of human resources; in addition, the sub boards cannot be commonly used due to different states of software; in the production or assembly process, the daughter boards with the same hardware state and different software states need to be distinguished and recorded, so that the error of the installation position is avoided.
Disclosure of Invention
The invention solves the technical problems that: the defect of the prior art is overcome, and a board position identification circuit applied to double-redundancy architecture equipment is provided, wherein ID numbers of the sub-boards are configured through circuit connection of hardware, the positions of the sub-boards on a template are distinguished, and mounting position errors are avoided.
The solution of the invention is as follows: the board position identification circuit comprises a mother board and N sub-boards, wherein the N sub-boards are inserted into the mother board in a plug-in mode, the sub-boards adopt a double-redundancy architecture, 2N board position identification sub-circuits are arranged on the mother board of the circuit, and the number of N is greater than or equal to that of the sub-boards;
each board bit identification sub-circuit comprises M point positions, 2 M N is more than or equal to each point position, each point position keeps a pull-up circuit connected to VCC and a pull-down circuit connected to GND, a plate position identification signal is output, M plate position identification signals are combined into a plate position identification signal bus, the plate position identification signal bus is connected to an interface of a sub-plate slot, every two plate position identification sub-circuits are in double redundancy backup, and are connected to the same sub-plate slot; when the mother board is welded, according to the arrangement of the preset board position identification signal bus value, a pull-up resistor or a pull-down resistor is welded at each point position in the board position identification sub-circuit, and a unique board position identification signal bus value is output;
and reading the board bit identification signal bus value by the daughter board inserted into the mother board to obtain the board bit corresponding to the daughter board.
The daughter board inserted into the mother board comprises a first board position identification matching circuit and a second board position identification matching circuit; the first board position identification matching circuit and the second board position identification matching circuit are mutually backup and comprise a driving chip and M/2 resistors, one ends of the resistors are connected with two board position identification signals in parallel, the other ends of the resistors are connected to the driving chip, the driving chip improves the driving capability of the board position identification signals and forwards the board position identification signals to a general IO interface of a CPU, and the CPU reads whether the board position identification signals are high level or low level, so that the bus value of the board position identification signals is determined.
The resistance value range is 100 omega-10 kΩ.
The preset board position identification signal bus value is arranged in an even verification mode, so that at least two board position identification signal levels in board position identification signal buses corresponding to any two different board positions are different, and the situation that when one board position identification signal is overturned due to a fault, the board position identification signal cannot be identified as other board positions, and misoperation is generated is ensured.
The pull-up resistor is 3k omega-10 k omega.
The pull-down resistor is 3k omega-10 k omega.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the invention, the board position identification resistor is arranged on the motherboard, and the board position identification resistor is welded on the motherboard, and after resistance welding, the corresponding signal wire is at a fixed level, so that a changeable dialing mode is avoided;
(2) The invention ensures that the hardware and software states of the sub-boards are completely consistent, increases the software productization level, ensures that all the sub-boards can be completely and universally interchanged, and avoids human resource waste and repeated labor caused by independent configuration of software.
Drawings
FIG. 1 is a schematic diagram of a motherboard slot according to an embodiment of the present invention;
FIG. 2 is an embodiment of an actuator redundancy scheme;
FIG. 3 is a board bit recognition hardware circuit according to an embodiment of the invention.
Detailed Description
The invention is further illustrated below with reference to examples.
The invention provides a board position identification circuit applied to double-redundancy architecture equipment, which comprises a mother board and N sub-boards, wherein the N sub-boards are inserted into the mother board in a plug-in mode, the sub-boards adopt double-redundancy architecture, 2N board position identification sub-circuits are arranged on the mother board of the equipment, and N is more than or equal to the number of the sub-boards;
each plate position is identifiedThe sub-circuit includes M bits, 2 M N is more than or equal to each point position, each point position keeps a pull-up circuit connected to VCC and a pull-down circuit connected to GND, a plate position identification signal is output, M plate position identification signals are combined into a plate position identification signal bus, the plate position identification signal bus is connected to an interface of a sub-plate slot, every two plate position identification sub-circuits are in double redundancy backup, and are connected to the same sub-plate slot; when the mother board is welded, according to the arrangement of the preset board position identification signal bus value, a pull-up resistor or a pull-down resistor is welded at each point position in the board position identification sub-circuit, and a unique board position identification signal bus value is output;
and reading the board bit identification signal bus value by the daughter board inserted into the mother board to obtain the board bit corresponding to the daughter board.
The daughter board inserted into the mother board comprises a first board position identification matching circuit and a second board position identification matching circuit; the first board position identification matching circuit and the second board position identification matching circuit are mutually backup and comprise a driving chip and M/2 resistors, one ends of the resistors are connected with two board position identification signals in parallel, the other ends of the resistors are connected to the driving chip, the driving chip improves the driving capability of the board position identification signals and forwards the board position identification signals to a general IO interface of a CPU, and the CPU reads whether the board position identification signals are high level or low level, so that the bus value of the board position identification signals is determined.
Preferably, the resistance is in the range of 100 Ω -10kΩ.
Preferably, the preset board bit identification signal bus value is arranged in an even verification mode, so that at least two board bit identification signal levels in board bit identification signal buses corresponding to any two different board bits are different, and the situation that when one board bit identification signal is overturned due to a fault, the board bit identification signal is not identified as other board bits, and misoperation is generated is ensured.
Preferably, the pull-up resistor is 3k omega-10 k omega.
Preferably, the pull-down resistor is 3k omega-10 k omega.
Examples
The embodiment is a high-reliability board position identification circuit applied to a dual-redundancy architecture, a specific method for board position identification is described in detail, various fault modes in the working process of equipment are analyzed, the scheme can ensure the reliable work of the equipment under the condition of one-time fault, and meanwhile, the safety of the equipment is ensured, and misoperation is avoided.
As shown in fig. 1, the redundancy scheme is as follows: the board position recognition scheme is established on a dual-redundancy plug-in board type structure, the sub boards are divided into different kinds of board cards such as control, communication, switching value input, switching value output, analog value input, analog value output and the like according to functions, and each sub board is provided with a unique ID number for distinguishing. The boards communicate through a high-speed serial bus, so that the rapidness and the real-time performance of the communication are ensured. As shown in fig. 2, in order to ensure reliability, the sub-board adopts a dual redundancy architecture, two CPUs in the sub-board control four execution ends, the execution end redundancy mode is parallel-serial connection, one of the two CPUs sends out an execution instruction, and the sub-board sends out the execution instruction.
The plate position recognition scheme is as follows: in order to ensure that the software and hardware of the board card are completely identical, the board identification circuit is distributed on the motherboard, taking the board identification signal bus as an example with 10 bits wide, 10 board identification point numbers are distributed on the daughter board connector, the network names are defined as ID_M9.0, wherein the board identification signal lines are connected in pairs, namely 5 networks for board identification are arranged, as shown in figure 3, the network names are defined as ID_Z4.0, and the corresponding relation is as follows.
Table 1 board position identification network connection relation
| ID_M[9..8] | ID_Z[4] |
| ID_M[7..6] | ID_Z[3] |
| ID_M[5..4] | ID_Z[2] |
| ID_M[3..2] | ID_Z[1] |
| ID_M[1..0] | ID_Z[0] |
Each point is pulled up to VCC or pulled down to GND through a resistor, a pull-up circuit and a pull-down circuit are reserved when the printed board circuit is designed, and only the pull-up resistor or the pull-down resistor is welded according to arrangement of board positions in installation. The daughter board is connected to the driving chip through a 1k omega resistor in series and then connected to the CPU.
The board position arrangement adopts an even check mode, and at least two board position identification network logics of any two different IDs are guaranteed to be different, so that when one-bit overturn occurs due to a fault, the node cannot be identified as other nodes to generate misoperation.
Table 2 correspondence between plate identification network and node number
| ID_Z[4..0] | NODE Number (NODE) |
| 00000 | 1 |
| 00011 | 2 |
| 00101 | 3 |
| 00110 | 4 |
| 01001 | 5 |
| 01010 | 6 |
| 01100 | 7 |
| 01111 | 8 |
| 10001 | 9 |
| 10010 | 10 |
| 10100 | 11 |
| 10111 | 12 |
| 11000 | 13 |
| 11011 | 14 |
| 11101 | 15 |
| 11110 | 16 |
| Others | Undefined |
In summary, the invention has the following advantages:
(1) The invention can judge the ID by configuring the board bit identification resistor on the motherboard and the daughter board can read and latch the board bit identification signal bus on the motherboard, so that the hardware and software states of a plurality of daughter boards are completely the same. Compared with the condition that only hardware realizes the productization, the software needs to be configured independently according to different ID numbers of the daughter board, the method greatly improves the productization degree of the software and reduces the technical risk, the management cost and the manpower resource cost caused by software modification.
(2) The circuit is simple, the pull-up resistor and the pull-down resistor are double redundancies, the signal of the inter-board connector is double-point double-line, and the circuit has higher reliability and lower cost. Through a simple circuit and a double-redundancy scheme, a low cost and high-reliability board position identification scheme is realized, and through analysis, the normal operation of the equipment is not influenced by one-time faults under all fault modes.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
Claims (4)
1. The board position identification circuit applied to the double-redundancy architecture equipment comprises a mother board and N sub-boards, wherein the N sub-boards are inserted into the mother board in a plug-in mode, and the sub-boards adopt a double-redundancy architecture, and the board position identification circuit is characterized in that 2N board position identification sub-circuits are arranged on the mother board;
each board bit identification sub-circuit comprises M point positions, 2 M N or more, each point location keeps a pull-up circuit connected to VCC and a pull-up circuit connected to GNDThe pull-down circuit outputs a board position identification signal, M board position identification signals form a board position identification signal bus together, the board position identification signal bus is connected to an interface of a sub board slot position, every two board position identification sub-circuits are in double redundancy backup, and are connected to the same sub board slot position; when the mother board is welded, according to the arrangement of the preset board position identification signal bus value, a pull-up resistor or a pull-down resistor is welded at each point position in the board position identification sub-circuit, and a unique board position identification signal bus value is output;
reading the board position identification signal bus value by a daughter board inserted into the motherboard to obtain a board position corresponding to the daughter board;
the daughter board inserted into the mother board comprises a first board position identification matching circuit and a second board position identification matching circuit; the first board position identification matching circuit and the second board position identification matching circuit are mutually backup and comprise a driving chip and M/2 resistors, one ends of the resistors are connected with two board position identification signals in parallel, the other ends of the resistors are connected to the driving chip, the driving chip improves the driving capability of the board position identification signals and forwards the board position identification signals to a general IO interface of a CPU, and the CPU reads whether the board position identification signals are high level or low level, so that the bus value of the board position identification signals is determined;
the preset board position identification signal bus value is arranged in an even verification mode, so that at least two board position identification signal levels in board position identification signal buses corresponding to any two different board positions are different, and the situation that when one board position identification signal is overturned due to a fault, the board position identification signal cannot be identified as other board positions, and misoperation is generated is ensured.
2. The board bit identification circuit applied to the double-redundancy architecture device according to claim 1, wherein the resistance value range is 100 Ω -10kΩ.
3. The board bit identification circuit applied to the dual redundancy architecture device according to claim 1, wherein the pull-up resistor is 3k omega-10 k omega.
4. The board bit identification circuit applied to the dual redundancy architecture device according to claim 1, wherein the pull-down resistor is 3k omega-10 k omega.
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| US5987548A (en) * | 1997-07-07 | 1999-11-16 | International Business Machines Corporation | Method and apparatus for determining system identification number system using system data bus and pull-up resistors in combination with a sensing circuitry |
| US6963217B2 (en) * | 2003-02-21 | 2005-11-08 | University Of South Florida | Method and apparatus for creating circuit redundancy in programmable logic devices |
| CN100390686C (en) * | 2004-04-21 | 2008-05-28 | 华为技术有限公司 | System for identifying single board redundant power supply |
| CN102970029A (en) * | 2012-11-06 | 2013-03-13 | 北京广利核系统工程有限公司 | High-safety digital quantity signal acquisition circuit |
| CN103118482B (en) * | 2012-12-28 | 2015-08-05 | 威力盟电子(苏州)有限公司 | There is circuit board and the discrimination method thereof of quality identification mark |
| CN103716200A (en) * | 2013-12-13 | 2014-04-09 | 上海斐讯数据通信技术有限公司 | Cassette optical line terminal equipment multiple passive optical fiber network card chip number identification method |
| CN104330670A (en) * | 2014-11-05 | 2015-02-04 | 深圳市华星光电技术有限公司 | Feedback separating circuit and combination detection method of motherboard and daughterboard |
| CN104571040A (en) * | 2014-12-31 | 2015-04-29 | 重庆川仪自动化股份有限公司 | Construction method of control system redundancy framework |
| US10082541B2 (en) * | 2015-06-11 | 2018-09-25 | Altera Corporation | Mixed redundancy scheme for inter-die interconnects in a multichip package |
| CN107505883B (en) * | 2017-07-31 | 2020-05-19 | 北京航天自动控制研究所 | High-reliability dual-redundancy integrated control module based on microcontroller |
| CN109857684B (en) * | 2019-01-04 | 2020-11-06 | 烽火通信科技股份有限公司 | Device, method and system for identifying slot address and type of board card of communication equipment |
| CN110673989B (en) * | 2019-08-27 | 2023-05-16 | 国网浙江省电力有限公司电力科学研究院 | Device and method for identifying daughter board card of backboard system |
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