CN112635691B - Array substrate and manufacturing method thereof - Google Patents
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- CN112635691B CN112635691B CN202011632207.2A CN202011632207A CN112635691B CN 112635691 B CN112635691 B CN 112635691B CN 202011632207 A CN202011632207 A CN 202011632207A CN 112635691 B CN112635691 B CN 112635691B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
- H10K50/818—Reflective anodes, e.g. ITO combined with thick metallic layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
- H10K50/816—Multilayers, e.g. transparent multilayers
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- H—ELECTRICITY
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Abstract
The invention relates to an array substrate and a manufacturing method of the array substrate. The array substrate is provided with an anode layer, wherein the anode layer comprises a first conducting layer, a reflecting metal layer, an anti-crystallization layer and a second conducting layer; the reflecting metal layer is arranged on the first conducting layer; the anti-crystallization layer is arranged on the reflection metal layer; the second conducting layer is arranged on the anti-crystallization layer; wherein the anti-crystallization layer is used to prevent the second conductive layer from crystallizing on the reflective metal layer while the anode layer is etched. According to the invention, the extremely thin film of other metals such as copper and the like is prepared on the silver-based reflective metal layer to serve as the anti-crystallization layer, so that the crystallization phenomenon of the silver-induced indium tin oxide is avoided, the condition that the indium tin oxide is left due to the crystallization of the indium tin oxide-based second conductive layer on the reflective metal layer when the anode layer is etched is avoided, the etching difficulty is reduced, the production efficiency and the yield are improved, the voltage Drop (IR-Drop) phenomenon of a large panel is reduced, and the display effect is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a manufacturing method of the array substrate.
Background
With the gradual maturity of Organic Light Emitting Diode (OLED) technology, the selection of different technical routes is also gradually scheduled, for example, a top-emission (top-emission) has a better transmittance than a bottom-emission (bottom-emission), and a simpler light path facilitates the design of a microcavity device, and the like is also defined as a more suitable route for development. Compared with a downward light-emitting device, the anode of the LED has higher requirement, and not only needs to have larger work function and roughness to match with an upper device, but also needs to be used as a reflecting film, so that the LED has good reflecting performance; for example, the anode requirements of the OLED can be well matched by using more ITO/Ag/ITO as the anode of the OLED, the upper layer of ITO can be thickened to adjust the optical cavity length and improve the performance of the device, and the current process requires that the LED can obtain better luminous efficiency at 750-800 angstroms.
As shown in fig. 1, which is a schematic structural diagram of an array substrate in the prior art, an array substrate 90 includes a glass substrate 91, a barrier layer 92, a buffer layer 93, an active layer 94, a gate insulating layer 95, a gate layer 96, an interlayer insulating layer 97, a source/drain layer 98, a passivation layer 99, and an anode layer 910, which are stacked. The anode layer 910 is typically formed of a lower Indium Tin Oxide (ITO), silver layer, and an upper indium tin oxide (ITO/Ag/ITO) structure. It was verified that the anode layer 910, whether it was a single layer of indium tin oxide or an ITO/Ag/ITO structure, had indium tin oxide residue after etching. In the actual preparation process, the silver layer has a larger effect of inducing indium tin oxide crystallization, so that the upper indium tin oxide layer on the silver layer is easy to crystallize, and the etching difficulty is larger or the risk of residue exists; the prior method can only reduce the relative crystallinity through special processes, but the tact time (tact time) is longer, which is not beneficial to mass production.
Therefore, a new array substrate and a method for fabricating the same are needed to overcome the problems in the prior art.
Disclosure of Invention
The invention mainly aims to provide an array substrate and a manufacturing method of the array substrate, which are used for solving the technical problems that a silver layer in an anode layer ITO/Ag/ITO structure of the existing array substrate has a larger effect of inducing indium tin oxide crystallization, so that an upper indium tin oxide layer on the silver layer is easy to crystallize, the etching difficulty is larger or has residual risk, and the production efficiency and the qualification rate are influenced by the existence of indium tin oxide residue after etching.
In order to achieve the above object, the present invention provides an array substrate, which includes an anode layer, the anode layer including a first conductive layer, a reflective metal layer, an anti-crystallization layer, and a second conductive layer; the reflecting metal layer is arranged on the first conducting layer; the anti-crystallization layer is arranged on the reflection metal layer; the second conducting layer is arranged on the anti-crystallization layer; wherein the anti-crystallization layer is to prevent the second conductive layer from crystallizing on the reflective metal layer while the anode layer is etched.
Further, the material of the reflective metal layer includes silver.
Further, the material of the anti-crystallization layer comprises copper; the thickness of the anti-crystallization layer is 5-100 angstroms.
Furthermore, the first conductive layer and the second conductive layer are made of indium tin oxide.
Furthermore, the array substrate comprises a glass substrate, a blocking layer, a buffer layer, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer insulating layer, a source drain electrode layer and a passivation layer; the barrier layer is arranged on the glass substrate; the buffer layer is arranged on the glass substrate and completely covers the barrier layer; the active layer is arranged on the buffer layer and corresponds to the barrier layer; the gate insulating layer is arranged on the active layer; the grid electrode layer is arranged on the grid electrode insulating layer; the interlayer insulating layer is arranged on the grid layer; the source drain electrode layer is arranged on the interlayer insulating layer; the passivation layer is arranged on the source drain electrode layer; the anode layer is arranged on the passivation layer and is electrically connected with the source drain layer.
The invention also provides a manufacturing method of the array substrate, which comprises the step of manufacturing the anode layer, wherein the step of manufacturing the anode layer specifically comprises the following steps: a step of manufacturing a first conductive layer, namely manufacturing the first conductive layer; a step of manufacturing a reflective metal layer, namely manufacturing the reflective metal layer on the first conductive layer; a step of manufacturing an anti-crystallization layer, wherein the anti-crystallization layer is manufactured on the reflection metal layer; a step of manufacturing a second conducting layer, namely manufacturing the second conducting layer on the anti-crystallization layer; and etching the anode layer to perform patterning, wherein the anti-crystallization layer is used for preventing the second conductive layer from crystallizing on the reflective metal layer when the anode layer is etched.
Further, in the step of fabricating the anode layer, a material of the reflective metal layer includes silver.
Further, in the step of manufacturing the anode layer, the material of the anti-crystallization layer comprises copper; the thickness of the anti-crystallization layer is 5-100 angstroms.
In the step of fabricating the anode layer, the first conductive layer and the second conductive layer are made of indium tin oxide.
Further, before the step of manufacturing the anode layer, the method further comprises the following steps:
a step of manufacturing a barrier layer, namely manufacturing the barrier layer on a glass substrate;
a buffer layer manufacturing step, wherein a buffer layer is manufactured on the glass substrate and completely covers the barrier layer;
manufacturing an active layer, namely manufacturing the active layer on the buffer layer, wherein the active layer is arranged corresponding to the barrier layer;
a step of manufacturing a gate insulating layer, wherein the gate insulating layer is manufactured on the active layer;
a step of manufacturing a grid layer, wherein the grid layer is manufactured on the grid insulating layer;
a step of manufacturing an interlayer insulating layer, wherein the interlayer insulating layer is manufactured on the grid layer;
a source drain layer is manufactured, wherein the source drain layer is manufactured on the interlayer insulating layer; and
manufacturing a passivation layer, namely manufacturing the passivation layer on the source drain layer; and manufacturing the anode layer on the passivation layer, wherein the anode layer is electrically connected with the source drain layer.
The invention has the beneficial effects that: the array substrate and the manufacturing method of the array substrate are provided, an extremely thin film of other metals such as copper and the like is prepared on a silver-based reflective metal layer to serve as an anti-crystallization layer to avoid the crystallization phenomenon of silver-induced indium tin oxide, the condition that indium tin oxide is left due to the fact that a second conductive layer made of indium tin oxide is crystallized on the reflective metal layer when an anode layer is etched is avoided, the etching difficulty is reduced, the production efficiency and the qualification rate are improved, the voltage Drop (IR-Drop) phenomenon of a large panel is reduced, and the display effect is improved.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional array substrate;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIG. 3 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of the active layer fabricated according to the embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a completed structure of the gate layer in an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of the source/drain layer manufactured in the embodiment of the present invention;
FIG. 7 is a flow chart of steps in fabricating an anode layer in accordance with an embodiment of the present invention.
The components in the figures are identified as follows:
a glass substrate 1, a barrier layer 2, a buffer layer 3,
an active layer 4, a gate insulating layer 5, a gate layer 6,
an interlayer insulating layer 7, a source drain layer 8, a passivation layer 9,
an anode layer 10, a first conductive layer 11, a reflective metal layer 12,
an anti-crystallization layer 13, a second conductive layer 14, and an array substrate 100.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 2, in an embodiment of the present invention, an array substrate 100 is provided, where the array substrate 100 includes a glass substrate 1, a barrier layer 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate layer 6, an interlayer insulating layer 7, a source drain layer 8, a passivation layer 9, and an anode layer 10.
Specifically, the barrier layer 2 is provided on the glass substrate 1; the buffer layer 3 is arranged on the glass substrate 1 and completely covers the barrier layer 2; the active layer 4 is arranged on the buffer layer 3 and corresponds to the barrier layer 2; the gate insulating layer 5 is arranged on the active layer 4; the gate electrode layer 6 is arranged on the gate insulating layer 5; the interlayer insulating layer 7 is arranged on the gate layer 6; the source drain layer 8 is arranged on the interlayer insulating layer 7; the passivation layer 9 is arranged on the source drain layer 8; the anode layer 10 is disposed on the passivation layer 9 and electrically connected to the source drain layer 8. The etched pattern of the anode layer 10 is any one or more of a circle, a rectangle, a triangle or a polygon, and can be used for adjusting the optical cavity length and improving the device performance.
Wherein the anode layer 10 includes a first conductive layer 11, a reflective metal layer 12, an anti-crystallization layer 13, and a second conductive layer 14; the reflective metal layer 12 is disposed on the first conductive layer 11; the anti-crystallization layer 13 is arranged on the reflection metal layer 12; the second conductive layer 14 is arranged on the anti-crystallization layer 13; wherein the anti-crystallization layer 13 is used to prevent the second conductive layer 14 from crystallizing on the reflective metal layer 12 when the anode layer 10 is etched.
In this embodiment, the first conductive layer 11 and the second conductive layer 14 are made of ito.
In this embodiment, the material of the reflective metal layer 12 includes silver.
In this embodiment, the material of the anti-crystallization layer 13 includes copper; the thickness of the anti-crystallization layer 13 is 5 angstroms to 100 angstroms, so that the growth of the second conductive layer 14 is induced by the thickness of at least one atomic layer, and the reflection effect of the reflective metal layer 12 is not affected by the excessive thickness of the anti-crystallization layer.
In this embodiment, a very thin film of other metals, such as copper, is prepared on the silver-based reflective metal layer 12 to serve as the anti-crystallization layer 13, so as to avoid the crystallization of silver-induced indium tin oxide, thereby avoiding the situation that indium tin oxide remains due to the crystallization of the indium tin oxide-based second conductive layer 14 on the reflective metal layer 12 when the anode layer is etched, reducing the difficulty of etching, improving the production efficiency and yield, reducing the voltage Drop (IR-Drop) of a large panel, and improving the display effect.
In this embodiment, the material of the active layer 4 includes IGZO, IZTO, or IGZTO.
Referring to fig. 3, the present invention further provides a method for manufacturing an array substrate 100, including the following steps S1-S9:
s1, manufacturing a barrier layer, namely manufacturing a barrier layer 2 on a glass substrate 1;
s2, a buffer layer manufacturing step, namely manufacturing a buffer layer 3 on the glass substrate 1 through chemical vapor deposition SiOx, wherein the buffer layer 3 completely covers the barrier layer 2;
s3, manufacturing an active layer, namely manufacturing an active layer 4 on the buffer layer 3, wherein the active layer 4 is arranged corresponding to the barrier layer 2; the material of the active layer 4 comprises IGZO, IZTO or IGZTO; as shown in fig. 4, fig. 4 is a schematic structural diagram of the completed active layer 4;
s4, manufacturing a gate insulation layer, namely manufacturing a gate insulation layer 5 on the active layer 4 through chemical vapor deposition SiOx;
s5, manufacturing a grid layer, namely manufacturing a grid layer 6 on the grid insulating layer 5; the gate layer 6 can be manufactured by a Mo/Ti/Cu sputtering mode; as shown in fig. 5, fig. 5 is a schematic structural diagram of the completed gate layer 6;
s6, forming an interlayer insulating layer 7 on the gate layer 6 by chemical vapor deposition of SiOx;
s7, manufacturing a source drain layer, namely manufacturing a source drain layer 8 on the interlayer insulating layer 7; the source drain electrode layer 8 can be manufactured by a Mo/Ti/Cu sputtering mode, and patterns are etched to be used as a source electrode lead and a drain electrode lead; as shown in fig. 6, fig. 6 is a schematic structural diagram of the source/drain layer 8 after fabrication; and
s8, manufacturing a passivation layer, namely manufacturing a passivation layer 9 on the source drain layer 8 through chemical vapor deposition SiOx;
s9, manufacturing an anode layer, namely manufacturing the anode layer 10 on the passivation layer 9, and etching a through hole on the passivation layer 9 to realize the electrical connection between the anode layer 10 and the source drain layer 8; as shown in fig. 2, fig. 2 is a schematic structural diagram of the completed anode layer 10.
Referring to fig. 7, the step S9 of fabricating the anode layer specifically includes steps S91-S95:
s91, a step of forming a first conductive layer 11; the material of the first conductive layer 11 includes indium tin oxide;
s92, forming a reflective metal layer 12 on the first conductive layer 11; the material of the reflective metal layer 12 comprises silver;
s93, manufacturing an anti-crystallization layer 13 on the reflecting metal layer 12; the material of the anti-crystallization layer 13 comprises copper; the thickness of the anti-crystallization layer 13 is 5 angstroms to 100 angstroms, so that the growth of the second conductive layer 14 is induced by the thickness of at least one atomic layer, and the reflection effect of the reflective metal layer 12 is not affected by the overlarge thickness of the anti-crystallization layer;
s94, a step of forming a second conductive layer, forming a second conductive layer 14 on the anti-crystallization layer 13; the material of the second conductive layer 14 includes indium tin oxide; and
s95, etching the anode layer 10 for patterning, wherein the anti-crystallization layer 13 is used to prevent the second conductive layer 14 from crystallizing on the reflective metal layer 12 when the anode layer 10 is etched.
The etched pattern of the anode layer 10 is any one or more of a circle, a rectangle, a triangle or a polygon, and can be used for adjusting the optical cavity length and improving the device performance.
The invention has the beneficial effects that: the array substrate and the manufacturing method of the array substrate are provided, an extremely thin film of other metals such as copper and the like is prepared on a silver-based reflective metal layer to serve as an anti-crystallization layer to avoid the crystallization phenomenon of silver-induced indium tin oxide, the condition that indium tin oxide is left due to the fact that a second conductive layer made of indium tin oxide is crystallized on the reflective metal layer when an anode layer is etched is avoided, the etching difficulty is reduced, the production efficiency and the qualification rate are improved, the voltage Drop (IR-Drop) phenomenon of a large panel is reduced, and the display effect is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and adaptations can be made without departing from the principle of the present invention, and such modifications and adaptations should also be considered as the scope of the present invention.
Claims (6)
1. An array substrate, wherein an anode layer is provided, the anode layer comprising:
a first conductive layer; the first conducting layer is made of indium tin oxide;
the reflecting metal layer is arranged on the first conducting layer; the material of the reflecting metal layer comprises silver;
the anti-crystallization layer is arranged on the reflection metal layer; the material of the anti-crystallization layer comprises copper; and
the second conducting layer is arranged on the anti-crystallization layer; the second conducting layer is made of indium tin oxide;
wherein the anti-crystallization layer is to prevent the second conductive layer from crystallizing on the reflective metal layer while the anode layer is etched.
2. The array substrate of claim 1, wherein the thickness of the anti-crystallization layer is 5 angstroms to 100 angstroms.
3. The array substrate of claim 1, wherein the array substrate comprises:
a glass substrate;
the barrier layer is arranged on the glass substrate;
the buffer layer is arranged on the glass substrate and completely covers the barrier layer;
the active layer is arranged on the buffer layer and corresponds to the barrier layer;
a gate insulating layer disposed on the active layer;
a gate electrode layer disposed on the gate insulating layer;
an interlayer insulating layer disposed on the gate electrode layer;
the source drain layer is arranged on the interlayer insulating layer; and
the passivation layer is arranged on the source drain electrode layer; the anode layer is arranged on the passivation layer and is electrically connected with the source drain layer.
4. The manufacturing method of the array substrate is characterized by comprising the step of manufacturing an anode layer, wherein the step of manufacturing the anode layer specifically comprises the following steps:
manufacturing a first conductive layer; the first conducting layer is made of indium tin oxide;
manufacturing a reflecting metal layer on the first conducting layer; the material of the reflecting metal layer comprises silver;
manufacturing an anti-crystallization layer on the reflecting metal layer; the material of the anti-crystallization layer comprises copper;
manufacturing a second conducting layer on the anti-crystallization layer; the second conducting layer is made of indium tin oxide; and
etching the anode layer for patterning, the anti-crystallization layer for preventing the second conductive layer from crystallizing on the reflective metal layer while the anode layer is etched.
5. The method for manufacturing the array substrate of claim 4, wherein the thickness of the anti-crystallization layer is 5-100 angstroms.
6. The method for manufacturing the array substrate according to claim 4, further comprising, before the step of manufacturing the anode layer:
manufacturing a barrier layer on a glass substrate;
manufacturing a buffer layer on the glass substrate, wherein the buffer layer completely covers the barrier layer;
manufacturing an active layer on the buffer layer, wherein the active layer is arranged corresponding to the barrier layer;
manufacturing a grid electrode insulating layer on the active layer;
manufacturing a grid electrode layer on the grid electrode insulating layer;
manufacturing an interlayer insulating layer on the grid layer;
manufacturing a source drain layer on the interlayer insulating layer; and
manufacturing a passivation layer on the source drain layer; and manufacturing the anode layer on the passivation layer, wherein the anode layer is electrically connected with the source drain layer.
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