CN112635583A - Metallization electrode of p type polycrystalline silicon passivation contact - Google Patents
Metallization electrode of p type polycrystalline silicon passivation contact Download PDFInfo
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- 238000001465 metallisation Methods 0.000 title claims abstract description 114
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 85
- 238000002161 passivation Methods 0.000 title claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000005641 tunneling Effects 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 229910052733 gallium Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 19
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000000137 annealing Methods 0.000 description 16
- 230000000052 comparative effect Effects 0.000 description 15
- 230000006798 recombination Effects 0.000 description 13
- 238000005215 recombination Methods 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 11
- 238000005245 sintering Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 8
- 239000002002 slurry Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000007650 screen-printing Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 239000000969 carrier Substances 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 6
- 230000008025 crystallization Effects 0.000 description 6
- 238000011065 in-situ storage Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 5
- 239000003513 alkali Substances 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 5
- 229910017604 nitric acid Inorganic materials 0.000 description 5
- 238000005289 physical deposition Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910000905 alloy phase Inorganic materials 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
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Abstract
The invention provides a p-type polycrystalline silicon passivation contact metallization electrode which comprises a crystalline silicon substrate, a tunneling layer, a heavily-doped polycrystalline silicon layer, a first metallization layer and a third metallization layer, wherein the crystalline silicon substrate, the tunneling layer, the heavily-doped polycrystalline silicon layer, the first metallization layer and the third metallization layer are sequentially arranged in a stacked mode, the metal of the first metallization layer is matched with the work function of the polycrystalline silicon layer, and the third metallization layer is an Al layer or a Cu layer. The laminated metal layer in the metalized electrode realizes full-surface carrier collection, the carrier transmission performance of the first metalized layer is good, the first metalized layer is matched with the work function of a heavily-doped polysilicon layer, good ohmic contact can be formed, the diffusion coefficient of metal of the first metalized layer in the polysilicon is low, the diffusion of the third metalized layer to a silicon substrate is reduced, the metal introduction defects are reduced, the composition is reduced, and the metallization cost is reduced.
Description
Technical Field
The invention relates to the technical field of silicon batteries, in particular to a p-type polycrystalline silicon passivation contact metalized electrode.
Background
At present, the crystalline silicon battery occupies the mainstream of the market by virtue of the advantages of mature process, long service life, high efficiency and the like. In the crystalline silicon battery, the front and back surfaces of a battery piece are metalized to manufacture electrodes to conduct current. The step has great influence on the efficiency and the overall cost of the cell, and the optimization of the metallization process and the slurry has great significance on the further development of the crystalline silicon cell.
The ultimate efficiency of the crystalline silicon solar cell is 29%, and the efficiency loss comprises optical loss, electrical loss and composite loss; with the improvement of the quality of the silicon chip, the surface recombination loss becomes a key factor restricting the improvement of the battery efficiency. A passivated emitter and back contact (PERC) battery with extremely high attention is characterized in that an aluminum oxide/silicon nitride dielectric layer is introduced to the back for passivation, and local metal contact is adopted; compared with an aluminum back surface field (Al-BSF) technology, the PERC technology effectively reduces back surface carrier recombination and improves the conversion efficiency of the battery. However, there is still a high recombination rate in the electrode contact area at the opening in the backside of the PERC cell.
In order to further reduce the back recombination rate and realize the back integral passivation, a back passivation contact (TOPCon) structure is developed by Fraunhofer ISE (Fraunhofer ISE), the front surface of a TOPCon structure crystalline silicon battery is a diffusion junction, a front surface grid line electrode is formed through screen printing, and a layer of ultrathin silicon oxide layer and a highly doped polycrystalline silicon layer are prepared on the back surface of the battery to form a passivation structure. The silicon oxide layer in the structure can enable multiple photons to enter the polycrystalline silicon layer through a tunneling effect and a pinhole effect, reduce recombination with minority photons, and further collect the photons in the polycrystalline silicon layer by metal, so that recombination with direct contact of the metal is reduced, and the open-circuit voltage and the short-circuit current of the battery are improved. For a boron-doped p-type TOPCon structure cell, the front surface is a phosphorus-doped n + emitter and the back surface is p-TOPCon full-area passivation. The structure does not need back opening and extra local doping, simplifies the process while reducing the opening composition of the PERC battery, and has larger promotion space compared with the PERC battery in the battery efficiency. By 10 months of 2020, the production efficiency of TOPCon cell is 23.5% -24.0%, while the production efficiency of PERC is about 22.8% -23.0%, and the efficiency of TOPCon cell is significantly higher than that of PERC cell.
There are three main problems with TOPCon structural metallization, adhesion of metallization contacts and contact resistance, the problem of recombination of metallization contacts, of which it is more critical to solve the metal-induced recombination problem, and therefore further demands are made on metallization pastes.
The metallization mode of the crystalline silicon battery comprises electroplating deposition, physical vapor deposition, screen printing and the like. The screen printing process is lower in cost and is a common metallization means in industrialization. The slurry is printed on the surface of the silicon wafer by screen printing, and then the slurry and the silicon wafer form ohmic contact through drying and high-temperature sintering.
The back of the p-type cell usually adopts Al slurry, and on one hand, ohmic contact is formed for p-type polycrystalline silicon; on the other hand, Al is much cheaper than Ag, so that the cost of the slurry can be obviously reduced; however, aluminum forms an alloy phase with silicon at sintering temperatures (typically 700 ℃ to 900 ℃) and diffuses rapidly in silicon to a depth of up to tens of microns, resulting in significant recombination at the Al contact area. Therefore, during sintering, the polysilicon is inevitably burned through if an Al paste is used, resulting in a deterioration of the passivation quality of the p-type TOPCon structure. Furthermore, in p-TOPCon structures, to improve optical performance, polysilicon is typically made thinner, which results in more significant penetration of Al metal, exacerbating the severity of the problem.
Disclosure of Invention
The technical problem solved by the invention is to provide a p-type polycrystalline silicon passivated contact metallized electrode which can limit and inhibit the diffusion of outer layer metal to a silicon substrate.
In view of this, the present application provides a p-type polysilicon passivation contact metallization electrode, which includes a crystalline silicon substrate, a tunneling layer, a heavily doped polysilicon layer, a first metallization layer and a third metallization layer, which are sequentially stacked, wherein a metal of the first metallization layer is matched with a work function of the polysilicon layer, and the third metallization layer is an Al layer or a Cu layer.
Preferably, the back electrode further comprises a second metallization layer disposed between the first metallization layer and the third metallization layer.
Preferably, the thickness of the second metallization layer is 10-200 nm.
Preferably, the second metallization layer is an Ag layer.
Preferably, the tunneling layer is SiOxA layer or a silicon oxynitride layer.
Preferably, the heavily doped polysilicon layer is a boron-doped polysilicon layer or a gallium-doped polysilicon layer.
Preferably, the metal of the first metallization layer is selected from Ti, Pd, Ni or Cr.
Preferably, the thickness of the tunneling layer is less than 5nm, the thickness of the heavily doped polysilicon layer is 20-500 nm, the thickness of the first metallization layer is 5-50 nm, and the thickness of the third metallization layer is 200-2000 nm or 10000-300000 nm.
Preferably, the doping concentration of the elements in the heavily doped polysilicon layer is 1E 17-5E 21cm-3。
The application provides a p-type polycrystalline silicon passivation contact metallization electrode which comprises a crystalline silicon substrate, a tunneling layer, a heavily doped polycrystalline silicon layer, a first metallization layer and a third metallization layer, wherein the crystalline silicon substrate, the tunneling layer, the heavily doped polycrystalline silicon layer, the first metallization layer and the third metallization layer are sequentially arranged in a stacked mode, the metal of the first metallization layer is matched with the work function of the heavily doped polycrystalline silicon layer, and the third metallization layer is an Al layer or a Cu layer; the metal of the first metallization layer can be matched with the work function of the polycrystalline silicon layer so as to form good ohmic contact with the heavily doped polycrystalline silicon layer, the diffusion coefficient in the polycrystalline silicon layer is low, the carrier transmission performance is good, interface adhesion and carrier collection are realized, and meanwhile, the penetration of Cu, Al and the like of the third metallization layer on the heavily doped polycrystalline silicon layer can be blocked. Further, a second metallization layer is included between the first metallization layer and the third metallization layer, and the second metallization layer is mainly a reflective layer to enhance reflection of light at the back surface.
Drawings
FIG. 1 is a schematic structural view of a TOPCon crystalline silicon cell prepared in comparative example 1 of the present invention;
fig. 2 is a schematic structural view of a back-side stacked metallization electrode of a TOPCon crystalline silicon cell prepared in example 1 of the present invention;
FIG. 3 is a schematic structural view of a TOPCon crystalline silicon cell of the present invention showing the basic passivation performance before metal electrode deposition;
fig. 4 is a schematic structural diagram of TOPCon crystalline silicon cells prepared in examples 2 and 3 of the present invention;
FIG. 5 is a schematic structural diagram of a sample when a TOPCon structure crystalline silicon cell of the present invention is etched away a metal electrode to test passivation effect;
FIG. 6 is a graph of pre-metallization passivation plate p-type polysilicon under carrier diffusion data for a metallized electrode prepared in example 1;
FIG. 7 is a graph of pre-metallization passivation plate p-type polysilicon under carrier diffusion data for a metallized electrode prepared in example 2;
FIG. 8 is a graph of the data for the diffusion of carriers under p-type polysilicon from a pre-metallization passivation segment for a metallized electrode prepared in example 3, respectively;
FIG. 9 is a graph of pre-metallization passivation patch p-type polysilicon under carrier diffusion data for a metallized electrode prepared in comparative example 1;
fig. 10 is a graph of the pre-metallization passivation patch p-type polysilicon under carrier diffusion data for the metallized electrode prepared in comparative 2.
Detailed Description
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
In view of the problem that the passivation quality is reduced due to Al metal penetration in the p-type polycrystalline silicon passivation contact, the application provides a metallization electrode, wherein a first metallization layer and a third metallization layer which are in contact with the heavily doped polycrystalline silicon layer are arranged in the metallization electrode, and a second metallization layer can be arranged between the first metallization layer and the third metallization layer according to needs; the second layer of metal adopts Ag to improve the conductivity of the structure, enhance the reflection and improve the passivation performance; the third metallization layer adopts Al or Cu, so that the cost of the structure is reduced. The invention discloses a p-type polycrystalline silicon passivation contact metallization electrode, which comprises a crystalline silicon substrate, a tunneling layer, a heavily doped polycrystalline silicon layer, a first metallization layer and a third metallization layer which are sequentially overlapped, wherein the metal of the first metallization layer is matched with the work function of the polycrystalline silicon layer, and the third metallization layer is an Al layer or a Cu layer.
In the metallization electrode of the p-type polysilicon passivation contact described in the present application (the specific result is shown in fig. 2), the crystalline silicon substrate is a crystalline silicon substrate well known to those skilled in the art, and the present application is not particularly limited thereto.
The tunneling layer on the surface of the crystalline silicon substrate is specifically an ultrathin dielectric layer which can be SiOxA layer, which may also be a silicon oxynitride layer; the thickness of the tunneling layer is less than 5nm, and in a specific embodiment, the thickness of the tunneling layer is 1.2-2.2 nm. The tunneling layer can enable multi-photon tunneling to the heavily doped polysilicon layer, so that minority-electron recombination is effectively prevented, and meanwhile, the heavily doped polysilicon layer can prevent metal from being in direct contact with the substrate, so that deep level defect recombination caused by metal is reduced.
The heavily doped polysilicon layer on the surface of the tunneling layer is a boron-doped polysilicon film or a gallium-doped polysilicon film, and the thickness of the heavily doped polysilicon layer is 20-500 nm, in some embodiments, the thickness of the heavily doped polysilicon layer is 30-400 nm, and in some embodiments, the thickness of the heavily doped polysilicon layer is 50-200 nAnd m is selected. The doping concentration of the heavily doped polysilicon layer is 1E 17-5E 21cm-3Preferably 5E 18-5E 19cm-3。
The metal matched with the work function formed by the heavily doped polysilicon layer forms a first metallization layer so as to form good ohmic contact with the heavily doped polysilicon layer, and meanwhile, the structure is compact, so that Al can be effectively prevented from diffusing to the heavily doped polysilicon layer at high temperature; more specifically, the metal of the first metallization layer is selected from Ti, Pd, Ni, Pt or Cr. The thickness of the first metallization layer is 5-50 nm, in some embodiments 10-40 nm, and in some embodiments 20-30 nm. The diffusion coefficient of the metal elements of the first metallization layer in the polycrystalline silicon is low, and the diffusion of Al, Cu and the like in the third metallization layer to the crystalline silicon substrate can be effectively blocked; because the first metallization layer prevents the diffusion of the metal elements in the third metallization layer, a thinner heavily doped polysilicon layer can be adopted, and the recombination of carriers in the polysilicon layer is reduced; furthermore, the metal in the first metallization layer forms a good ohmic contact with the heavily doped polysilicon layer, and does not cause the equilibrium carrier concentration inside the polysilicon passivation contact to change significantly when conducting carriers.
The third metallization layer is used for realizing charge transmission and can be selected from Al and Cu; if the third metallization layer is a full-surface covering type back electrode, the thickness is 200-2000 nm; in the case of a grid line electrode, the thickness is 10000-300000 nm, and in some embodiments, the thickness of the third metallization layer is 100-200 nm. Preferably, a second metallization layer, specifically a reflective layer, is disposed between the first metallization layer and the third metallization layer to improve reflection of light at the back surface and improve passivation performance, so as to improve overall conductivity of the electrode and reduce resistivity. The metal of the second metallization layer is selected from Ag and has a thickness of 10-200 nm, in some embodiments, the thickness of the second metallization layer is 30-150 nm, and in some embodiments, the thickness of the second metallization layer is 50-100 nm.
Each layer of the p-type polycrystalline silicon passivation contact metallized electrode is prepared respectively, wherein a tunneling layer adopts a wet chemical oxidation method, a high-temperature oxidation method or a plasma auxiliary oxidation method; the heavily doped polysilicon layer can be prepared by combining Plasma Enhanced Chemical Vapor Deposition (PECVD) with an in-situ doping method or a non-in-situ doping method, a low-pressure chemical vapor deposition (LPCVD) with an in-situ doping method or a non-in-situ doping method, other physical vapor deposition methods (PVD) such as magnetron sputtering and the like with an in-situ doping method or a non-in-situ doping method and the like, then crystallizing the film by high-temperature annealing (500-1100 ℃, the typical temperature is 680-1000 ℃), activating doping atoms, and leading the dielectric layer to undergo structural relaxation in the high-temperature treatment process so as to reduce the density of defect states; the metallization layer structure can be prepared in sequence by adopting a physical vapor deposition method and a screen printing method, and a surface silicon oxide layer is removed by HF before the metallization layer is prepared; finally, annealing and sintering are carried out, and the metallized electrode which forms good contact with the polycrystalline silicon layer can be obtained.
The application provides a p-type polycrystalline silicon passivation contact metallization electrode, which introduces a three-layer metal layer structure, wherein the first layer realizes interface adhesion, carrier collection and inhibits outer-layer metal from diffusing to a silicon substrate, so that metal introduction defects are reduced, metal contact recombination loss is reduced, and metallization cost is reduced; the middle layer is a reflecting layer, so that the reflection of light on the back surface is improved; the third layer is a low-cost metal layer which plays a role in charge transmission and simultaneously reduces the metallization cost; the innovation point is that the first metallization layer has low diffusion coefficient in silicon and good carrier transmission performance, can form good ohmic contact with the heavily doped polysilicon layer, and can block Cu, Al and the like from penetrating through the doped layer. The diffusion concentration of carriers under the P-type polysilicon is as follows: silicon oxide interface carrier concentration>1e19cm-3。
For further understanding of the present invention, the crystalline silicon cell with p-type TOPCon structure provided by the present invention is described in detail below with reference to the following examples, and the scope of the present invention is not limited by the following examples.
1) Physical vapor deposition of metal embodiments
To facilitate understanding, this example further details the specific implementation of the present application, and describes only a part of the examples of the present application, but does not include all examples. The present embodiments are described in sufficient detail to enable a full understanding of the invention, but the invention may be practiced in other ways than those specifically described and is not limited to the specific embodiments disclosed below.
The method comprises the following steps: taking a p-type silicon wafer, and carrying out a standard RCA cleaning process on the silicon wafer to obtain a clean surface;
step two: HNO at 95-105 ℃ by adopting wet method3Preparing a double-sided oxide layer with the thickness of 1.5-2 nm by medium oxidation for 15 min; the method for implementing this step is not particularly limited, and may be selected by itself, such as plasma method, thermal oxidation method, etc.; the oxide layer is a silicon oxide layer or a silicon oxynitride layer or the like;
step three: placing the silicon wafer with the oxide layer prepared into PECVD (plasma enhanced chemical vapor deposition) to deposit a B-doped amorphous silicon layer, wherein the thickness of the B-doped amorphous silicon layer is 20-200 nm; the implementation method of this step is not specifically limited, and can be selected by self, such as normal pressure chemical vapor deposition method, low pressure chemical vapor deposition method, etc.;
step four: carrying out high-temperature crystallization on the sample on which the amorphous silicon layer is deposited in a diffusion annealing furnace, wherein the crystallization temperature is 800-950 ℃;
step five: soaking the sample in HF for 2min after crystallization to obtain a clean surface;
step six: depositing a comprehensive metal layer Ti/Ag/Al on the clean back surface by adopting physical vapor deposition; 10-30 nm of Ti layer, 50-100 nm of Ag layer and 100-200 nm of Al layer; the deposition method is not limited, and thermal evaporation coating, electron beam evaporation coating and the like can be selected automatically; the Ti layer in the laminated metal layer can be replaced by Pd, Ni, Cr and the like, the Ag layer can be selected according to preparation conditions and preparation cost, and the Al layer can be replaced by Cu;
step seven: and (3) rapidly annealing and sintering the metal sample at 650-850 ℃ to obtain the full-area metallized electrode.
2) Screen printing of metal embodiments
The method comprises the following steps: and taking a p-type silicon wafer, and carrying out a standard RCA cleaning process on the silicon wafer to obtain a clean surface.
Step two: preparing a double-sided oxide layer with the thickness of 1.5-2 nm by adopting a thermal oxidation method; the implementation method of this step is not specifically limited, and may be selected by itself, such as a plasma method, a chemical oxidation method, etc., and the oxide layer is a silicon oxide layer or a silicon oxynitride layer, etc.;
step three: placing the silicon wafer with the oxide layer prepared into PECVD (plasma enhanced chemical vapor deposition) to deposit a B-doped amorphous silicon layer, wherein the thickness of the B-doped amorphous silicon layer is 20-200 nm; the implementation method of this step is not specifically limited, and can be selected by itself, such as normal pressure chemical vapor deposition method, low pressure chemical vapor deposition method, etc.;
step four: carrying out high-temperature crystallization on the sample on which the amorphous silicon layer is deposited in a diffusion annealing furnace, wherein the crystallization temperature is 800-950 ℃;
step five: soaking the sample in HF for 2min after crystallization to obtain a clean surface;
step six: sequentially printing a first layer of metal paste containing Ti, a second layer of metal paste containing Ag and a third layer of metal paste containing Al on the back surface according to the pattern by adopting a screen printing method; the Ti slurry in the laminated metal layer can be replaced by Pd, Ni, Cr and the like, and the Ag slurry can be selected according to preparation conditions and preparation cost; the Al slurry can be replaced by Cu;
step seven: and (3) rapidly annealing and sintering the metal sample at 650-950 ℃ to obtain the grid line metallized electrode.
The metallized electrode was prepared according to the above method, and the specific examples are as follows:
example 1Ti
Cleaning a p-type substrate by an RCA standard cleaning process, performing double-sided alkali polishing, preparing ultrathin silicon oxide layers on the front and back surfaces of a silicon wafer by a nitric acid oxidation method, preparing double-sided 30nm boron-doped amorphous silicon oxide films by a PECVD method, performing high-temperature annealing at 850-950 ℃ to form polycrystalline silicon films, and collecting data of a minority carrier lifetime meter; performing HF treatment on the annealed passivation sheet to remove an oxide layer, depositing a comprehensive metal electrode by adopting an electron beam physical deposition method, wherein a Ti layer is deposited by 10nm, an Ag layer is deposited by 0nm, an Al layer is deposited by 100nm, and performing rapid annealing sintering at 700-800 ℃ to form good contact between the electrode and a polycrystalline silicon layer so as to obtain a metallized sample; to verify the effect of the Ti layer in the metallization stack, HNO was used3And the metallization layer is etched with HF,collecting data of the minority carrier lifetime instrument, wherein the result is shown in table 1;
comparative example 1 no Ti
Cleaning a p-type substrate by an RCA standard cleaning process, performing double-sided alkali polishing, preparing ultrathin silicon oxide layers on the front and back surfaces of a silicon wafer by a nitric acid oxidation method, preparing double-sided 30nm boron-doped amorphous silicon oxide films by a PECVD method, performing high-temperature annealing at 850-950 ℃ to form polycrystalline silicon films, and collecting data of a minority carrier lifetime meter; performing HF treatment on the annealed passivation sheet to remove an oxide layer, depositing a comprehensive metal electrode by adopting an electron beam physical deposition method, wherein a Ti layer is deposited to be 0nm, an Ag layer is deposited to be 0nm, an Al layer is deposited to be 100nm, and performing rapid annealing sintering at 700-800 ℃ to form good contact between the electrode and a polycrystalline silicon layer so as to obtain a metallized sample (the structure is shown in figure 1); to verify the effect of Ti-free layer in the metallization stack, HNO was used3Etching the metallization layer with HF, and collecting the data of the minority carrier lifetime tester, wherein the result is shown in Table 1;
table 1 typical results of passivation for example 1 and comparative example 1 comparative data table
Example 1 and comparative example 1 show that the metallization layer comprising a high temperature treatment in the presence of the first metallization layer Ti does not negatively affect the passivation effect, the Ti layer effectively preventing the Al layer from diffusing.
Example 2Ti
Cleaning a p-type substrate by an RCA standard cleaning process, performing double-sided alkali polishing, preparing ultrathin silicon oxide layers on the front and back surfaces of a silicon wafer by a nitric acid oxidation method, preparing double-sided 30nm boron-doped amorphous silicon oxide films by a PECVD method, performing high-temperature annealing at 850-950 ℃ to form polycrystalline silicon films, and collecting data of a minority carrier lifetime meter; HF treatment is carried out on the annealed passivation piece to remove an oxide layer, and the electron beam physical deposition method is adopted to deposit the comprehensive metalAn electrode, wherein a Ti layer is deposited to 10nm, an Ag layer is deposited to 20nm, an Al layer is deposited to 100nm, and the electrode and a polycrystalline silicon layer form good contact through rapid annealing sintering at 700-800 ℃ to obtain a metallized sample; to verify the effect of the Ti layer in the metallization stack, HNO was used3And etching the metallization layer with HF, and collecting the test data of the minority carrier lifetime instrument.
Comparative example 2 no Ti
Cleaning a p-type substrate by an RCA standard cleaning process, performing double-sided alkali polishing, preparing ultrathin silicon oxide layers on the front and back surfaces of a silicon wafer by a nitric acid oxidation method, preparing double-sided 30nm boron-doped amorphous silicon oxide films by a PECVD method, performing high-temperature annealing at 850-950 ℃ to form polycrystalline silicon films, and collecting data of a minority carrier lifetime meter; performing HF treatment on the annealed passivation sheet to remove an oxide layer, depositing a comprehensive metal electrode by adopting an electron beam physical deposition method, wherein a Ti layer is deposited to be 0nm, an Ag layer is deposited to be 20nm, an Al layer is deposited to be 100nm, and performing rapid annealing sintering at 700-800 ℃ to form good contact between the electrode and a polycrystalline silicon layer so as to obtain a metallized sample; to verify the effect of the metallization stack without a Ti layer, HNO was used3The metallization layer was etched with HF and data from the minority carrier lifetime tester was collected with the results shown in table 2.
Table 2 typical results of passivation for example 2 and comparative example 2 table of comparative data
Example 2 and comparative example 2 show that the metallization layer containing high temperature treatment in the presence of the first metallization layer Ti does not negatively affect the passivation effect, the Ti layer effectively prevents the Al layer from diffusing, and the second metal layer Ag alone does not have the effect of blocking the Al diffusion.
Example 3Cr
Cleaning a p-type substrate by an RCA standard cleaning process, performing double-sided alkali polishing, preparing ultrathin silicon oxide layers on the front and back surfaces of a silicon wafer by a nitric acid oxidation method, preparing double-sided 30nm boron-doped amorphous silicon oxide films by a PECVD method, performing high-temperature annealing at 850-950 ℃ to form polycrystalline silicon films, and collecting data of a minority carrier lifetime meter;performing HF treatment on the annealed passivation sheet to remove an oxide layer, depositing a comprehensive metal electrode by adopting an electron beam physical deposition method, wherein a Cr layer is deposited by 10nm, an Ag layer is deposited by 20nm, an Al layer is deposited by 100nm, and performing rapid annealing sintering at 700-800 ℃ to form good contact between the electrode and a polycrystalline silicon layer so as to obtain a metallized sample; to verify the role of the Cr layer in the metallization stack, HNO was used3And etching the metallization layer with HF, and collecting the test data of the minority carrier lifetime instrument.
Table 3 typical results of passivation for example 3 and comparative example 2 comparative data table
Example 3 and comparative example 2 show that the metallization layer comprising a high temperature treatment in the presence of the first metallization layer Cr has no negative effect on the passivation effect, and that the Cr layer is also effective in preventing the Al layer from diffusing.
FIGS. 6-10 are graphs of the diffusion data of carriers under p-type polysilicon of the pre-metallization passivation pieces of the metallized electrodes prepared in examples 1-3 and comparative examples 1-2, respectively, and it can be seen that the concentration of carriers at the silicon oxide interface of the metallized electrode prepared in the present application is shown>1e19cm-3。
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. The p-type polycrystalline silicon passivation contact metallization electrode is characterized by comprising a crystalline silicon substrate, a tunneling layer, a heavily-doped polycrystalline silicon layer, a first metallization layer and a third metallization layer which are sequentially stacked, wherein the metal of the first metallization layer is matched with the work function of the polycrystalline silicon layer, and the third metallization layer is an Al layer or a Cu layer.
2. The metallized electrode of claim 1, wherein the back electrode further comprises a second metallization layer disposed between the first metallization layer and the third metallization layer.
3. The metallized electrode of claim 2, wherein the second metallization layer has a thickness of 10nm to 200 nm.
4. The metallized electrode of claim 2, wherein the second metallization layer is a layer of Ag.
5. The metallized electrode of claim 1 or 2, wherein the tunneling layer is SiOxA layer or a silicon oxynitride layer.
6. The metallized electrode of claim 1 or 2, wherein the heavily doped polysilicon layer is a boron doped polysilicon layer or a gallium doped polysilicon layer.
7. The metallized electrode of claim 1 or 2, wherein the metal of the first metallization layer is selected from Ti, Pd, Ni or Cr.
8. The metalized electrode as recited in claim 1 or 2, wherein the tunneling layer has a thickness of less than 5nm, the heavily doped polysilicon layer has a thickness of 20 to 500nm, the first metalized layer has a thickness of 5 to 50nm, and the third metalized layer has a thickness of 200 to 2000nm or 10000 to 300000 nm.
9. The metalized electrode as recited in claim 1 or 2, wherein the heavily doped polysilicon layer has an element doping concentration of 1E 17-5E 21cm-3。
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