WO2023213024A1

WO2023213024A1 - Electrode structure of topcon battery, preparation method therefor and application thereof

Info

Publication number: WO2023213024A1
Application number: PCT/CN2022/113225
Authority: WO
Inventors: 叶继春; 曾俞衡; 盛江; 林娜; 杜浩江; 廖明墩; 闫宝杰; 王太强; 刘伟
Original assignee: 中国科学院宁波材料技术与工程研究所
Priority date: 2022-05-06
Filing date: 2022-08-18
Publication date: 2023-11-09
Also published as: CN115064600A

Abstract

The present invention provides an electrode structure of a TOPCon battery, the electrode structure comprising a back electrode and a front electrode. The back electrode is placed on a first passivation layer on the back side of a crystalline silicon substrate, the front electrode is placed on a second passivation layer on the front side of the crystalline silicon substrate, any electrode among the back electrode and the front electrode comprises a nickel seed layer and an aluminum electrode layer, the nickel seed layer is stacked on the first passivation layer or the second passivation layer, and the aluminum electrode layer is stacked on the nickel seed layer. The present invention provides an electrode structure of a TOPCon battery, the electrode structure employing a composite metal structure of the nickel seed layer and the aluminum electrode layer to replace a silver electrode in the prior art. The nickel seed layer can form a good ohmic contact with doped polycrystalline silicon.

Description

An electrode structure of a TOPCon battery and its preparation method and application

Technical field

The present invention relates to the technical field of solar cells, and specifically to an electrode structure of a TOPCon battery and its preparation method and application.

Background technique

Tunneling silicon oxide passivation contact technology (TOPCon) is a crystalline silicon solar cell proposed by the Fraunhofer Institute in Germany in 2013. The TOPCon structure has excellent surface passivation performance and can effectively improve battery efficiency. In the production of crystalline silicon solar cells, an important process is the production of back electrodes. Electrodes play the role of collecting and conducting current in solar cells. However, the current backside of TOPCon cells uses n-type doped polysilicon based on phosphorus doping, which requires the use of silver paste to form a good contact.

Most of the existing n-type TOPCon batteries use silver paste on the back. Due to the high unit price of silver, the cost of n-type TOPCon batteries using silver paste on the back increases significantly, resulting in that the cost of electricity is still higher than the current mainstream PERC in industrialization. batteries, affecting mass production promotion; and as a precious metal, silver’s abundance in the earth’s crust is significantly lower than that of aluminum, and the annual global silver production is very limited. When silicon-based solar cells develop to an annual output of terawatts When the above situation occurs, global silver production will be unable to meet the demand of the photovoltaic industry, which will lead to further rise in silver prices.

For this reason, there is a technical solution in the existing technology that directly uses aluminum paste to replace silver paste. However, the application effect of aluminum paste on n-type TOPCon is not good for the following two reasons:

1) Because during sintering, silicon atoms will quickly dissolve into Al, causing polysilicon to be penetrated and the passivation effect to be completely destroyed.

2) Al may penetrate to a depth of several microns or more than ten microns below the surface of the silicon wafer, and it is difficult for Al to form a good ohmic contact with the n-type silicon wafer.

Contents of the invention

The present invention aims to solve one of the technical problems in the related art, at least to a certain extent. To this end, an electrode structure of a TOPCon battery is provided, which uses a composite metal structure of a nickel seed layer and an aluminum electrode layer to replace the silver electrode in the existing technology. The nickel seed layer can form good ohmic contact with doped polysilicon.

In order to solve the above problems, the present invention provides an electrode structure of a TOPCon battery, including a back electrode and a front electrode. The back electrode is placed on the first passivation layer on the back side of the crystalline silicon substrate, and the front electrode is placed on the back electrode. On the second passivation layer on the front side of the crystalline silicon substrate, any one of the back electrode and the front electrode includes a nickel seed layer and an aluminum electrode layer, and the nickel seed layer is superimposed on the first passivation layer. layer or the second passivation layer, and the aluminum electrode layer is superimposed on the nickel seed layer.

Compared with the existing technology, the nickel seed layer in the above-mentioned battery structure is very dense and can effectively block the penetration of aluminum paste, thus protecting the good passivation performance of the TOPCon structure.

Optionally, a tunnel oxide layer and a doped polysilicon layer are provided between the crystalline silicon substrate and the first passivation layer. When the doped polysilicon layer is n-type phosphorus-doped polysilicon, the first The main component of the nickel seed layer on the passivation layer is NiP _x ; when the doped polysilicon layer is p-type boron doped polysilicon, the main component of the nickel seed layer on the first passivation layer is NiB _x .

Optionally, the first passivation layer is composed of an aluminum oxide layer and a silicon nitride layer, and a side of the aluminum oxide layer away from the silicon nitride layer is compounded with the doped polysilicon layer.

Optionally, when the doped polysilicon layer is n-type phosphorus-doped polysilicon, the main component of the nickel seed layer on the second passivation layer is NiP _x ; when the doped polysilicon layer is p When type boron is doped into polysilicon, the main component of the nickel seed layer on the second passivation layer is _NiBx .

Optionally, the thickness of the nickel seed layer is 100-5000 nm.

Optionally, the nickel seed layer contains one or more trace elements of chromium, copper, tin, silver and sulfur.

Optionally, the total mass of the trace elements accounts for 0.01-1% of the total mass of the nickel seed layer.

The second object of the present invention is to provide a method for preparing an electrode structure of a TOPCon battery.

A method for preparing the electrode structure of a TOPCon battery as described in any one of the above, including the following steps:

S1. Prepare a tunnel oxide layer, a doped polysilicon layer and a first passivation layer on the back side of the crystalline silicon substrate, and prepare a doped emitter and a second passivation layer on the front side of the crystalline silicon substrate;

S2. Perform groove processing on the first passivation layer or the second passivation layer;

S3. Form a nickel seed layer in the groove opened in S2 through electroless nickel plating and annealing;

S4. Form an aluminum electrode layer on the nickel seed layer by screen printing and sintering.

Compared with the existing technology, the above method for preparing the battery structure has the following advantages:

(1) Plate a nickel seed layer on the doped polysilicon layer through electroless plating technology. Plate a nickel seed layer on the doped polysilicon layer through electroless plating technology. By adjusting the composition of the seed layer and annealing treatment, it can be combined with the doped polysilicon layer. Hybrid polysilicon forms a good ohmic contact. .

(2) The electroless nickel plating seed layer is very dense and can effectively block the penetration of aluminum slurry, thus protecting the good passivation performance of the TOPCon structure.

(3) Electroless nickel plating has self-aligning properties and only deposits on polysilicon, which helps simplify the process complexity. Moreover, the material cost of the electroless nickel plating seed layer is low and easy to achieve mass production.

(4) The electrode structure still maintains the screen printing aluminum paste, which has higher productivity and lower cost than the electroplating method. The electrode uses nickel and aluminum metal, which has good chemical stability and can effectively maintain the stability of the battery.

Optionally, the annealing temperature in step S3 is 150-600°C, and the annealing time is 5-15 minutes.

Optionally, the sintering temperature in step S4 is 400-600°C, and the sintering time is 1-2 minutes.

The third object of the present invention is to provide a crystalline silicon battery using the electrode structure of a TOPCon battery.

A crystalline silicon battery that applies the electrode structure of any of the above-mentioned TOPCon batteries.

Optionally, the crystalline silicon cell includes, from bottom to top, a back electrode, a first passivation layer, a doped polysilicon layer, a tunnel oxide layer, a crystalline silicon substrate, a doped emitter, a second passivation layer and a front electrode.

Description of the drawings

Figure 1 is a schematic structural diagram of a TOPCon battery in Embodiment 1 of the present invention;

Figure 2 is a schematic structural diagram of a TOPCon battery in Embodiment 2 of the present invention.

Detailed ways

The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

In this embodiment, the tunnel oxide layer 2 on the back side of the crystalline silicon substrate 1 is also called an ultra-thin silicon oxide layer, which is essentially an ultra-thin dielectric layer. It can be a SiOx layer or a silicon oxynitride layer; The thickness is <5 nm. In specific embodiments, the thickness of the tunnel oxide layer 2 is 1.2-2.2 nm. The tunnel oxide layer 2 can enable multicarriers to tunnel into the heavily doped polysilicon layer 3, effectively preventing minority carrier recombination. At the same time, the heavily doped polysilicon layer 3 can prevent direct contact between the metal and the substrate, reducing the recombination of deep energy level defects introduced by the metal. .

Further, in this embodiment, the preparation method of the tunnel oxide layer 2 includes: thermal nitric acid oxidation method, rapid thermal oxidation method (RTO), ultraviolet ozone method (UV/O ₃ ), ozone deionized water method (DIO ₃ ), thermal oxidation method, PECVD-N ₂ O method, mixed acid oxidation method, etc., aiming to prepare ultra-thin, high-quality silicon oxide layer with low interface defect state density.

In this embodiment, the first passivation layer 4 is a SiNx layer, a composite layer of a SiNx layer and an AlOx layer, or a composite layer of a SiNx layer and a SiOx layer.

Further, in a specific embodiment, the first passivation layer 4 is composed of a composite of AlO _x and SiN _x , and the side of AlO _x away from SiN _x is composited with the doped polysilicon layer 3 . SiN _x acts as a protective layer to reduce high-temperature damage that may be caused by sintering. At the same time, hydrogenated SiN _x can also passivate polysilicon through its own hydrogen during the sintering process.

As shown in Figure 1, the electrode structure of the TOPCon battery in this embodiment includes a back electrode 5 and a front electrode 8. The back electrode 5 is placed on the first passivation layer 4 on the back side of the crystalline silicon substrate 1, so The front electrode 8 is placed on the second passivation layer 7 on the front side of the crystalline silicon substrate 1 , and any one of the back electrode 5 and the front electrode 8 includes nickel seed layers 51 and 81 and an aluminum electrode layer 52 , 82, that is, the back electrode 5 includes a nickel seed layer 51 and an aluminum electrode layer 52, then the front electrode 8 is a conventional electrode; or the front electrode 5 includes a nickel seed layer 81 and an aluminum electrode layer 82, then the back electrode 5 is a conventional electrode. The nickel seed layers 51 and 81 are superimposed on the first passivation layer 4 or the second passivation layer 7 , and the aluminum electrode layers 52 and 82 are superimposed on the nickel seed layers 51 and 81 .

Specifically, a tunnel oxide layer 2 and a doped polysilicon layer 3 are provided between the crystalline silicon substrate 1 and the first passivation layer 4. When the doped polysilicon layer 3 is n-type phosphorus-doped polysilicon, The main component of the nickel seed layer 51 on the first passivation layer 4 is NiP _x ; when the doped polysilicon layer 3 is p-type boron-doped polysilicon, the nickel seed layer 51 on the first passivation layer 4 The main component of the nickel seed layer 51 is _NiBx .

Specifically, the first passivation layer 4 is composed of an aluminum oxide layer and a silicon nitride layer, and the side of the aluminum oxide layer away from the silicon nitride layer is compounded with the doped polysilicon layer 3 .

Specifically, the thickness of the nickel seed layers 51 and 81 is 100-5000 nm.

Specifically, the nickel seed layers 51 and 81 contain one or more trace elements among chromium, copper, tin, silver and sulfur, and the sum of the masses of the trace elements accounts for the total mass of the nickel seed layers 51 and 81 0.01-1% of mass.

The trace element added in this embodiment is specifically sulfur. During the cathode reaction process of electroless plating, the trace sulfite ions contained in the plating solution have the opportunity to be reduced to sulfur atoms and doped in the nickel plating layer. The chemical Plating includes electric-assisted electroless plating, light-assisted electroless plating, and sensitized electroless plating.

The preparation method of the electrode structure of the TOPCon battery in this embodiment includes the following steps:

S1. Prepare the tunnel oxide layer 2, the doped polysilicon layer 3 and the first passivation layer 4 on the back side of the crystalline silicon substrate 1, and prepare the doped emitter 6 and the second passivation layer on the front side of the crystalline silicon substrate 1. 7;

S2. Perform groove processing on the first passivation layer 4 or the second passivation layer 7;

S3. Form nickel seed layers 51 and 81 in the groove opened in S2 through electroless nickel plating and annealing;

S4. Form aluminum electrode layers 52 and 82 on the nickel seed layers 51 and 81 by screen printing and sintering.

In step S2, when the first passivation layer 4 is grooved, an electrode grid profile is formed on the surface of the first passivation layer 4, and the doped polysilicon layer 3 is exposed at the bottom of the groove. When the second passivation layer 7 is grooved, an electrode grid profile is formed on the surface of the second passivation layer 7, and the doped emitter layer 6 is exposed at the bottom of the groove.

Specifically, the specific process of the preparation method of the electrode structure of the TOPCon battery is as follows:

1) Use openings on the backside Al ₂ O ₃ /SiN _x stack to expose the bottom doped polysilicon layer 3. The method of opening holes can usually be laser drilling; it can also be patterned by photolithography, spraying, printing, etc., and then the holes can be formed by etching.

2) Under the induction of light field, electric field, or sensitizer, use electroless plating method to directly deposit a layer of nickel seed layer 51 on the doped polysilicon. The main component of the nickel layer is NiP _x , and also includes other necessary trace amounts. elements to adjust film properties. If it is n-type phosphorus-doped polysilicon, a NiP _x layer is usually used. Generally speaking, the thickness of the nickel layer ranges from 100nm to 5000nm. It should be noted that the nickel layer is only deposited on the polysilicon layer and will not be deposited on the surface of the SiN _x layer, which has a self-alignment effect.

3) According to different needs, perform annealing treatments at 150-600°C for different times, usually using a nitrogen-hydrogen mixture as a protective atmosphere, so that the nickel seed layer 51 can form good ohmic contact with the doped polysilicon. Alternatively, according to process requirements, the nickel seed layer 51 can also be directly deposited without annealing, and then sintered together with the aluminum electrode layer 52 to form a good ohmic contact.

4) Then, screen printing is used to print aluminum paste on the nickel layer on the back, and then it is sintered in a chain furnace to form good ohmic contact between the aluminum paste and the nickel layer.

Example 1

n-type crystalline silicon substrate 1, clean, use thermal oxidation method to prepare tunnel oxide layer 2 on the backside, and then use PECVD to prepare 100nm heavily doped phosphorus amorphous silicon on the backside silicon oxide, and conduct 880-920℃ high temperature for different times Annealing to form doped polysilicon layer 3 and TOPCon structure, on the surface of n-type heavily doped polysilicon, a 2000nm thick nickel-phosphorus alloy is prepared by electroless plating, and then annealed under nitrogen-hydrogen mixture protection at 150-450°C. Test contact resistivity. After testing, the contact resistivity distribution is 0.1-5mΩcm2, which meets the application requirements of battery contact resistivity.

Example 2

N-type silicon wafers are passivated with TOPCon on both sides, and their polysilicon thickness is 100-300nm. The implied open circuit voltage iVoc of the original passivated sheet is 730mV, and the corresponding single-sided saturation current density is 6 fA/cm2. On one surface of n-type heavily doped polysilicon, a 500-3000nm thick nickel-phosphorus alloy is prepared by electroless plating, and then undergoes an annealing treatment under the protection of a nitrogen-hydrogen mixture at 150-250°C, and then screen-prints aluminum paste on it. And after sintering treatment at 700-800℃.

After testing, the saturation current density of the sintered metal contact area is 30-200fA/cm2, which meets the needs of battery applications.

Example 3

First, the n-type crystalline silicon substrate 1 is cleaned, and then the n-type crystalline silicon substrate 1 is textured on both sides, and boron is expanded on one side of the front surface of the n-type crystalline silicon substrate 1 to form a doped emitter 6, that is, boron emitter. The non-boron-expanded surface is subjected to acid etching to remove the boron-coated layer and textured surface, and a thermal oxidation method is used to prepare a tunnel oxide layer 2 on the back surface. PECVD is then used to prepare 100 nm of heavily doped phosphorus amorphous silicon on the back silicon oxide. ; Perform 880-920°C high temperature annealing for different times to form the doped polysilicon layer 3, pn junction and TOPCon structure, use aluminum oxide and silicon nitride to cover and deposit the front and rear surfaces, and form the first passivation on the surface of the doped polysilicon layer 3 Layer 4 forms a second passivation layer 7 on the surface of the doped emitter 6 . Subsequently, laser drilling is performed on the first passivation layer 4 to form an electrode grid profile on the surface of the first passivation layer 4, and the doped polysilicon layer 3 is exposed at the bottom of the trench. A 2000nm undoped nickel-phosphorus alloy layer is prepared in the tank by electroless plating, and annealed at 150-450°C to form a nickel seed layer 51 . Then, the aluminum electrode layer 52 is printed on the nickel alloy using a screen printing method, and then a belt furnace sintering process is performed. At the same time, a silver electrode is prepared on the surface of the second passivation layer 7 using a screen printing method, and finally a finished battery is produced.

After testing, it was verified that the average efficiency of the battery is greater than 23.3%.

Example 4

First, the n-type crystalline silicon substrate 1 is cleaned, and then the n-type crystalline silicon substrate 1 is textured on both sides, and boron is expanded on one side of the front surface of the n-type crystalline silicon substrate 1 to form a doped emitter 6, that is, boron emitter. The non-boron-expanded surface is subjected to acid etching to remove the boron-coated layer and textured surface, and a thermal oxidation method is used to prepare a tunnel oxide layer 2 on the back surface. PECVD is then used to prepare 100 nm of heavily doped phosphorus amorphous silicon on the back silicon oxide. ; Perform 880-920°C high temperature annealing for different times to form the doped polysilicon layer 3, pn junction and TOPCon structure, use aluminum oxide and silicon nitride to cover and deposit the front and rear surfaces, and form the first passivation on the surface of the doped polysilicon layer 3 Layer 4 forms a second passivation layer 7 on the surface of the doped emitter 6 . Subsequently, laser drilling is performed on the first passivation layer 4 to form an electrode grid profile on the surface of the first passivation layer 4, and the doped polysilicon layer 3 is exposed at the bottom of the groove. A 2000nm nickel-phosphorus alloy layer doped with 0.01-0.1% sulfur is prepared in a tank by electroless plating, and annealed at 150-450°C to form a nickel seed layer 51 . The aluminum electrode layer 52 is then printed on the undoped nickel alloy by screen printing, followed by belt furnace sintering. At the same time, a silver electrode is prepared on the surface of the second passivation layer 7 using a screen printing method, and finally a finished battery is produced.

After testing, it was verified that the average efficiency of the battery is greater than 24%.

Example 5

First, the n-type crystalline silicon substrate 1 is cleaned, and then the n-type crystalline silicon substrate 1 is textured on both sides, and boron is expanded on one side of the front surface of the n-type crystalline silicon substrate 1 to form a doped emitter 6, that is, boron emitter. The non-boron-expanded surface is subjected to acid etching to remove the boron-coated layer and textured surface, and a thermal oxidation method is used to prepare a tunnel oxide layer 2 on the back surface. PECVD is then used to prepare 100 nm of heavily doped phosphorus amorphous silicon on the back silicon oxide. ; Perform 880-920°C high temperature annealing for different times to form the doped polysilicon layer 3, pn junction and TOPCon structure, use aluminum oxide and silicon nitride to cover and deposit the front and rear surfaces, and form the first passivation on the surface of the doped polysilicon layer 3 Layer 4, a second passivation layer 7 is formed on the boron emitter. Then, the second passivation layer 7 is laser-drilled to form an electrode grid profile, and the doped emitter layer 6 is exposed at the bottom of the groove. A 2000nm undoped nickel-phosphorus alloy layer is prepared in the tank by electroless plating, and annealed at 150-450°C to form a nickel seed layer 81. The aluminum electrode layer 82 is then printed on the nickel alloy using a screen printing method, followed by a belt furnace sintering process. At the same time, a silver electrode is prepared by screen printing on the back of the first passivation layer 4, and finally a finished battery is produced.

After testing, it was verified that the average efficiency of the battery is approximately 23.5%.

Example 6

First, the n-type crystalline silicon substrate 1 is cleaned, and then the n-type crystalline silicon substrate 1 is textured on both sides, and boron is expanded on one side of the front surface of the n-type crystalline silicon substrate 1 to form a doped emitter 6, that is, boron emitter. The non-boron-expanded surface is subjected to acid etching to remove the boron-coated layer and textured surface, and a thermal oxidation method is used to prepare a tunnel oxide layer 2 on the back surface. PECVD is then used to prepare 100 nm of heavily doped phosphorus amorphous silicon on the back silicon oxide. ; Perform 880-920°C high temperature annealing for different times to form the doped polysilicon layer 3, pn junction and TOPCon structure, use aluminum oxide and silicon nitride to cover and deposit the front and rear surfaces, and form the first passivation on the surface of the doped polysilicon layer 3 Layer 4, a second passivation layer 7 is formed on the boron emitter. Then, the second passivation layer 7 is laser-drilled to form an electrode grid profile, and the doped emitter layer 6 is exposed at the bottom of the groove. A 2000nm nickel-phosphorus alloy layer doped with 0.01-0.1% sulfur is prepared by electroless plating, and annealed at 150-450°C to form a nickel seed layer 81 . An aluminum electrode layer 82 is then printed on the undoped nickel alloy using a screen printing method, followed by a belt furnace sintering process. At the same time, a silver electrode is prepared by screen printing on the back of the first passivation layer 4, and finally a finished battery is produced.

After testing, it was verified that the average efficiency of the battery is approximately 24.1%.

Comparative example 1

First, the n-type crystalline silicon substrate 1 is cleaned, and then the n-type crystalline silicon substrate 1 is textured on both sides, boron is expanded on one side of the front surface of the n-type crystalline silicon substrate 1, and the non-boron-expanded surface is acid-etched. Process to remove the boron plating layer and texture, use thermal oxidation method to prepare tunnel oxide layer 2 on the back, and then use PECVD to prepare 100nm heavily doped phosphorus amorphous silicon on the back silicon oxide; conduct 880-920℃ high temperature for different times Annealing is performed to form a doped polysilicon layer 3, a pn junction and a TOPCon structure, aluminum oxide and silicon nitride are used to cover and deposit the front and rear surfaces, and a first passivation layer 4 is formed on the surface of the doped polysilicon layer 3. Then, laser holes are opened, and then the aluminum paste electrode layer 52 is printed at the opening position by screen printing, and then the belt furnace sintering process is performed. The electrodes are prepared by screen printing on the front side at the same time.

After testing, it was verified that the average efficiency of the battery is approximately 18.7%.

Comparative example 2

First, the n-type crystalline silicon substrate 1 is cleaned, and then the n-type crystalline silicon substrate 1 is textured on both sides, boron is expanded on one side of the front surface of the n-type crystalline silicon substrate 1, and the non-boron-expanded surface is acid-etched. Process to remove the boron plating layer and texture, use thermal oxidation method to prepare tunnel oxide layer 2 on the backside, and then use PECVD to prepare 100nm heavily doped phosphorus amorphous silicon on the backside silicon oxide; conduct 880-920℃ high temperature for different times Annealing is performed to form a doped polysilicon layer 3, a pn junction and a TOPCon structure, aluminum oxide and silicon nitride are used to cover and deposit the front and rear surfaces, and a first passivation layer 4 is formed on the surface of the doped polysilicon layer 3. Then, a silver paste electrode layer 52 is printed on the first passivation layer using a screen printing method, and then a belt furnace sintering process is performed. The electrodes are prepared by screen printing on the front side at the same time.

After testing, it was verified that the average efficiency of the battery is approximately 23.8%.

Although the present disclosure is disclosed as above, the protection scope of the present disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and these changes and modifications will fall within the protection scope of the present invention.

Claims

An electrode structure of a TOPCon battery, including a back electrode (5) and a front electrode (8). The back electrode (5) is placed on the first passivation layer (4) on the back side of a crystalline silicon substrate (1), The front electrode (8) is placed on the second passivation layer (7) on the front side of the crystalline silicon substrate (1), and is characterized in that: between the back electrode (5) and the front electrode (8) Either electrode includes a nickel seed layer (51, 81) and an aluminum electrode layer (52, 82). The nickel seed layer (51, 81) is superimposed on the first passivation layer (4) or the second passivation layer. On the layer (7), the aluminum electrode layers (52, 82) are superimposed on the nickel seed layer (51, 81).
The electrode structure of a TOPCon battery according to claim 1, characterized in that: a tunnel oxide layer (2) and a doped layer are provided between the crystalline silicon substrate (1) and the first passivation layer (4). Hybrid polysilicon layer (3), when the doped polysilicon layer (3) is n-type phosphorus-doped polysilicon, the main component of the nickel seed layer (51) on the first passivation layer (4) is NiP x ; when the doped polysilicon layer (3) is p-type boron-doped polysilicon, the main component of the nickel seed layer (51) on the first passivation layer (4) is NiB x .
The electrode structure of a TOPCon battery according to claim 2, characterized in that the first passivation layer (4) is a silicon nitride layer or a composite layer of a silicon nitride layer and an aluminum oxide layer or a silicon nitride layer. A composite layer of silicon oxide layer and silicon oxide layer.
The electrode structure of a TOPCon battery according to claim 1, characterized in that when the doped polysilicon layer (3) is n-type phosphorus-doped polysilicon, the second passivation layer (7) The main component of the nickel seed layer (81) is NiPx ; when the doped polysilicon layer (3) is p-type boron-doped polysilicon, the nickel seed on the second passivation layer (7) The main component of layer (81) is NiBx .
The electrode structure of a TOPCon battery according to claim 1, characterized in that: the thickness of the nickel seed layer (51, 81) is 100-5000 nm.
The electrode structure of a TOPCon battery according to claim 1, characterized in that the nickel seed layer (51, 81) contains one or more trace elements among chromium, copper, tin, silver and sulfur.
The electrode structure of a TOPCon battery according to claim 6, characterized in that: the sum of the masses of the trace elements accounts for 0.01-1% of the total mass of the nickel seed layer (51, 81)
A method for preparing the electrode structure of a TOPCon battery according to any one of claims 1 to 7, characterized in that it includes the following steps:

S1. Prepare a tunnel oxide layer (2), a doped polysilicon layer (3) and a first passivation layer (4) on the back side of the crystalline silicon substrate (1), and prepare a doped polysilicon layer (3) on the front side of the crystalline silicon substrate (1). Miscellaneous emitter (6) and second passivation layer (7);

S2. Perform groove processing on the first passivation layer (4) or the second passivation layer (7);

S3. Form a nickel seed layer (51, 81) in the groove opened in S2 through electroless nickel plating and annealing;

S4. Form an aluminum electrode layer (52, 82) on the nickel seed layer (51, 81) by screen printing and sintering.
A crystalline silicon battery, characterized by applying the electrode structure of the TOPCon battery described in any one of claims 1-7.