CN112635575B - 一种高频impatt二极管台面管芯结构及制备方法 - Google Patents

一种高频impatt二极管台面管芯结构及制备方法 Download PDF

Info

Publication number
CN112635575B
CN112635575B CN202110041251.4A CN202110041251A CN112635575B CN 112635575 B CN112635575 B CN 112635575B CN 202110041251 A CN202110041251 A CN 202110041251A CN 112635575 B CN112635575 B CN 112635575B
Authority
CN
China
Prior art keywords
epitaxial layer
mesa
tube core
frequency
type epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110041251.4A
Other languages
English (en)
Other versions
CN112635575A (zh
Inventor
潘结斌
陈婧瑶
吕东锋
李文翰
史一明
李泽瑞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
No 214 Institute of China North Industries Group Corp
Original Assignee
No 214 Institute of China North Industries Group Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by No 214 Institute of China North Industries Group Corp filed Critical No 214 Institute of China North Industries Group Corp
Priority to CN202110041251.4A priority Critical patent/CN112635575B/zh
Publication of CN112635575A publication Critical patent/CN112635575A/zh
Application granted granted Critical
Publication of CN112635575B publication Critical patent/CN112635575B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66159Transit time diodes, e.g. IMPATT, TRAPATT diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/864Transit-time diodes, e.g. IMPATT, TRAPATT diodes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开一种高频IMPATT二极管台面管芯结构,包括p+导电基底,p+导电基底顶面设有台面管芯,其特征在于,所述台面管芯中央设有竖直的通孔,使台面管芯形成环形圆台状;制备时,在n+硅晶圆片上生长n型外延层、p型外延层及p+外延层;对n型外延层掺杂施主杂质n,p外延层掺杂受主杂质p;在p+外延层表面制备p+电极增强层;对n+硅晶圆片进行减薄;在n+硅晶圆片的减薄面制备n+电极增强层;按照台面管芯设计图形,通过光刻、腐蚀工艺,由n+电极增强层向p+外延层腐蚀,得到高频IMPATT二极管台面管芯结构;该结构能较好地减小器件高频工作状态下因趋肤效应而引入的附加等效电阻,增大器件高频工作状态下的输出功率,提高器件的可靠性。

Description

一种高频IMPATT二极管台面管芯结构及制备方法
技术领域
本发明涉及毫米波固态器件技术领域,具体是一种高频IMPATT二极管台面管芯结构及制备方法。
背景技术
毫米波/太赫兹是一个发展迅速的交叉学科,科研学术价值和工业应用前景极其重要,可有效缩小系统体积,提高探测精度、抗干扰能力及无线通信传输速率等。雪崩碰撞渡越时间(IMPact Avalanche Transit Time简称IMPATT)二极管因其工作频率高、输出功率大等特点在毫米波/太赫兹无损检测、测速测距、雷达成像、无线通信等领域具有应用价值。
在毫米波频段,IMPATT二极管采用台面结构,这种结构可有效减小器件引入的寄生电容、电感效应,有利于提高器件工作频率和输出功率,随着器件工作频率的不断提升(100GHz以上),高频引起的趋肤效应作用明显,器件工作电流被限制在台面管芯表层深度δ以内流动,势必引起台面管芯有效电阻增加,在沿垂直台面IMPATT二极管半径方向产生电压降,该压降将使电流在台面IMPATT二极管结构上形成非均匀分布并产生有效串联电阻,从而引起器件直流功率转换成射频功率的效率降低。另外,趋肤效应在高频下也使器件产生隧道电流效应,破坏器件端电压-电流相位关系,很难提供180°的雪崩相位延迟,减小器件负阻。上述因素,将导致IMPATT二极管高频工作状态下器件输出功率降低、可靠性变差,器件极易烧毁等。
发明内容
本发明的目的在于提供一种高频IMPATT二极管台面管芯结构及制备方法,该IMPATT二极管台面管芯结构能较好地减小器件高频(100GHz以上)工作状态下因趋肤效应而引入的附加等效电阻,增大器件高频工作状态下的输出功率,提高器件的可靠性。
本发明解决其技术问题所采用的技术方案是:
一种高频IMPATT二极管台面管芯结构,包括p+导电基底,p+导电基底顶面设有台面管芯pn结,其特征在于,所述台面管芯中央设有竖直的通孔,使台面管芯形成环形圆台状。
进一步的,所述通孔下部的孔径由上至下渐缩。
本发明还提供一种高频IMPATT二极管台面管芯结构的制备方法,包括以下步骤:
S1、在n+硅晶圆片上生长n型外延层、p型外延层及p+外延层;
S2、对n型外延层掺杂施主杂质n,p外延层掺杂受主杂质p;
S3、在p+外延层表面制备p+电极增强层;
S4、对n+硅晶圆片进行减薄;
S5、在n+硅晶圆片的减薄面制备n+电极增强层;
S6、按照台面管芯设计图形,通过光刻、腐蚀工艺,由n+电极增强层向p+外延层腐蚀,得到所述的高频IMPATT二极管台面管芯结构。
本发明的有益效果是,通过在台面管芯中央设置通孔,改变电流的流过截面,在相同的台面管芯结构面积下,能够有效减弱高频趋肤效应导致趋肤深度而限制电流通过的影响,降低台面管芯因高频趋肤效应所引起的附加电阻,可提升高频段尤其是毫米波频段器件的输出功率;另外,在相同的台面管芯结构面积下,有效增大了管芯的散热热沉面积,利于功率器件的热传导,提升器件的可靠性。
附图说明
下面结合附图和实施例对本发明进一步说明:
图1是本发明的结构示意图;
图2是图1的俯视图;
图3是本发明制备方法步骤S1的示意图;
图4是本发明制备方法步骤S3的示意图;
图5是本发明制备方法步骤S4的示意图;
图6是本发明制备方法步骤S5的示意图;
图7是本发明制备方法步骤S6的腐蚀示意图;
图8是本发明制备方法腐蚀后得到的二极管台面管芯结构的示意图。
实施方式
结合图1与图2所示,本发明提供一种高频IMPATT二极管台面管芯结构,包括p+导电基底1,p+导电基底顶面设有台面管芯pn结2,所述台面管芯pn结2中央设有竖直的通孔3,使台面管芯形成环形圆台状;通孔3下部的孔径由上至下渐缩。
本发明还提供一种高频IMPATT二极管台面管芯结构的制备方法,包括以下步骤:
S1、结合图3所示,在n+硅晶圆片11上依次生长n型外延层12、p型外延层13及p+外延层14;
n型外延层12的厚度Wn由公式 (1)决定,
p型外延层13的厚度Wp由公式 (2)决定,
公式(1)、(2)中Vsn为n型外延层12饱和载流子漂移速率,Vsp为p型外延层13饱和载流子漂移速率,f0为器件工作频率;
S2、对n型外延层掺杂施主杂质n,p外延层掺杂受主杂质p;
本实施例n掺杂采用的掺杂杂质是P(磷),p掺杂采用的掺杂杂质是B(硼);
n掺杂的杂质浓度ND与p掺杂的杂质浓度NA由器件工作频率f0,Wn、Wp层载流子以饱和漂移速率运动的最大电场及IMPATT二极管器件偏置电流密度J0确定,对于高频大功率管芯,满足公式ND*Wn=NA*Wp (3);
S3、结合图4所示,在p+外延层14表面制备p+电极增强层15;p+外延层14与p+电极增强层15共同作为p+电极;
首先进行化学清洗,去除晶圆及p+外延层表面上的污物,再采用蒸发、溅射及电镀等半导体手段在p+外延层表面生长p+电极增强层,p+电极增强层可采用复合金属层,例如:Au/Cu/Au,保证p+电极具有极低的电阻和优良的热传导能力,提高器件电极的可靠性;
S4、结合图5所示,对n+硅晶圆片11进行减薄;
n+硅晶圆片由于具有极低电阻率,采用半导体化学腐蚀手段减薄至12μm左右,然后对减薄面进行抛光、清洗;
S5、结合图6所示,在n+硅晶圆片的减薄面制备n+电极增强层16;
采用蒸发、溅射及电镀等半导体手段在n+硅晶圆片的减薄面生长n+电极增强层,n+电极增强层可采用复合金属层,例如:Ti/Pd/Au,n+电极增强层与腐蚀剩下的硅晶圆片共同作为n+电极;
S6、结合图7与图8所示,按照台面管芯设计图形,通过光刻、腐蚀工艺,由n+电极增强层向p+外延层腐蚀,得到高频IMPATT二极管环形圆台状芯结构。
p+电极增强层15作为p+导电基底,p+外延层14、p型外延层13、n型外延层12、n+硅晶圆片11以及n+电极增强层16共同构成带有通孔3的台面管芯。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制;任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同替换、等效变化及修饰,均仍属于本发明技术方案保护的范围内。

Claims (2)

1.一种高频IMPATT二极管台面管芯结构的制备方法,IMPATT二极管台面管芯结构包括p+导电基底,p+导电基底顶面设有台面管芯pn结,所述台面管芯中央设有竖直的通孔,使台面管芯形成环形圆台状,其特征在于,包括以下步骤:
S1、在n+硅晶圆片上生长n型外延层、p型外延层及p+外延层;
S2、对n型外延层掺杂施主杂质,p外延层掺杂受主杂质;
S3、在p+外延层表面制备p+电极增强层;
S4、对n+硅晶圆片进行减薄;
S5、在n+硅晶圆片的减薄面制备n+电极增强层;
S6、按照台面管芯设计图形,通过光刻、腐蚀工艺,由n+电极增强层向p+外延层腐蚀,得到所述的高频IMPATT二极管台面管芯结构。
2.根据权利要求1所述的一种高频IMPATT二极管台面管芯结构,其特征在于,所述通孔下部的孔径由上至下渐缩。
CN202110041251.4A 2021-01-13 2021-01-13 一种高频impatt二极管台面管芯结构及制备方法 Active CN112635575B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110041251.4A CN112635575B (zh) 2021-01-13 2021-01-13 一种高频impatt二极管台面管芯结构及制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110041251.4A CN112635575B (zh) 2021-01-13 2021-01-13 一种高频impatt二极管台面管芯结构及制备方法

Publications (2)

Publication Number Publication Date
CN112635575A CN112635575A (zh) 2021-04-09
CN112635575B true CN112635575B (zh) 2023-08-22

Family

ID=75294067

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110041251.4A Active CN112635575B (zh) 2021-01-13 2021-01-13 一种高频impatt二极管台面管芯结构及制备方法

Country Status (1)

Country Link
CN (1) CN112635575B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1290926A (zh) * 1969-06-20 1972-09-27
JPS5779671A (en) * 1980-11-05 1982-05-18 Nec Corp Impatt diode
US5145809A (en) * 1990-12-04 1992-09-08 Millitech Corporation Fabrication of gunn diode semiconductor devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160225694A1 (en) * 2013-06-27 2016-08-04 Hans-Joachim Barth High conductivity high frequency via for electronic systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1290926A (zh) * 1969-06-20 1972-09-27
JPS5779671A (en) * 1980-11-05 1982-05-18 Nec Corp Impatt diode
US5145809A (en) * 1990-12-04 1992-09-08 Millitech Corporation Fabrication of gunn diode semiconductor devices

Also Published As

Publication number Publication date
CN112635575A (zh) 2021-04-09

Similar Documents

Publication Publication Date Title
US10243066B2 (en) Producing a semiconductor device by epitaxial growth
US8258032B2 (en) Power semiconductor devices and methods for manufacturing the same
US9070571B2 (en) Power switching module with reduced oscillation
CN111697077B (zh) 一种SiC沟槽栅功率MOSFET器件及其制备方法
CN104576720A (zh) 半导体器件和逆导igbt
Eisele Selective etching technology for 94 GHz GaAs IMPATT diodes on diamond heat sinks
CN113241377A (zh) 一种提升耐高温和抗辐照能力的igbt结构及其制备方法
CN107305909A (zh) 一种逆导型igbt背面结构及其制备方法
CN112635575B (zh) 一种高频impatt二极管台面管芯结构及制备方法
US20160322511A1 (en) Integration of the silicon impatt diode in an analog technology
CA1104265A (en) Heterojunction avalanche diode with a ternary alloy of gallium, indium and arsenic, and a binary alloy of indium and phosphorus
US20200395441A1 (en) Semiconductor structure and manufacturing method thereof
KR101448158B1 (ko) 저전압-고전류용 고성능 고속회복다이오드(hp-frd) 및 그 제조방법
CN103296072B (zh) 一种提高了BVcbo的双极型晶体管及其生产工艺
CN108520896A (zh) 一种耐压双极晶体管及其制作方法
CN111755502A (zh) 一种沟槽rc-igbt器件结构及其制作方法
CN115312591B (zh) 一种快恢复二极管及其制备方法
CN104603958A (zh) 平面雪崩光电二极管
CN113964197B (zh) 一种低泄漏电流的igbt器件及其制备方法
CN111863973B (zh) 肖特基二极管及其制备方法
CN113488540A (zh) 一种具有垂直场板保护的SiC基槽栅MOSFET结构
US9029250B2 (en) Method for producing semiconductor regions including impurities
CN111261725A (zh) 一种新型的超低压降肖特基二极管及其制备方法
CN218351475U (zh) 一种雪崩二极管结构
CN212365970U (zh) 一种沟槽rc-igbt器件结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant