CN112635552A - HEMT device with multi-gate field plate structure and preparation method thereof - Google Patents
HEMT device with multi-gate field plate structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 66
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
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- 230000005684 electric field Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention relates to a multi-gate field plate structure HEMT device and a preparation method thereof, wherein the HEMT device comprises a source electrode, a first passivation layer, a p-type GaN region and a drain electrode which are positioned on an AlGaN layer, the source electrode and the drain electrode are positioned at two ends of the first passivation layer, and the p-type GaN region is positioned in the first passivation layer and close to the source electrode; the second passivation layer is formed on the surface of the first passivation layer; the grid electrode is formed in the second passivation layer and is in contact with the upper surface of the p-type GaN region; the floating grid field plate is formed in a second passivation layer between the grid electrode and the drain electrode and positioned on the upper surface of the first passivation layer, the floating grid field plate is close to the grid electrode, and the source field plate connected with the source electrode extends from the source grid region to a part of the grid drain region; and a drain field plate connected to the drain electrode and located on the upper surface of the second passivation layer. The depletion region is effectively enlarged by arranging the distribution mode between the multi-grid field plate structure and the source/drain field plate, the electric field distribution between the grid and the grid is widened, and the breakdown voltage is improved.
Description
Technical Field
The invention relates to the field of high electron mobility transistors, in particular to a HEMT device with a multi-gate field plate structure and a preparation method thereof.
Background
A High Electron Mobility Transistor (HEMT) is a field effect transistor, which is a heterojunction formed of two materials having different band gaps to provide a channel for a carrier, and can operate at an extremely high frequency, so that it has wide applications in communication, satellite, radar, and the like. The gallium nitride high electron mobility transistor has the characteristics of high switching speed and low switching loss, and has wide application prospect in the fields of microwave power amplification and power conversion.
The electric field distribution in a HEMT has a decisive influence on the device performance and reliability. How to optimize the electric field distribution in the HEMT device, improve the breakdown voltage of the HEMT and improve the device performance on the premise of not increasing the size of the device is one of the problems to be solved urgently.
Disclosure of Invention
Aiming at the technical problems in the prior art, the primary object of the invention is to provide a multi-gate field plate structure HEMT device and a preparation method thereof, wherein the HEMT device provides a new charge balance mode by setting a distribution mode between the multi-gate field plate structure and a source/drain field plate, effectively enlarges a depletion region, replaces a single-peak electric field with a multi-peak electric field, makes the electric field distribution more uniform, reduces leakage current, and can effectively adjust the electric potential distribution, thereby widening the electric field distribution between a gate and the gate and improving the breakdown voltage; meanwhile, on the premise of not increasing the size of the device, the lower threshold voltage of the HEMT device is kept, and the on-resistance of the device is kept unchanged.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-gate field plate structure HEMT device, comprising: the buffer layer, the GaN channel layer and the AlGaN layer are sequentially stacked on the Si substrate;
the source electrode and the drain electrode are positioned at two ends of the first passivation layer, and the p-type GaN region is positioned in the first passivation layer and close to the source electrode;
the second passivation layer is formed on the surface of the first passivation layer;
a gate formed in the second passivation layer in contact with an upper surface of the p-type GaN region;
the floating gate field plate is formed in a second passivation layer between the grid electrode and the drain electrode and is positioned on the upper surface of the first passivation layer, the floating gate field plate is close to the grid electrode, n floating gate field plates are arranged, and n is larger than or equal to 1;
the source field plate is connected with the source electrode, is positioned on the upper surface of the second passivation layer and extends from the source gate region to part of the gate drain region;
and the drain field plate is connected with the drain electrode and is positioned on the upper surface of the second passivation layer.
Further, the number n of the floating gate field plates is preferably 3 or 4, the floating gate field plates are arranged in the direction close to the gate side and towards the drain side, and the vertical distance between the source/drain field plates and the floating gate field plates is kept uniform and unchanged.
Furthermore, the floating gate field plate, the drain field plate and the source field plate are the same in thickness.
Furthermore, the floating gate field plates are the same in size, and the distances between adjacent floating gate field plates are equal and independent of each other.
Further, the length of the floating gate field plate is in a ratio of 1: 3: 5: 7 …, and are independent of each other.
Further, the length of the floating gate field plate is in a ratio of 1: 2: 4: the equivalence ratio of 8 … varies and is independent of each other.
Further, the vertical distance between the source field plate and the gate field plate is preferably 0.1 μm; the vertical distance between the drain field plate and the grid field plate is preferably 0.1 μm, the length of the floating grid field plate is preferably 0.2 μm, the space between the floating grid field plates is preferably 0.2 μm, the space between the floating grid field plate close to the grid and the grid is preferably 0.2 μm, and the thickness of the floating grid field plate is preferably 0.1 μm.
Further, the source/drain electrode is preferably a Ti/Al/Ni/Au metal composite layer, and the grid electrode is preferably a Ni/Au metal composite layer.
Further, the material of the floating gate field plate is not identical to the gate material.
The invention also provides a preparation method of the HEMT device with the multi-gate field plate structure, which comprises the following steps:
sequentially epitaxially growing a buffer layer, a GaN channel layer and an AlGaN layer on a substrate;
depositing a mask layer on the AlGaN layer, and etching the mask layer to form a growth window;
epitaxially growing a p-type GaN layer in the growth window region, and removing the mask layer to form a p-type GaN region;
depositing a first passivation layer, etching two ends of the first passivation layer to form a source/drain region, and depositing a metal layer to form a source/drain electrode;
etching the first passivation layer of the p-type GaN region to form a gate window, and depositing a metal layer to form a gate electrode;
depositing a second passivation layer covering the source/drain electrode and the gate electrode;
etching a second passivation layer between the grid and the drain to form a floating grid field plate window, and depositing a metal layer to form a floating grid field plate window;
and thickening the second passivation layer, and respectively preparing a source field plate connected to the source electrode and a drain field plate connected to the drain electrode on the surface of the second passivation layer, wherein the source field plate extends to a part of the gate drain region.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a HEMT device of a multi-gate field plate structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art without any creative effort belong to the protection scope of the present invention. "upper surface" in the present invention means the second surface of the layer concerned in the direction pointing along the back surface of the substrate towards the growth surface of the substrate material; the "lower surface", i.e. in the above-mentioned direction, relates to the first surface of the layer.
The present invention will be described in further detail below. Referring to fig. 1, the embodiment provides a HEMT device with a multi-gate field plate structure, which includes a Si substrate 1, an AlN buffer layer 2, an AlGaN buffer layer 3 with gradually changed Al composition, a GaN channel layer 4, and an AlGaN layer 5, which are sequentially stacked on the Si substrate 1. Wherein the Si substrate 1 and the AlN buffer layer 2 are also provided with a thin layer of Al. In a preferred embodiment, the Al composition of the AlGaN buffer layer 3 with a graded Al composition is 0.5, 0.45, 0.4, and 0.25, respectively.
The p-type GaN region 6, the source electrode 7, the drain electrode 8 and the first passivation layer 101 are disposed on the surface of the AlGaN layer 5, wherein the source electrode 7 and the drain electrode 8 are disposed at two side ends of the first passivation layer 101, and the p-type GaN region 6 is disposed in the first passivation layer 101 near the source electrode 7. The material of the first passivation layer 101 is preferably silicon dioxide. The source electrode 7 and the drain electrode 8 are preferably Ti/Al/Ni/Au complex metal layers.
The second passivation layer 102 covers the surface of the first passivation layer 101, wherein the gate 9 is disposed on the upper surface of the p-type GaN region 6, directly contacts the upper surface of the p-type GaN region 6, and is formed in the second passivation layer 102. The floating gate field plates 13 are positioned in the second passivation layer 102 and formed in the region between the gate 9 and the drain electrode 8, wherein the floating gate field plates 13 are arranged on the surface of the first passivation layer 101, and n floating gate field plates are provided, and n is larger than or equal to 1.
The source field plate 11 is connected to the source electrode 7 and is located on the surface of the second passivation layer 102. The source field plate 11 extends from the region between the source electrode 7 and the gate electrode 9 to a portion of the region between the gate electrode 9 and the drain electrode 8. A drain field plate 12 is connected to the drain electrode 8 at the surface of the second passivation layer 102. The drain field plate 12 extends to a portion of the drain 8 and gate 9 regions.
The floating gate field plate 13, the drain field plate 12 and the source field plate 11 have the same thickness. In a preferred embodiment, the number of floating gate field plates, preferably n-3 or 4, is independent of each other. Optionally, the floating gate field plates 13 have the same size, and the spacing between two adjacent floating gate field plates is equal. Optionally, the length of the floating gate field plate along the direction from the gate to the drain is in a ratio of 1: 3: 5: 7 …, and the spacing between two adjacent floating gate field plates is equal. In another preferred embodiment, the length of the floating gate field plate along the direction from the gate to the drain is in the ratio of 1: 2: 4: an equal ratio of 8 ….
The floating grid field plate is close to the grid and located in the grid drain region, the source field plate extends to a part of the grid drain region from the source grid region, the vertical distance between the source/drain field plate and the floating grid field plate is kept uniform and unchanged, and the grid field plates are arranged from the side close to the grid to the drain direction. Through the arrangement of the multi-grid field plate structure and the position relation of the source/drain field plate, a new charge balance mode is realized, the depletion region is effectively enlarged, the electric field distribution is more uniform, the leakage current is reduced, and the setting mode can keep smaller threshold voltage on the premise of not increasing the size of a device and keeps the on-resistance unchanged.
In a preferred embodiment, the vertical distance between the source field plate and the gate field plate is preferably 0.1 μm, which is to say the thickness of the passivation layer between the source or drain field plate and the gate field plate in the vertical direction. The vertical distance between the drain field plate and the gate field plate is preferably 0.1 μm, the length of the floating gate field plate is preferably 0.2 μm, the spacing between the floating gate field plates is preferably 0.2 μm, the spacing between the floating gate field plate close to the gate 9 and the gate 9 is preferably 0.2 μm, and the thickness of the floating gate field plate is preferably 0.1 μm.
The gate 9 is preferably a Ni/Au metal composite layer and in preferred embodiments the material of the floating gate field plate is not exactly the same as the gate material, e.g., the floating gate field plate is preferably a Ti/Au metal composite layer.
Based on the HEMT device with the multi-gate field plate structure, the invention also provides a preparation method of the HEMT device with the multi-gate field plate structure, which comprises the following steps:
and sequentially epitaxially growing a buffer layer, a GaN channel layer and an AlGaN layer on the substrate. Specifically, a thin layer of Al is grown on a Si (111) substrate by metal organic chemical vapor deposition. First, the growth temperature of the chamber was adjusted to 940 ℃ in H2Heating for 10min under the atmosphere to remove the oxide film on the surface of the substrate, continuously adjusting the growth temperature to 1060 ℃, introducing TMA, and reacting for 12 s.
Then, an AlN buffer layer was grown on the Al layer while adjusting the growth temperature to 1070 ℃. TMA (trimethylaluminum) is continuously introduced during the growth process, NH3By pulsed introduction of NH during the time T13NH during time T23Not into the reaction chamber. The growth conditions were TMA flow of 13sccm, NH3The flow rate was 800sccm, the time T1 was 12s, and the time T2 was 6 s. The AlN buffer layer was grown to a thickness of 160 nm.
Continuously growing Al with gradually changed Al components on the AlN buffer layerxGa1-xAnd an N buffer layer. The flow rate of TEGa was kept at 40sccm, the flow rate of TMA was gradually decreased from the initial growth temperature of 1060 ℃ to a reduction of 20 ℃, the Al components were 0.5, 0.45, 0.4, and 0.25, respectively, and the growth time of each component was 360 nm.
Followed byIn the gradual change of AlxGa1-xGrowing a GaN channel layer on the N buffer layer, setting the growth temperature to 920 ℃, the pressure to 40Torr and the H2Flow rate 500sccm, NH3The flow rate of the gallium source is 5000sccm, the flow rate of the gallium source is 220sccm, and the growth thickness of the gallium source is 35 nm. And then growing a layer of AlGaN on the GaN buffer layer. The growth temperature is 920 ℃, the pressure is 40Torr, and the growth temperature is H2Flow rate 500sccm, NH3The flow rate of the silicon source is 5000sccm, the flow rate of the aluminum source is 10sccm, the flow rate of the gallium source is 40sccm, and the growth thickness of the silicon source is 15 nm.
Subsequently, a Plasma Enhanced Chemical Vapor Deposition (PECVD) is selected and N is set2O flow rate of 800sccm, SiH4The flow rate is 150sccm, the pressure is 1000mT, the temperature is 250 ℃, and the power is 25W. Deposition of 0.1 μm SiO on AlGaN layer2And a passivation layer. Etching the SiO by wet method2And a passivation layer forming a p-GaN region window with a length of 0.1 μm.
Continuing to select MOCVD process to grow p-GaN layer to fill the window region and remove SiO2The passivation layer forms a p-type GaN region.
A first passivation layer is deposited, preferably silicon dioxide, deposited to a thickness of 0.1 μm. And etching by a wet method to form a source/drain region at two ends of the first passivation layer, and depositing a Ti/Al/Ni/Au composite metal layer by an electron beam evaporation method to manufacture a source electrode and a drain electrode. Wherein the thickness of the Ti layer is 30nm, the thickness of Al is 180nm, the thickness of Ni is 40nm, and the thickness of Au is 60 nm. Vacuum degree of electron beam evaporation is less than 2.0 × 10-6Pa, power of 200W, and evaporation rate of not more than 3 angstroms/second. And then, placing the metal epitaxial wafer in an acetone solution for soaking for 20min, then carrying out ultrasonic washing, washing with ultrapure water and drying with ammonia gas, stripping the metal except the source electrode and the drain electrode, and then placing the epitaxial wafer in an ammonia gas atmosphere at 850 ℃ for carrying out ohmic contact annealing for 30s to form a source-drain contact electrode.
Etching the first passivation layer of the p-type GaN region to form a grid window, and depositing Ni/Au two layers of metal by using an electron beam evaporation method, wherein the thickness of Ni is 30nm, and the thickness of Au is 200 nm; and then, soaking the epitaxial wafer in stripping liquid to strip metal, washing with ultrapure water for 2min, and drying with ammonia gas to obtain the gate electrode.
And depositing a second passivation layer by PECVD (plasma enhanced chemical vapor deposition), wherein the second passivation layer preferably is silicon dioxide and has the thickness of 0.05 mu m, and covers the source/drain electrode and the gate electrode. The process conditions for depositing the passivation layer are as follows: n is a radical of2O flow rate of 800sccm, SiH4The flow rate is 150sccm, the pressure is 1000mT, the temperature is 250 ℃, and the power is 25W.
In SiO2And manufacturing a mask on the passivation layer, etching a second passivation layer between the grid electrode and the drain electrode to form a floating grid field plate window, wherein the distance between the floating grid field plate window and the grid electrode is 0.2 microns, the Ti/Au metal combination with the deposition thickness of 0.1 micron is deposited to fill the floating grid field plate window, the length of the floating grid field plate is 0.2 microns, the number of the floating grid field plates is preferably 4, and the distances between the floating grid field plates are equal and are all 0.2 microns.
And thickening the second passivation layer, and respectively preparing a source field plate connected to the source electrode and a drain field plate connected to the drain electrode on the surface of the second passivation layer, wherein the source field plate extends to a part of the gate drain region from the source electrode side. In this example, the source field plate has a thickness of 0.1 microns and a length of 2.2 microns, and the drain field plate has a thickness of 0.1 microns and a length of 1.6 microns.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (10)
1. Many grid field plate structure HEMT device, its characterized in that includes: the buffer layer, the GaN channel layer and the AlGaN layer are sequentially stacked on the Si substrate;
the source electrode and the drain electrode are positioned at two ends of the first passivation layer, and the p-type GaN region is positioned in the first passivation layer and close to the source electrode;
the second passivation layer is formed on the surface of the first passivation layer;
a gate formed in the second passivation layer in contact with an upper surface of the p-type GaN region;
the floating gate field plate is formed in a second passivation layer between the grid electrode and the drain electrode and is positioned on the upper surface of the first passivation layer, the floating gate field plate is close to the grid electrode, n floating gate field plates are arranged, and n is larger than or equal to 1;
the source field plate is connected with the source electrode, is positioned on the upper surface of the second passivation layer and extends from the source gate region to part of the gate drain region;
and the drain field plate is connected with the drain electrode and is positioned on the upper surface of the second passivation layer.
2. The HEMT device of claim 1, wherein said number n of said floating gate field plates is preferably 3 or 4, said floating gate field plates are arranged in a direction close to said gate side toward said drain side, and the vertical distance between said source/drain field plates and said floating gate field plates is kept uniform.
3. The HEMT device of claim 2, wherein said floating gate field plate, drain field plate and source field plate are the same thickness.
4. The HEMT device of claim 2 or 3, wherein said floating gate field plates are of the same size and are spaced apart equally from each other independently.
5. The HEMT device of claim 2 or 3, wherein said floating gate field plate has a length in a direction from the gate to the drain in a ratio of 1: 3: 5: 7 …, and are independent of each other.
6. The HEMT device of claim 2 or 3, wherein said floating gate field plate has a length in a direction from the gate to the drain in a ratio of 1: 2: 4: the equivalence ratio of 8 … varies and is independent of each other.
7. The HEMT device of claim 4, wherein said source field plate is preferably at a vertical distance of 0.1 μm from the gate field plate; the vertical distance between the drain field plate and the grid field plate is preferably 0.1 μm, the length of the floating grid field plate is preferably 0.2 μm, the space between the floating grid field plates is preferably 0.2 μm, the space between the floating grid field plate close to the grid and the grid is preferably 0.2 μm, and the thickness of the floating grid field plate is preferably 0.1 μm.
8. The HEMT device of claim 4, wherein the source/drain is preferably a Ti/Al/Ni/Au metal composite layer and the gate is preferably a Ni/Au metal composite layer.
9. The HEMT device of claim 4, wherein said floating gate field plate is not completely the same material as said gate material.
10. The preparation method of the HEMT device with the multi-gate field plate structure is characterized by comprising the following steps of:
sequentially epitaxially growing a buffer layer, a GaN channel layer and an AlGaN layer on a substrate;
depositing a mask layer on the AlGaN layer, and etching the mask layer to form a growth window;
epitaxially growing a p-type GaN layer in the growth window region, and removing the mask layer to form a p-type GaN region;
depositing a first passivation layer, etching two ends of the first passivation layer to form a source/drain region, and depositing a metal layer to form a source/drain electrode;
etching the first passivation layer of the p-type GaN region to form a gate window, and depositing a metal layer to form a gate electrode;
depositing a second passivation layer covering the source/drain electrode and the gate electrode;
etching a second passivation layer between the grid and the drain to form a floating grid field plate window, and depositing a metal layer to form a floating grid field plate window;
and thickening the second passivation layer, and respectively preparing a source field plate connected to the source electrode and a drain field plate connected to the drain electrode on the surface of the second passivation layer, wherein the source field plate extends to a part of the gate drain region.
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