CN112631236A - Performance test system and method of electronic speed regulator - Google Patents
Performance test system and method of electronic speed regulator Download PDFInfo
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- CN112631236A CN112631236A CN202011349352.XA CN202011349352A CN112631236A CN 112631236 A CN112631236 A CN 112631236A CN 202011349352 A CN202011349352 A CN 202011349352A CN 112631236 A CN112631236 A CN 112631236A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
Abstract
The invention relates to a performance test system and a method of an electronic speed regulator, wherein the performance test system comprises: a logic quantity verification card connected with the electronic speed regulator; the analog quantity verification card is connected with the electronic speed regulator; a CPU simulator connected with the electronic speed regulator and used for simulating and replacing a CPU of the electronic speed regulator; the upper computer is connected with the logic quantity verification card, the analog quantity verification card, the CPU simulator and the electronic speed regulator, and is used for sending a test instruction to one of the logic quantity verification card, the analog quantity verification card and the CPU simulator, acquiring an output signal from one of the logic quantity verification card, the analog quantity verification card and the CPU simulator, and analyzing the output signal to acquire a test result. By implementing the technical scheme of the invention, the performance test of the electronic speed regulator can be realized, so that the hidden danger of the emergency diesel engine system operation is eliminated and the unavailable event of the emergency diesel engine is avoided.
Description
Technical Field
The invention relates to the field of nuclear power, in particular to a performance test system and method of an electronic speed regulator.
Background
At present, an electronic speed regulator used by a large emergency diesel engine control system of a nuclear power plant in China is produced abroad, and the electronic speed regulator is software and hardware integrated highly-integrated control equipment and is used for controlling the rotating speed and the power of a large diesel engine. In practical applications, there are two maintenance strategies for the governor: one is to prevent the speed regulator from being replaced in advance due to faults, which causes the speed regulator to be in good state when being replaced, and the speed regulator cannot be used as the best as possible; one is that the governor fails and is replaced during operation, which can cause an emergency diesel engine unavailability event that the nuclear power plant does not allow. Both of the above cases lack the diagnosis and performance evaluation of the state of the transmission, and do not take measures against the actual condition of the transmission.
Disclosure of Invention
The invention aims to solve the technical problem of providing a performance test system and method of an electronic speed regulator aiming at the defect that the prior art cannot realize state diagnosis and performance evaluation of the electronic speed regulator.
The technical scheme adopted by the invention for solving the technical problems is as follows: a performance testing system of an electronic governor is constructed, comprising:
a logic quantity verification card connected with the electronic speed regulator;
the analog quantity verification card is connected with the electronic speed regulator;
a CPU simulator connected with the electronic speed regulator and used for simulating and replacing a CPU of the electronic speed regulator;
the upper computer is connected with the logic quantity verification card, the analog quantity verification card, the CPU simulator and the electronic speed regulator, and is used for sending a test instruction to one of the logic quantity verification card, the analog quantity verification card and the CPU simulator, acquiring an output signal from one of the logic quantity verification card, the analog quantity verification card and the CPU simulator, and analyzing the output signal to acquire a test result.
Preferably, when a logic quantity input channel performance test of the electronic speed regulator is carried out,
the upper computer is used for sending a power supply signal generation instruction to the logic quantity verification card, receiving a power supply output signal from the CPU simulator, and acquiring a high level threshold value and a low level threshold value in combination with a generation time sequence of the power supply input signal;
the logic quantity verification card is used for generating an instruction according to the power supply signal, generating a corresponding power supply input signal and outputting the corresponding power supply input signal to a logic quantity input interface of the electronic speed regulator;
and the CPU simulator is used for collecting corresponding interface data from the electronic speed regulator, judging high and low levels and recording time sequence of the interface data so as to obtain a power output signal and sending the power output signal to the upper computer.
Preferably, when a logic quantity output channel performance test of the electronic speed regulator is carried out,
the upper computer is used for sending a logic quantity output performance test instruction to the CPU simulator and receiving and storing the loading capacity value of the corresponding channel from the logic quantity verification card;
the CPU simulator is used for generating a corresponding logic quantity signal according to the logic quantity output performance test instruction and outputting the corresponding logic quantity signal to the electronic speed regulator;
and the logic quantity verification card is used for receiving a functional logic signal from a logic quantity output interface of the electronic speed regulator and analyzing the functional logic signal to acquire the loading capacity value of the corresponding channel.
Preferably, when the performance test of the frequency signal input channel of the electronic speed regulator is carried out,
the upper computer is used for sending a frequency signal generation instruction to the logic quantity verification card, receiving a frequency output signal from the CPU simulator, and acquiring a frequency response threshold and an amplitude minimum response threshold of a frequency signal input channel in combination with a generation time sequence of the frequency input signal;
the logic quantity verification card is used for generating an instruction according to the frequency signal, generating a corresponding frequency input signal and outputting the frequency input signal to the frequency input port of the electronic speed regulator;
the CPU simulator is used for collecting corresponding interface data from the electronic speed regulator, carrying out frequency/amplitude/waveform analysis and time sequence recording on the interface data so as to obtain a frequency output signal, and sending the frequency output signal to the upper computer.
Preferably, when the performance test of the analog quantity output channel of the electronic speed regulator is carried out,
the upper computer is used for sending an analog quantity output set value instruction to the CPU simulator, receiving and storing a loading capacity value and a functional simulation signal of a corresponding channel from the analog quantity verification card, and generating a report according to the functional simulation signal and the analog quantity output set value instruction;
the CPU simulator is used for generating a corresponding analog quantity signal according to the analog quantity output set value instruction and outputting the analog quantity signal to the electronic speed regulator;
the analog quantity verification card is used for collecting corresponding functional analog signals from an analog quantity output interface of the electronic speed regulator, analyzing the functional analog signals to obtain the loading capacity values of corresponding channels, and respectively uploading the loading capacity values of the corresponding channels and the collected corresponding functional analog signals to the upper computer.
Preferably, the functional analog signal comprises: the system comprises an accelerator position signal, a TCA Speed rotating Speed signal, a diesel engine rotating Speed signal, a TCB Speed rotating Speed signal, a load balancing signal, an internal rotating Speed set value signal and an accelerator output signal.
Preferably, when performing a chip function test of the electronic governor,
the upper computer is used for sending a parameter configuration instruction or a state reading instruction to the CPU simulator and determining the chip function of the electronic speed regulator according to the returned result of the CPU simulator;
and the CPU simulator is used for configuring the parameters of the electronic speed regulator or reading the state of the electronic speed regulator through a PLCC packaging tool interface of the electronic speed regulator according to the received parameter configuration command or state reading command.
Preferably, the electronic governor comprises a PLCC socket connected to the PLCC package tooling interface, and an on-board ROM, an on-board RAM, a watchdog, and a driver respectively connected to the PLCC socket, and further,
configuring a parameter of the electronic governor or reading a status of the electronic governor, comprising:
carrying out full address access verification on the onboard ROM, and recording the erasing speed;
testing the function of the onboard RAM by performing high-capacity data operation and memory exchange;
testing the function of the watchdog by outputting pulse signals with different frequencies and collecting reset signals of the watchdog;
and testing the function of the driver by sending a control instruction to the driver and collecting an output signal of the driver.
The invention also provides a performance test method of the electronic speed regulator, which comprises the following steps:
the upper computer sends a test instruction to one of the logic quantity verification card, the analog quantity verification card and the CPU simulator;
the upper computer collects an output signal from one of the logic quantity verification card, the analog quantity verification card and the CPU simulator;
and the upper computer analyzes the output signal to obtain a test result.
According to the technical scheme provided by the invention, the performance test and diagnosis of the electronic speed regulator can be realized by combining the logic quantity verification card, the analog quantity verification card and the CPU simulator with the upper computer, so that a worker can better know the initial state of newly purchased electronic speed regulator spare parts and the state of the electronic speed regulator in field use, and the hidden danger of the operation of an emergency diesel engine system is eliminated and the unavailable event of the emergency diesel engine is avoided.
Drawings
In order to illustrate the embodiments of the invention more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort. In the drawings:
FIG. 1 is a logical block diagram of the electronic governor of the present invention;
FIG. 2 is a logic structure diagram of a first embodiment of a performance testing system of the electronic governor of the present invention;
FIG. 3 is a logic structure diagram of a second embodiment of the performance testing system of the electronic governor of the present invention;
FIG. 4 is a logic structure diagram of a third embodiment of a performance testing system of the electronic governor of the present invention;
FIG. 5 is a logical block diagram of a fourth embodiment of a performance testing system for an electronic governor of the present invention;
FIG. 6 is a logic structure diagram of a fifth embodiment of the performance testing system of the electronic governor of the present invention;
FIG. 7 is a logical block diagram of a sixth embodiment of a performance testing system for an electronic governor of the present invention;
fig. 8 is a flow chart of a first embodiment of the performance testing method of the electronic speed regulator.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First, the electronic governor is a highly integrated control device, and functions to control the rotational speed and power of a large diesel engine. With reference to the internal logic structure of the electronic governor shown in fig. 1, the electronic governor includes a CPU11, and a logic input interface 12, an analog input interface 13, a rotational speed input interface 14, a logic output interface 15, an analog output interface 16, an accelerator opening output interface 17, a power module 18, and a communication module 19, which are respectively connected to a CPU 11.
According to the structure of the electronic speed regulator, the invention constructs a performance test system of the electronic speed regulator so as to carry out performance test and diagnostic analysis on the channel level and the component level of the electronic speed regulator 10. As shown in fig. 2, the performance test system of this embodiment includes a logic quantity verification card 20, an analog quantity verification card 30, a CPU simulator 40, and an upper computer 50, which are respectively connected to the electronic governor 10, wherein the CPU simulator 40 is used to simulate and replace the CPU of the electronic governor 10. In addition, the logic quantity verification card 20, the analog quantity verification card 30, and the CPU simulator 40 are also connected to the upper computer 50, respectively. The upper computer 50 is used for sending a test instruction to one of the logic quantity verification card 20, the analog quantity verification card 30 and the CPU simulator 40, acquiring an output signal from one of the logic quantity verification card 20, the analog quantity verification card 30 and the CPU simulator 40, and analyzing the output signal to obtain a test result.
Through the performance test system of this embodiment, performance test and diagnostic analysis of the electronic governor 10 can be realized, and the content of the performance test includes a logic quantity input channel performance test, a logic quantity output channel performance test, a frequency signal input channel performance test, an analog quantity output channel performance test, and a function test of each chip, for example, including: channel accuracy, threshold, critical chip performance. Therefore, the staff can better know the initial state of newly purchased electronic speed regulator spare parts and the state of the electronic speed regulator in field use, thereby eliminating the hidden trouble of the operation of an emergency diesel engine system and avoiding the occurrence of an unavailable event of the emergency diesel engine.
In this embodiment, it should be noted that, regarding the CPU simulator 40, it can be known from the schematic diagram and the structural diagram of the electronic governor that the currently used electronic governor is designed based on 87C196KD and is packaged by a PLCC, so that the CPU simulator 40 can select a corresponding substitute chip or substitute module, is designed by using a PLCC package identical to 87C196KD, and is configured with 68PIN sockets on the module, and the CPU PINs of the electronic governor are connected to the main control module of the CPU simulator 40. A CPU simulator is developed according to the definition of each pin of the original CPU, the requirement of electrical parameters and functions, and the complete replacement of the original CPU of the electronic speed regulator is realized.
The diagnostic flow of the performance testing system of the present invention is described below with reference to fig. 1 and 2: firstly, the CPU simulator 40 is used for replacing the CPU of the electronic speed regulator 10, then a reading instruction is sent to the CPU simulator 40 through the upper computer 50, the EEPROM information, the EPLD information, the address distribution information of each port and the state of the functional module of the electronic speed regulator are read, and the information is recorded and stored. Then, signals are respectively input from the logic quantity input interface 12 and the analog quantity input interface 13 of the electronic speed regulator 10, the CPU simulator 40 is used for collecting and uploading the signals in the corresponding channels, and the upper computer 50 is used for analyzing and checking the data to realize the performance detection of the input channels. In addition, the upper computer 50 can also send a simulation operation diagnosis instruction, the CPU simulator 40 starts to send logic or simulation signals to each output channel, and then the logic quantity verification card 20 and the analog quantity verification card 30 collect signals from the corresponding output interfaces of the electronic speed regulator 10, and upload the data to the upper computer 50 for comparison and correction. Then, the upper computer 50 sends a loading capacity test instruction, tests the loading capacity of the corresponding output channel of the electronic speed regulator through the logic quantity verification card 20 and the analog quantity verification card 30, and summarizes and uploads the test data to the upper computer 50. The upper computer 50 generates and stores the analysis result into a document record, so that the fault library can be completed and the fault record can be searched and consulted conveniently.
Fig. 3 is a logic structure diagram of a second embodiment of the performance testing system of the electronic governor of the present invention, and the performance testing system of this embodiment is used to perform a performance test of the logic quantity input channel of the electronic governor. In this embodiment, the upper computer 50 is configured to send a power signal generation instruction to the logic quantity verification card 20, receive a power output signal from the CPU emulator 40, and obtain a high level threshold and a low level threshold in combination with a generation timing sequence of a power input signal; the logic quantity verification card 20 is used for generating a corresponding power supply input signal according to the power supply signal generation instruction and outputting the corresponding power supply input signal to the logic quantity input interface 12 of the electronic speed regulator 10; the CPU simulator 40 is configured to collect corresponding interface data from the PLCC packaging tool interface 111 of the electronic governor 10, perform high-low level determination and time-series recording on the interface data, obtain a power output signal, and send the power output signal to the upper computer 50.
In this embodiment, the logic quantity input channel performance test is implemented by the logic quantity verification card 20 and the CPU simulator 40 in cooperation with the electronic governor 10. Specifically, the upper computer 50 sends a power signal generation instruction, for example, a step voltage/step voltage generation instruction to the main control unit MCU21 of the logic quantity verification card 20. In the logic amount verification card 20, the MCU21 interprets the received instruction and outputs logic amount data to the DA conversion unit 22, and the DA conversion unit 22 may be a multi-channel DA conversion circuit. The DA conversion unit 22 DA-converts the input logic amount data and then outputs to the power supply signal generation unit 23. The power signal generating unit 23 generates a plurality of paths of step voltages/step voltages, outputs the step voltages to the logic input interface 12 of the electronic speed regulator 10, and transmits voltage signals to the PLCC packaging tool interface 111 after the logic input interface 12 of the electronic speed regulator 10 is processed by an internal circuit of the electronic speed regulator. Then, the CPU simulator 40 collects data input by the PLCC tool package interface 111 through the logic input interface 41 thereof, and the first determination unit 42 performs analysis high and low level determination and timing recording. Finally, the CPU simulator 40 summarizes the level data and uploads the level data to the software of the upper computer 50, and the upper computer 50 judges the high and low level thresholds and the time sequence in combination with the generation time sequence of the multi-channel step voltage and the step voltage, and stores the recorded data.
Fig. 4 is a logic structure diagram of a third embodiment of the performance testing system of the electronic governor of the present invention, and the performance testing system of the embodiment is used for performing a performance test of a logic quantity output channel of the electronic governor. In this embodiment, the upper computer 50 is configured to send a logic quantity output performance test instruction to the CPU simulator 40, and receive and store a loading capacity value of a corresponding channel from the logic quantity verification card 20; the CPU simulator 40 is used for generating a corresponding logic quantity signal according to the logic quantity output performance test instruction and outputting the corresponding logic quantity signal to the electronic speed regulator 10; the logic quantity verification card 20 is used for receiving the functional logic signals from the logic quantity output interface 15 of the electronic speed regulator 10 and analyzing the functional logic signals to obtain the loading capacity value of the corresponding channel.
In this embodiment, the logic quantity output channel performance test of the electronic governor is realized by the logic quantity verification card 20 and the CPU simulator 40 in cooperation with the electronic governor 10. Specifically, the upper computer 50 sends a logic quantity output performance test instruction to the CPU simulator 40, the CPU simulator 40 analyzes the instruction and generates a corresponding logic quantity signal, the signal is connected to the PLCC package tool interface of the electronic speed regulator 10 through a cable to enter the main board of the electronic speed regulator 10, and then each channel circuit of the main board of the electronic speed regulator processes the entered logic quantity signal and outputs the processed logic quantity signal to the logic quantity verification card 20 from the logic quantity output interface 15. In the logic quantity verification card 20, a signal enters a logic quantity acquisition unit 25 through a logic quantity load adjusting unit 24 for data analysis, wherein the logic quantity load adjusting unit 24 can be a multi-path load adjusting circuit, and the logic quantity acquisition unit 25 can be a multi-path current and voltage sampling circuit. Finally, the logic quantity verification card outputs the loading capacity value of each channel, and uploads the loading capacity value to the upper computer 50 for data storage.
Fig. 5 is a logical structure diagram of a fourth embodiment of the performance testing system of the electronic governor according to the present invention, and the performance testing system of this embodiment is used to perform a performance test of the frequency signal input channel of the electronic governor. In this embodiment, the upper computer 50 is configured to send a frequency signal generation instruction to the logic quantity verification card 20, receive a frequency output signal from the CPU simulator 40, and obtain a frequency response threshold and an amplitude minimum response threshold of a frequency signal input channel in combination with a generation timing sequence of a frequency input signal; the logic quantity verification card 20 is used for generating a corresponding frequency input signal according to the frequency signal generation instruction and outputting the frequency input signal to the frequency (rotating speed) input port 14 of the electronic speed regulator 10; the CPU simulator 40 is configured to collect corresponding interface data from the electronic governor 10, perform frequency/amplitude/waveform analysis and time-series recording on the interface data, obtain a frequency output signal, and send the frequency output signal to an upper computer.
In this embodiment, the performance test of the frequency signal input channel of the electronic governor is implemented by the logic quantity verification card 20 and the CPU simulator 40 in cooperation with the electronic governor 10. Specifically, the upper computer 50 sends a frequency signal generation instruction, for example, a sine wave/square wave generation instruction, to the main control unit MCU21 of the logic quantity verification card 20. In the logic amount verification card 20, the MCU21 parses the received instruction and outputs logic amount data to the DA conversion unit 22, and the DA conversion unit 22 may be a multi-channel DA conversion circuit. The DA conversion unit 22 performs DA conversion on the input logic quantity data and then outputs to the frequency signal generation unit 26, and the frequency signal generation unit 26 generates a sine wave/square wave signal with adjustable amplitude/frequency and outputs to the frequency input interface 14 of the electronic governor 10. The internal circuit of the electronic governor 10 processes the input signal and transmits the processed signal to the PLCC package tool interface 111 for output. The CPU simulator 40 collects the interface data of the PLCC package tooling interface 111 through the frequency collection interface 43 thereof, and then performs frequency/amplitude/waveform analysis judgment and timing recording on the interface data by the second judgment unit 44. Finally, the CPU simulator 40 summarizes the data and transmits the summarized data to the software of the upper computer 50, and the upper computer 50 determines the frequency response threshold, the minimum amplitude threshold, and the time sequence in combination with the generation time sequence of the amplitude/frequency-adjustable sine wave/square wave signal, and stores the recorded data.
Fig. 6 is a logic structure diagram of a fifth embodiment of the performance testing system of the electronic speed regulator according to the present invention, and the performance testing system of the embodiment is used for performing the performance test of the analog output channel of the electronic speed regulator. In this embodiment, the upper computer 50 is configured to send an analog output set value instruction to the CPU simulator 40, receive and store a loading capability value and a functional analog signal of a corresponding channel from the analog verification card 30, and generate a report according to the functional analog signal and the analog output set value instruction; the CPU simulator 40 is used for generating a corresponding analog quantity signal according to the analog quantity output set value instruction and outputting the analog quantity signal to the electronic speed regulator 10; the analog quantity verification card 30 is used for collecting corresponding functional analog signals from the analog quantity output interface 16 of the electronic speed regulator 10, and the functional analog signals comprise: the analog quantity verification card 30 analyzes the functional analog signals to obtain the loading capacity values of the corresponding channels, and respectively uploads the loading capacity values of the corresponding channels and the collected corresponding functional analog signals to the upper computer 50.
In this embodiment, the analog output channel performance test of the electronic governor is performed by the CPU simulator 40 and the analog verification card 20 in cooperation with the electronic governor 10. Specifically, the upper computer 50 sends an analog output set value instruction to the CPU simulator 40, and the CPU simulator 40 analyzes the received instruction and generates corresponding analog data, which is transmitted to the main control board of the electronic governor 10 through the cable and PLCC packaging tool interface 111. The internal circuit of the electronic governor 10 processes the input analog signal into analog signals for the following actual functions: accelerator position, TCA Speed, diesel engine Speed, TCB Speed, load balancing, internal Speed set value and accelerator output. The analog quantity signal output of the actual function is mainly in three forms, which are: 4-20mA, 0-1V and 0-10V. The analog load testing unit 31 and the analog collecting unit 32 in the analog verification card 30 respectively process and analyze the collected multi-channel multi-type analog signals so as to upload the load capacity evaluation data and the analog data collection value to the upper computer 50. The upper computer 50 then performs report summarization and storage on the received data.
Fig. 7 is a logical structure diagram of a sixth embodiment of the performance testing system of the electronic governor according to the present invention, and a chip function test of the electronic governor is performed by the performance testing system of this embodiment. In this embodiment, the electronic governor specifically includes a PLCC socket 112 connected to a PLCC package tooling interface 111, and an on-board RAM113, an on-board rom (eeprom)114, a bus signal integrator 115, a driver 116, a watchdog 117, and an address latch 118 that are respectively connected to the PLCC socket 112.
The CPU simulator 40 of this embodiment can be connected to each on-board chip of the electronic governor through the PLCC package tooling interface 111, so that the work of the on-board chip can be checked and diagnosed by reading the configuration parameters and the state of each chip, specifically, the upper computer 50 is configured to send a parameter configuration instruction or a state reading instruction to the CPU simulator 40, and determine the chip function of the electronic governor 10 according to the return result of the CPU simulator 40; the CPU simulator 40 is configured to configure the parameters of the electronic governor or read the state of the electronic governor through the PLCC package tool interface 111 of the electronic governor according to the received parameter configuration command or the state reading command.
Furthermore, the port address can be analyzed according to the main chip, other chip manuals and circuit schematic diagrams, and the parameters of the electronic speed regulator are configured or the state of the electronic speed regulator is read, which specifically comprises the following steps: carrying out full address access verification on the onboard ROM and recording the erasing speed; testing the function of onboard RAM by performing high-capacity data operation and memory exchange; testing the function of the watchdog by outputting pulse signals with different frequencies and collecting reset signals of the watchdog; the function of the driver is tested by sending control instructions to the driver and collecting the output signal of the driver.
Fig. 8 is a flowchart of a first embodiment of a performance testing method of an electronic governor according to the present invention, the performance testing method of the embodiment including:
s11, the upper computer sends a test instruction to one of the logic quantity verification card, the analog quantity verification card and the CPU simulator;
s12, the upper computer collects an output signal from one of the logic quantity verification card, the analog quantity verification card and the CPU simulator;
and S13, analyzing the output signal by the upper computer to obtain a test result.
In an alternative embodiment, when a logic quantity input channel performance test of the electronic speed regulator is carried out, the following steps are carried out:
the upper computer sends a power supply signal generation instruction to the logic quantity verification card;
the logic quantity verification card generates an instruction according to the power supply signal, generates a corresponding power supply input signal and outputs the corresponding power supply input signal to a logic quantity input interface of the electronic speed regulator;
the CPU simulator collects corresponding interface data from the electronic speed regulator, judges the high and low levels of the interface data and records the high and low levels of the interface data in time sequence so as to obtain a power output signal, and sends the power output signal to an upper computer;
and the upper computer receives the power supply output signal from the CPU simulator and acquires the high level threshold value and the low level threshold value by combining the generation time sequence of the power supply input signal.
In this embodiment, according to the circuit diagram of the electronic governor, a signal is applied to the input end of the logic quantity input channel, the signal is a program-controlled power supply signal, a step voltage or a step voltage can be set, and whether the state of the channel changes or not is acquired at the corresponding data line end of the CPU simulator every time the signal is applied. The method can test the high level threshold value and the low level threshold value of the logic quantity input channel. Moreover, only one channel can be tested at a time, and a plurality of channels can be tested simultaneously.
In an alternative embodiment, when a logic quantity output channel performance test of the electronic speed regulator is carried out, the following steps are carried out:
the upper computer is used for sending a logic quantity output performance test instruction to the CPU simulator;
the CPU simulator generates a corresponding logic quantity signal according to the logic quantity output performance test instruction and outputs the logic quantity signal to the electronic speed regulator;
the logic quantity verification card receives the functional logic signal from the logic quantity output interface of the electronic speed regulator and analyzes the functional logic signal to obtain the loading capacity value of the corresponding channel;
and the upper computer receives and stores the loading capacity value of the corresponding channel from the logic quantity verification card.
In the embodiment, the load capacity of the output channel is tested by setting the state of each logic output channel through software according to a circuit diagram of the electronic speed regulator.
In an alternative embodiment, when the performance test of the frequency signal input channel of the electronic speed regulator is carried out, the following steps are carried out:
the upper computer sends a frequency signal generation instruction to the logic quantity verification card;
the logic quantity verification card generates an instruction according to the frequency signal, generates a corresponding frequency input signal and outputs the frequency input signal to a frequency input port of the electronic speed regulator;
the CPU simulator collects corresponding interface data from the electronic speed regulator, performs frequency/amplitude/waveform analysis and time sequence recording on the interface data to acquire a frequency output signal, and sends the frequency output signal to an upper computer;
and the upper computer receives the frequency output signal from the CPU simulator, and acquires a frequency response threshold and an amplitude minimum response threshold of the frequency signal input channel by combining the generation time sequence of the frequency input signal.
In the embodiment, according to a circuit diagram of the electronic speed regulator, sinusoidal or square wave signals with adjustable frequency and adjustable amplitude are added at the input end of a frequency input channel, the calculated frequency is collected in a corresponding channel of a CPU simulator, and a frequency response threshold and an amplitude minimum response threshold of the frequency signal input channel are tested.
In an optional embodiment, when the performance test of an analog output channel of the electronic speed regulator is carried out, the upper computer sends an analog output set value instruction to the CPU simulator;
the CPU simulator generates a corresponding analog quantity signal according to the analog quantity output set value instruction and outputs the analog quantity signal to the electronic speed regulator;
the analog quantity verification card collects corresponding functional analog signals from an analog quantity output interface of the electronic speed regulator, analyzes the functional analog signals to obtain the loading capacity values of corresponding channels, and respectively uploads the loading capacity values of the corresponding channels and the collected corresponding functional analog signals to an upper computer;
and the upper computer receives and stores the loading capacity value and the function simulation signal of the corresponding channel from the analog quantity verification card, and generates a report according to the function simulation signal and the analog quantity output set value instruction.
In the embodiment, according to a circuit diagram of the electronic speed regulator, different output values of analog quantity can be set through software, whether actual output is the same as a set value or not is collected and verified, channel verification is similar, and the maximum load carrying capacity of each channel is tested at the same time.
In an alternative embodiment, when performing a chip function test of the electronic governor, the following steps are performed:
the upper computer sends a parameter configuration instruction or a state reading instruction to the CPU simulator;
the CPU simulator configures the parameters of the electronic speed regulator or reads the state of the electronic speed regulator through a PLCC packaging tool interface of the electronic speed regulator according to the received parameter configuration instruction or state reading instruction;
and the upper computer determines the chip function of the electronic speed regulator according to the returned result.
In this embodiment, the CPU simulator reads data configuring the chip, sets the state of each functional module on the board, and reads the address assignment information and the data state of each port, thereby implementing verification of each functional module and chip on the board, such as function test and verification of the watchdog chip.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (9)
1. A performance testing system for an electronic governor, comprising:
a logic quantity verification card connected with the electronic speed regulator;
the analog quantity verification card is connected with the electronic speed regulator;
a CPU simulator connected with the electronic speed regulator and used for simulating and replacing a CPU of the electronic speed regulator;
the upper computer is connected with the logic quantity verification card, the analog quantity verification card, the CPU simulator and the electronic speed regulator, and is used for sending a test instruction to one of the logic quantity verification card, the analog quantity verification card and the CPU simulator, acquiring an output signal from one of the logic quantity verification card, the analog quantity verification card and the CPU simulator, and analyzing the output signal to acquire a test result.
2. The performance test system of an electronic governor according to claim 1, wherein, in performing a performance test of a logic quantity input channel of the electronic governor,
the upper computer is used for sending a power supply signal generation instruction to the logic quantity verification card, receiving a power supply output signal from the CPU simulator, and acquiring a high level threshold value and a low level threshold value in combination with a generation time sequence of the power supply input signal;
the logic quantity verification card is used for generating an instruction according to the power supply signal, generating a corresponding power supply input signal and outputting the corresponding power supply input signal to a logic quantity input interface of the electronic speed regulator;
and the CPU simulator is used for collecting corresponding interface data from the electronic speed regulator, judging high and low levels and recording time sequence of the interface data so as to obtain a power output signal and sending the power output signal to the upper computer.
3. The performance test system of an electronic governor according to claim 1, wherein, in performing a performance test of a logical quantity output channel of the electronic governor,
the upper computer is used for sending a logic quantity output performance test instruction to the CPU simulator and receiving and storing the loading capacity value of the corresponding channel from the logic quantity verification card;
the CPU simulator is used for generating a corresponding logic quantity signal according to the logic quantity output performance test instruction and outputting the corresponding logic quantity signal to the electronic speed regulator;
and the logic quantity verification card is used for receiving a functional logic signal from a logic quantity output interface of the electronic speed regulator and analyzing the functional logic signal to acquire the loading capacity value of the corresponding channel.
4. The performance test system of the electronic governor according to claim 1, wherein, in performing a performance test of a frequency signal input channel of the electronic governor,
the upper computer is used for sending a frequency signal generation instruction to the logic quantity verification card, receiving a frequency output signal from the CPU simulator, and acquiring a frequency response threshold and an amplitude minimum response threshold of a frequency signal input channel in combination with a generation time sequence of the frequency input signal;
the logic quantity verification card is used for generating an instruction according to the frequency signal, generating a corresponding frequency input signal and outputting the frequency input signal to the frequency input port of the electronic speed regulator;
the CPU simulator is used for collecting corresponding interface data from the electronic speed regulator, carrying out frequency/amplitude/waveform analysis and time sequence recording on the interface data so as to obtain a frequency output signal, and sending the frequency output signal to the upper computer.
5. The performance test system of the electronic governor according to claim 1, wherein, in performing a performance test of an analog output channel of the electronic governor,
the upper computer is used for sending an analog quantity output set value instruction to the CPU simulator, receiving and storing a loading capacity value and a functional simulation signal of a corresponding channel from the analog quantity verification card, and generating a report according to the functional simulation signal and the analog quantity output set value instruction;
the CPU simulator is used for generating a corresponding analog quantity signal according to the analog quantity output set value instruction and outputting the analog quantity signal to the electronic speed regulator;
the analog quantity verification card is used for collecting corresponding functional analog signals from an analog quantity output interface of the electronic speed regulator, analyzing the functional analog signals to obtain the loading capacity values of corresponding channels, and respectively uploading the loading capacity values of the corresponding channels and the collected corresponding functional analog signals to the upper computer.
6. The electronic governor performance testing system of claim 5, wherein the functional analog signal comprises: the system comprises an accelerator position signal, a TCA Speed rotating Speed signal, a diesel engine rotating Speed signal, a TCB Speed rotating Speed signal, a load balancing signal, an internal rotating Speed set value signal and an accelerator output signal.
7. The performance test system of the electronic governor according to claim 1, wherein, in performing a chip function test of the electronic governor,
the upper computer is used for sending a parameter configuration instruction or a state reading instruction to the CPU simulator and determining the chip function of the electronic speed regulator according to the returned result of the CPU simulator;
and the CPU simulator is used for configuring the parameters of the electronic speed regulator or reading the state of the electronic speed regulator through a PLCC packaging tool interface of the electronic speed regulator according to the received parameter configuration command or state reading command.
8. The performance testing system of the electronic governor of claim 7, wherein the electronic governor includes a PLCC socket connected to the PLCC package tooling interface, and an on-board ROM, an on-board RAM, a watchdog, a driver respectively connected to the PLCC socket, and,
configuring a parameter of the electronic governor or reading a status of the electronic governor, comprising:
carrying out full address access verification on the onboard ROM, and recording the erasing speed;
testing the function of the onboard RAM by performing high-capacity data operation and memory exchange;
testing the function of the watchdog by outputting pulse signals with different frequencies and collecting reset signals of the watchdog;
and testing the function of the driver by sending a control instruction to the driver and collecting an output signal of the driver.
9. A performance test method of an electronic speed regulator is characterized by comprising the following steps:
the upper computer sends a test instruction to one of the logic quantity verification card, the analog quantity verification card and the CPU simulator;
the upper computer collects an output signal from one of the logic quantity verification card, the analog quantity verification card and the CPU simulator;
and the upper computer analyzes the output signal to obtain a test result.
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