CN112599665A - RRAM Cell stack TaOx manufacturing method and structure - Google Patents
RRAM Cell stack TaOx manufacturing method and structure Download PDFInfo
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- CN112599665A CN112599665A CN202011362522.8A CN202011362522A CN112599665A CN 112599665 A CN112599665 A CN 112599665A CN 202011362522 A CN202011362522 A CN 202011362522A CN 112599665 A CN112599665 A CN 112599665A
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- taox
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- cell stack
- rram cell
- forming
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- 229910003070 TaOx Inorganic materials 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 40
- 230000008569 process Effects 0.000 claims abstract description 23
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 150000002978 peroxides Chemical class 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000008859 change Effects 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 238000005502 peroxidation Methods 0.000 abstract description 4
- 238000013461 design Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a manufacturing method of RRAM Cell stack TaOx, which comprises the following steps: forming a lower TiN layer of the RRAM Cell stack on the MxVx layer, and depositing Ta with a preset thickness T for the first time; forming a gradual TaOx layer which is not completely oxidized under a first preset condition; forming a Ta peroxide layer under a second preset condition; and depositing Ta and TiN again, and forming the RRAM Cell Stack structure through a photoetching process and an etching process. The invention also discloses an RRAM Cell stack TaOx structure. The invention adopts the change of the oxidation mode of Ta to obtain the graded structure of TaOx, obtains the TaOx resistance change material by controlling the oxidation condition step by step, and can avoid oxygen vacancy caused by difficult control of Ta peroxidation so as to meet the design requirement of devices.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing RRAM Cell stack TaOx. The invention also relates to a RAM Cell stack TaOx structure.
Background
With the further miniaturization of the logic process, particularly after the logic process enters a 40nm process node, the integration difficulty of the traditional EEPROM or NOR FLASH and the advanced logic process represented by HKMG and FinFET is further increased, the high manufacturing cost and the degraded device performance cannot be accepted by practical application, and the miniaturization meets a bottleneck, so that the research and development of the NOR FLASH in the world are stopped at the 55nm node for a long time; on the other hand, embedded application is very sensitive to power consumption, the traditional embedded Flash erasing voltage is as high as more than 10V and cannot be reduced along with the shrinking of process nodes, and an additional high-voltage circuit module is needed, so that the application of the embedded Flash erasing voltage in low-power-consumption occasions is limited;
the resistive random access memory is a novel storage technology and has a simple two-end structure, and the working mechanism of the resistive random access memory is that under the action of an external voltage, reversible conversion between a high-resistance state and a low-resistance state is realized by forming and breaking a conductive channel by a device, so that data is stored. The resistive random access memory has the characteristics of good scalability, easiness in three-dimensional stacking and the like, and the international semiconductor technology roadmap indicates that the resistive random access memory is one of novel storage technologies with the most commercial potential.
The TaOx forming process in the industry generally adopts three modes at present, wherein the first mode directly adopts a PVD mode to carry out TaOx film deposition, the second mode adopts a PVD mode to carry out Ta deposition, then adopts a CVD mode to oxidize Ta through an N2O mode, the third mode adopts a PVD mode to carry out Ta deposition, and then adopts a CVD or Asher mode to carry out O2 oxidation, the TaOx can be obtained by the three modes, but the three modes all have difficulty in controlling the oxidation degree, and in addition, certain difficulty exists in the subsequent process.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to solve the technical problem of providing a method for manufacturing RRAM Cell stack TaOx, which can avoid oxygen vacancy caused by difficult control of Ta peroxidation.
The invention aims to solve another technical problem of providing an RRAM Cell stack TaOx structure which can avoid oxygen vacancy caused by difficult control of Ta peroxidation.
In order to solve the technical problem, the method for manufacturing the RRAM Cell stack TaOx provided by the invention comprises the following steps:
s1, forming a lower TiN layer of the RRAM Cell stack on the MxVx layer, and depositing Ta with a preset thickness T for the first time;
s2, forming a gradient TaOx layer which is not completely oxidized under a first preset condition;
s3, forming a Ta peroxide layer under a second preset condition;
and S4, depositing Ta and TiN again, and forming the RRAM Cell Stack structure through a photoetching process and an etching process.
Optionally, the method for fabricating RRAM Cell stack TaOx is further modified, in step S1, Ta with a predetermined thickness T is deposited for the first time by using PVD process.
Optionally, the method for manufacturing RRAM Cell stack TaOx is further improved, and steps S2 and S3 both use a CVD process.
Optionally, in a further improvement of the method for manufacturing RRAM Cell stack TaOx, step S2 uses N20 to form an incompletely oxidized graded TaOx layer, where x of the incompletely oxidized graded TaOx layer is less than 5/2, and multiple Ta oxides exist in the incompletely oxidized graded TaOx layer, and the ratio of Ta atoms to oxygen atoms should be less than 5/2.
Optionally, the method for manufacturing RRAM Cell stack TaOx is further improved, and the first preset condition includes:
the CVD energy is 100W-200W, and the flow rate of N20 is 1000sccm-3000 sccm.
Optionally, the method for fabricating RRAM Cell stack TaOx is further modified, and step S3 uses N20 to form a Ta peroxide layer.
Optionally, the fabrication method of RRAM Cell stack TaOx is further improved, and the Ta peroxide layer is Ta2O5 layer
Optionally, the method for manufacturing RRAM Cell stack TaOx is further improved, and the second preset condition includes:
the CVD energy is 400W-500W, and the flow rate of N20 is 3000sccm-5000 sccm.
In order to solve the above technical problem, the present invention provides an RRAM Cell stack TaOx structure, including:
a first TiN layer, a Ta peroxide layer, a gradual TaOx layer which is not completely oxidized and a second TiN layer which are sequentially formed from top to bottom;
wherein the Ta peroxide layer is Ta2O5, and the incompletely oxidized graded TaOx layer has x < 5/2.
The invention adopts the change of the oxidation mode of Ta to obtain the gradual change structure of TaOx, thereby meeting the design requirement of the device. The method adopts a CVD mode to carry out oxidation treatment on Ta by N2O step by step, obtains the TaOx resistance change material by controlling the oxidation condition step by step, and can avoid oxygen vacancy caused by difficult control of Ta peroxidation so as to meet the design requirement of a device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a schematic structural diagram of a conventional RRAM Cell stack TaOx.
FIG. 2 is a schematic flow chart of a first embodiment of the present invention.
Fig. 3 is a first schematic diagram of a second embodiment of the present invention.
Fig. 4 is a schematic diagram of a second embodiment of the present invention.
FIG. 5 is a third schematic diagram of a second embodiment of the present invention.
FIG. 6 is a fourth schematic diagram of the second embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
A first embodiment;
as shown in fig. 2, a method for manufacturing RRAM Cell stack TaOx includes the following steps:
s1, forming a lower TiN (BE) layer of the RRAM Cell stack on the MxVx layer, and depositing Ta with the preset thickness T for the first time;
s2, forming a gradient TaOx layer which is not completely oxidized under a first preset condition;
s3, forming a Ta peroxide layer under a second preset condition;
and S4, depositing Ta and TiN (TE) again, and forming the RRAM Cell Stack structure through a photoetching process and an etching process.
A second embodiment;
with continued reference to fig. 2, a method for manufacturing RRAM Cell stack TaOx includes the following steps:
s1, as shown in FIG. 3, forming a lower TiN (BE) layer of the RRAM Cell stack on the MxVx layer, and depositing Ta with a preset thickness T for the first time by adopting a PVD process;
s2, as shown in FIG. 4, using CVD process, the energy is 100W-200W, preferably 200W, the N20 flow is 1000sccm-3000sccm, preferably 2000sccm, to form incompletely oxidized graded TaOx layer, wherein x of the incompletely oxidized graded TaOx layer is less than 5/2;
s3, as shown in FIG. 5, forming a Ta peroxide layer by CVD process with energy of 400-500W, preferably 300W, and N20 flow rate of 3000-5000 sccm, preferably 4000sccm, wherein the Ta peroxide layer is Ta2O5 layer;
s4, as shown in FIG. 6, depositing Ta and TiN (TE) again, and forming the RRAM Cell Stack structure through a photoetching process and an etching process.
A third embodiment;
the invention provides an RRAM Cell stack TaOx structure, comprising:
a first TiN layer, a Ta peroxide layer, a gradual TaOx layer which is not completely oxidized and a second TiN layer which are sequentially formed from top to bottom;
wherein the Ta peroxide layer is Ta2O5, and the incompletely oxidized graded TaOx layer has x < 5/2.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
1. A manufacturing method of RRAM Cell stack TaOx is characterized by comprising the following steps:
s1, forming a lower TiN layer of the RRAM Cell stack on the MxVx layer, and depositing Ta with a preset thickness T for the first time;
s2, forming a gradient TaOx layer which is not completely oxidized under a first preset condition;
s3, forming a Ta peroxide layer under a second preset condition;
and S4, depositing Ta and TiN again, and forming the RRAM Cell Stack structure through a photoetching process and an etching process.
2. The method of fabricating an RRAM Cell stack TaOx of claim 1, wherein:
in step S1, Ta with a predetermined thickness T is first deposited by PVD.
3. The method of fabricating an RRAM Cell stack TaOx of claim 1, wherein:
in steps S2 and S3, a CVD process is adopted.
4. The method of fabricating an RRAM Cell stack TaOx of claim 1, wherein:
step S2 forms an incompletely oxidized graded TaOx layer with N20, where x of the incompletely oxidized graded TaOx layer is < 5/2.
5. The method of claim 4, wherein the first predetermined condition comprises:
the CVD energy is 100W-200W, and the flow rate of N20 is 1000sccm-3000 sccm.
6. The method of fabricating an RRAM Cell stack TaOx of claim 1, wherein:
step S3 forms a Ta peroxide layer using N20.
7. The method of claim 6, wherein the method comprises: the Ta peroxide layer is a Ta2O5 layer.
8. The method of claim 6, wherein the second predetermined condition comprises:
the CVD energy is 400W-500W, and the flow rate of N20 is 3000sccm-5000 sccm.
9. An RRAM Cell stack TaOx structure, comprising:
a first TiN layer, a Ta peroxide layer, a gradual TaOx layer which is not completely oxidized and a second TiN layer which are sequentially formed from top to bottom;
wherein the Ta peroxide layer is Ta2O5, and the incompletely oxidized graded TaOx layer has x < 5/2.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090152526A1 (en) * | 2007-11-07 | 2009-06-18 | Interuniversitair Microelektronica Centrum (Imec) Vzw | Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof |
| CN102696107A (en) * | 2009-12-18 | 2012-09-26 | 松下电器产业株式会社 | Resistance-varying element and process for production thereof |
| US8883557B1 (en) * | 2013-09-03 | 2014-11-11 | Intermolecular, Inc. | Controlling composition of multiple oxides in resistive switching layers using atomic layer deposition |
| US20160005792A1 (en) * | 2014-07-02 | 2016-01-07 | Renesas Electronics Corporation | Semiconductor memory device, and method for producing the same |
| CN108630808A (en) * | 2017-03-16 | 2018-10-09 | 华邦电子股份有限公司 | Resistive random access memory structure and forming method thereof |
| CN109411602A (en) * | 2018-11-22 | 2019-03-01 | 上海华力微电子有限公司 | Tantalum oxide-based resistance-variable storing device and its manufacturing method |
| CN111799372A (en) * | 2020-05-15 | 2020-10-20 | 上海华力微电子有限公司 | Method for forming RRAM resistive switching structure |
-
2020
- 2020-11-27 CN CN202011362522.8A patent/CN112599665A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090152526A1 (en) * | 2007-11-07 | 2009-06-18 | Interuniversitair Microelektronica Centrum (Imec) Vzw | Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof |
| CN102696107A (en) * | 2009-12-18 | 2012-09-26 | 松下电器产业株式会社 | Resistance-varying element and process for production thereof |
| US20120252184A1 (en) * | 2009-12-18 | 2012-10-04 | Takeki Ninomiya | Variable resistance element and manufacturing method thereof |
| US8883557B1 (en) * | 2013-09-03 | 2014-11-11 | Intermolecular, Inc. | Controlling composition of multiple oxides in resistive switching layers using atomic layer deposition |
| US20160005792A1 (en) * | 2014-07-02 | 2016-01-07 | Renesas Electronics Corporation | Semiconductor memory device, and method for producing the same |
| CN108630808A (en) * | 2017-03-16 | 2018-10-09 | 华邦电子股份有限公司 | Resistive random access memory structure and forming method thereof |
| CN109411602A (en) * | 2018-11-22 | 2019-03-01 | 上海华力微电子有限公司 | Tantalum oxide-based resistance-variable storing device and its manufacturing method |
| CN111799372A (en) * | 2020-05-15 | 2020-10-20 | 上海华力微电子有限公司 | Method for forming RRAM resistive switching structure |
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