CN111799372A - Method for forming RRAM resistive switching structure - Google Patents
Method for forming RRAM resistive switching structure Download PDFInfo
- Publication number
- CN111799372A CN111799372A CN202010413713.6A CN202010413713A CN111799372A CN 111799372 A CN111799372 A CN 111799372A CN 202010413713 A CN202010413713 A CN 202010413713A CN 111799372 A CN111799372 A CN 111799372A
- Authority
- CN
- China
- Prior art keywords
- layer
- tantalum
- forming
- switching structure
- resistive switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 85
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 85
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 37
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 19
- 229910003070 TaOx Inorganic materials 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 4
- 230000008859 change Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005502 peroxidation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for forming a RRAM resistive switching structure, which comprises the following steps: providing a semiconductor substrate; forming a lower electrode on the semiconductor substrate; forming a first tantalum layer using a Ta of an α phase on the lower electrode, and forming a second tantalum layer using a Ta of a β phase on the first tantalum layer; oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer; and sequentially forming a barrier layer and an upper electrode on the tantalum oxide layer. In the invention, the tantalum forming the tantalum oxide layer is formed in two steps, and the materials of the tantalum formed in the two steps are different, namely, the first tantalum layer is formed by alpha-phase Ta, and then the second tantalum layer is formed by beta-phase Ta, so that the process and the degree of the tantalum oxidized into the tantalum oxide layer can be easily controlled, and the tantalum oxide layer with better effect is formed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a RRAM resistive switching structure.
Background
With the further miniaturization of logic processes, particularly after the logic process enters a 40nm process node, the integration difficulty of the traditional EEPROM (electrically erasable programmable read only memory) or NOR FLASH (nonvolatile FLASH memory) and the advanced logic process represented by HKMG (high-k insulating layer + metal gate process) and FinFET (FinFET field effect transistor) is further increased, the high manufacturing cost and the degraded device performance cannot be accepted by practical application, and the miniaturization meets a bottleneck, so that the international research and development on NOR FLASH is stopped at the 55nm node for a long time; on the other hand, embedded application is very sensitive to power consumption, the traditional embedded Flash erasing voltage is as high as more than 10V and cannot be reduced along with the shrinking of process nodes, and an additional high-voltage circuit module is needed, so that the application of the embedded Flash erasing voltage in low-power-consumption occasions is limited.
A Resistive Random-Access Memory (RRAM) is a novel Memory technology, and has a simple upper and lower end structure, and the working mechanism is that the resistance of a material is changed between a high resistance state and a low resistance state according to different voltages applied to a metal oxide, and the change is reversible, so that a current channel is opened or blocked for storing data. And the resistance change memory is a memory resistor which can still memorize electric charges after the power is turned off, and simultaneously transfer data quickly. In structure, it also has the characteristics of good scalability and easy three-dimensional stacking, so the international semiconductor technology roadmap indicates that the resistive random access memory is one of the most commercialized new memory technologies and is considered as the fourth element of the circuit.
The key structure of the resistive random access memory is a resistive random access memory, and one process structure layer of the resistive random access memory usually adopts TaOx as a resistive random access material. The process for forming TaOx generally adopts three modes in the prior art, wherein the first mode directly adopts a PVD (physical vapor deposition) mode to carry out TaOx film deposition; in the second mode, the deposition of Ta is carried out in a PVD (physical vapor deposition) mode, and then the oxidation of Ta is carried out in a CVD (chemical vapor deposition) mode in an N2O mode; the third method is to perform the deposition of Ta by PVD (physical vapor deposition) and then perform the oxidation by O2 by CVD (chemical vapor deposition), but all of the three methods use the same single oxidation condition in the oxidation process, and the value of X of TaOx is not constant, and the TaOx has multiple layers, so that the oxidation degree of TaOx is difficult to control by using the single oxidation condition, for example, the oxidation may be over-oxidized or insufficient.
Disclosure of Invention
The invention aims to provide a method for forming a RRAM resistive switching structure, which is easy to control the oxidation degree of a tantalum oxide layer in the RRAM resistive switching structure.
In order to achieve the above object, the present invention provides a method for forming a RRAM resistive switching structure, including:
providing a semiconductor substrate;
forming a lower electrode on the semiconductor substrate;
forming a first tantalum layer using a Ta of an α phase on the lower electrode, and forming a second tantalum layer using a Ta of a β phase on the first tantalum layer;
oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer;
and sequentially forming a barrier layer and an upper electrode on the tantalum oxide layer.
Optionally, in the forming method of the RRAM resistive switching structure, the semiconductor substrate includes a metal layer and a via layer.
Optionally, in the method for forming the RRAM resistive switching structure, the method for forming the lower electrode includes: forming a dielectric layer on the semiconductor substrate; etching the dielectric layer to expose the surface of the semiconductor substrate to form a groove; filling titanium nitride in the groove; the titanium nitride is ground so that the surface is flat shaped into the lower electrode.
Optionally, in the method for forming the RRAM resistance change structure, the material of the barrier layer includes tantalum, and the material of the upper electrode includes titanium nitride.
Optionally, in the method for forming the RRAM resistive switching structure, the tantalum oxide layer includes a TaOx layer and Ta on the TaOx layer2O5。
Optionally, in the method for forming the RRAM resistance change structure, X is less than 5/2.
Optionally, in the method for forming the RRAM resistive switching structure, the first tantalum layer and the second tantalum layer are both formed by physical vapor deposition.
Optionally, in the method for forming the RRAM resistance change structure, plasma energy for forming the first tantalum layer is greater than 400 w.
Optionally, in the method for forming the RRAM resistance change structure, plasma energy for forming the second tantalum layer is less than 200 w.
Optionally, in the method for forming the RRAM resistive switching structure, N used for oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer2And (4) an O oxidation mode.
In the method for forming the RRAM resistive switching structure, a semiconductor substrate is provided; forming a lower electrode on the semiconductor substrate; forming a first tantalum layer using a-phase Ta and a second tantalum layer using a β -phase Ta on the lower electrode; oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer; and sequentially forming a barrier layer and an upper electrode on the tantalum oxide layer. The tantalum forming the tantalum oxide layer is formed in two steps, the materials of the tantalum formed in the two steps are different, namely, the first tantalum layer is formed by alpha-phase Ta, and then the second tantalum layer is formed by beta-phase Ta, so that the process and the degree of the tantalum oxidized into the tantalum oxide layer can be easily controlled, and the tantalum oxide layer with better effect is formed.
Drawings
Fig. 1 is a flowchart of a method of forming a RRAM resistive switching structure according to an embodiment of the present invention;
fig. 2 to 5 are schematic structural diagrams of a method for forming a RRAM resistive switching structure according to an embodiment of the present invention;
in the figure: 100-semiconductor substrate, 110-copper, 120-low dielectric constant material, 130-dielectric layer, 140-lower electrode, 150-tantalum oxide layer, 151-first tantalum layer, 152-second tantalum layer, 160-barrier layer and 170-upper electrode.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are designed in a simplified manner and are not to scale, this being done solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, the order in which those steps are presented herein is not necessarily the only order in which those steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
After the research of the inventor, the inventor improves on the first mode based on the prior art, and in the process of forming TaOx, in order to solve the problem of peroxidation, more oxygen vacancies can be formed, so that a gradual change structure is formed. Referring to fig. 1, the present invention provides a method for forming a RRAM resistive switching structure, including:
s11: providing a semiconductor substrate;
s12: forming a lower electrode on the semiconductor substrate;
s13: forming a first tantalum layer using a-phase Ta and a second tantalum layer using a β -phase Ta on the lower electrode;
s14: oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer;
s15: and sequentially forming a barrier layer and an upper electrode on the tantalum oxide layer.
Referring to fig. 2, the present invention provides a semiconductor substrate 100, wherein a RRAM resistive structure is formed on a structure of the semiconductor substrate 100, and the resistive structure is in a high resistive state and a low resistive state, so as to turn on and off a current, and thus, the RRAM resistive structure can be formed on any semiconductor structure having an electrical function. For example, the semiconductor substrate 100 herein includes a metal layer and a via layer. Referring to fig. 2, as a schematic diagram of an embodiment of the present invention, a metal layer is used as an example of a semiconductor substrate, and the metal layer may be copper 110 and a low-k material 120 located on both sides of the copper 110. The metal layer can be any one of a number of metal layers, such as a Top layer, a Bottom layer, and any layer between a Top layer and a Bottom layer. And if a via layer, the via layer may be a via and a low dielectric constant material on both sides of the via.
Next, with reference to fig. 2, a dielectric layer 130 is formed on the semiconductor substrate 100, wherein the dielectric layer 130 may be made of silicon carbonitride (NDC), and in other embodiments of the present invention, may be made of other materials, such as silicon nitride; etching the dielectric layer 130 to expose the semiconductor substrate surface 100 to form a groove; filling titanium nitride in the groove; and grinding the titanium nitride to make the surface smooth. The ground titanium nitride forms the lower electrode 140.
Next, referring to fig. 3, the first tantalum layer is formed on the dielectric layer 130 and the lower electrode 140, and the second tantalum layer 152 is formed on the first tantalum layer 151. The first tantalum layer 151 is a Ta phase, and the second tantalum layer 152 is a Ta phase. The order of the α -phase Ta and the β -phase Ta cannot be changed, i.e., the α -phase Ta is formed first and then the β -phase Ta is formed. The first tantalum layer 151 and the second tantalum layer 152 are formed by physical vapor deposition, and the physical vapor deposition may be a PVD sputtering plate process. Further, the plasma energy for forming the first tantalum layer 151 is greater than 400w, and the plasma energy for forming the second tantalum layer 152 is less than 200 w. The alpha phase of Ta and the beta phase of Ta are tantalum formed under different conditions, and therefore, the reactions to oxidation are completely different between them, and one may be completely oxidized while the other may not have been completely oxidized. Thus, under a single oxidation condition, the combination of Ta in the alpha phase and Ta in the beta phase cannot all be fully oxidized, i.e., not all Ta is formed2O5. Some of which form TaOx, X may be any value less than 5/2.
The thicknesses of the first tantalum layer 151 and the second tantalum layer 152 are not limited, but the sum of the thicknesses of the first tantalum layer 151 and the second tantalum layer 152 is a thickness required for a tantalum oxide layer in actual operation of the embodiment of the present invention, and therefore, the thicknesses of the first tantalum layer 151 and the second tantalum layer 152 are determined in a specific operation. For example, if the tantalum oxide layer thickness is required to be 500 angstroms, the first tantalum layer 151 may be 300 angstroms and the second tantalum layer 152 200 angstroms, and conversely, if the first tantalum layer 151 is 200 angstroms and the second tantalum layer 152 is 300 angstroms, this is also possible.
Next, referring to fig. 4, the first tantalum layer 151 and the second tantalum layer 152 are oxidized to form tantalum oxideThe layer 150 is oxidized by N2O. The tantalum oxide layer 150 includes a TaOx layer and Ta on the TaOx layer2O5And said X is less than 5/2. That is, the tantalum oxide layer 150 includes a plurality of layers except for the uppermost Ta layer2O5Layer, also TaOx layer, e.g. Ta2O4Layer or Ta2O3Or Ta2O2And may even be Ta for example2And O. It is possible that X is less than 5/2, and these oxides are the most desirable tantalum oxide layers for RRAM resistive switching structures. In the prior art, TaOx is formed by three methods, wherein the first method directly adopts a PVD method to deposit a TaOx film; in the second mode, Ta is deposited in a PVD mode, and then Ta is oxidized in a CVD mode in an N2O mode; the third method is to deposit Ta by PVD and then oxidize O2 by CVD. The oxidation degree of the three methods is not easy to control, and the oxidation can be carried out once all the three methods are oxidized, namely, the peroxidation is carried out, and Ta is formed all the time2O5By adopting the method for forming the tantalum oxide layer 150 provided by the invention, the completely oxidized tantalum oxide layer and other forms of tantalum oxide layers can be formed, the oxidation result is easier to control, and the oxidation effect is better.
Next, referring to fig. 5, a barrier layer 160 is formed on the tantalum oxide layer 150, wherein the material of the barrier layer 160 includes tantalum, and the tantalum may be formed by PVD (physical vapor deposition). After physical vapor deposition of tantalum, the tantalum surface is polished to form a tantalum oxide layer 150.
Next, an upper electrode 170 is formed on the barrier layer 150, and a material of the upper electrode 170 includes titanium nitride. The titanium nitride may be formed by PVD (physical vapor deposition). In other embodiments of the present invention, a via structure may be further formed on the upper electrode 170 for communicating the resistive switching structure with a peripheral circuit. The methods of forming the barrier layer 160 and forming the upper electrode 170 according to the embodiments of the present invention may all adopt the prior art, and therefore, the detailed description thereof is omitted.
In summary, in the method for forming the RRAM resistive switching structure provided in the embodiments of the present invention, a semiconductor substrate is provided; forming a lower electrode on the semiconductor substrate; forming a first tantalum layer using a-phase Ta and a second tantalum layer using a β -phase Ta on the lower electrode; oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer; and sequentially forming a barrier layer and an upper electrode on the tantalum oxide layer. The tantalum forming the tantalum oxide layer is formed in two steps, the materials of the tantalum formed in the two steps are different, namely, the first tantalum layer is formed by alpha-phase Ta, and then the second tantalum layer is formed by beta-phase Ta, so that the process and the degree of the tantalum oxidized into the tantalum oxide layer can be easily controlled, and the tantalum oxide layer with better effect is formed.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for forming a RRAM resistive switching structure is characterized by comprising the following steps:
providing a semiconductor substrate;
forming a lower electrode on the semiconductor substrate;
forming a first tantalum layer using a Ta of an α phase on the lower electrode, and forming a second tantalum layer using a Ta of a β phase on the first tantalum layer;
oxidizing the first tantalum layer and the second tantalum layer to form a tantalum oxide layer;
and sequentially forming a barrier layer and an upper electrode on the tantalum oxide layer.
2. The method of forming a RRAM resistive switching structure of claim 1, wherein the semiconductor substrate includes a metal layer and a via layer.
3. The method of forming a RRAM resistive switching structure of claim 1, wherein the method of forming the lower electrode comprises:
forming a dielectric layer on the semiconductor substrate;
etching the dielectric layer to expose the surface of the semiconductor substrate to form a groove;
filling titanium nitride in the groove;
and grinding the titanium nitride to enable the surface of the titanium nitride to be flat to form the lower electrode.
4. The method of forming a RRAM resistive switching structure of claim 1, wherein the material of the barrier layer comprises tantalum and the material of the upper electrode comprises titanium nitride.
5. The method of forming a RRAM resistive-switching structure of claim 1, wherein the tantalum oxide layer comprises a TaOx layer and Ta on the TaOx layer2O5。
6. The method for forming the RRAM resistive switching structure according to claim 5, wherein X is less than 5/2.
7. The method for forming a RRAM resistive switching structure according to claim 1, wherein the first tantalum layer and the second tantalum layer are both formed by physical vapor deposition.
8. The method for forming a RRAM resistive switching structure according to claim 7, wherein the first tantalum layer is formed with a plasma energy of more than 400 w.
9. The method for forming a RRAM resistive switching structure according to claim 8, wherein the second tantalum layer is formed with a plasma energy of less than 200 w.
10. The method of forming a RRAM resistive switching structure of claim 9, wherein the oxide is oxidizedN used for forming tantalum oxide layer by the first tantalum layer and the second tantalum layer2And (4) an O oxidation mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010413713.6A CN111799372B (en) | 2020-05-15 | 2020-05-15 | Method for forming RRAM resistive switching structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010413713.6A CN111799372B (en) | 2020-05-15 | 2020-05-15 | Method for forming RRAM resistive switching structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111799372A true CN111799372A (en) | 2020-10-20 |
| CN111799372B CN111799372B (en) | 2023-03-24 |
Family
ID=72806697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010413713.6A Active CN111799372B (en) | 2020-05-15 | 2020-05-15 | Method for forming RRAM resistive switching structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111799372B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112599665A (en) * | 2020-11-27 | 2021-04-02 | 上海华力微电子有限公司 | RRAM Cell stack TaOx manufacturing method and structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1418150A (en) * | 2000-02-29 | 2003-05-14 | 莱克斯马克国际公司 | Method for producing desired tantalum phase |
| JP2005298975A (en) * | 2004-04-15 | 2005-10-27 | Hewlett-Packard Development Co Lp | Method of making tantalum layer and apparatus using tantalum layer |
| US20080127480A1 (en) * | 2006-12-05 | 2008-06-05 | Spansion Llc | Method of fabricating metal-insulator-metal (mim) device with stable data retention |
| TW201327794A (en) * | 2011-12-27 | 2013-07-01 | Ind Tech Res Inst | A resistive random access memory and its fabrication method |
| US20140112059A1 (en) * | 2011-06-24 | 2014-04-24 | Feng Miao | High-reliability high-speed memristor |
| WO2017019068A1 (en) * | 2015-07-29 | 2017-02-02 | Hewlett Packard Enterprise Development Lp | Non-volatile resistance memory devices including a volatile selector with copper and tantalum oxide |
| CN109411602A (en) * | 2018-11-22 | 2019-03-01 | 上海华力微电子有限公司 | Tantalum oxide-based resistance-variable storing device and its manufacturing method |
| US20190088870A1 (en) * | 2017-09-19 | 2019-03-21 | Toshiba Memory Corporation | Memory element |
| CN110112096A (en) * | 2019-05-17 | 2019-08-09 | 长江存储科技有限责任公司 | Metal interconnection structure and forming method thereof |
-
2020
- 2020-05-15 CN CN202010413713.6A patent/CN111799372B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1418150A (en) * | 2000-02-29 | 2003-05-14 | 莱克斯马克国际公司 | Method for producing desired tantalum phase |
| JP2005298975A (en) * | 2004-04-15 | 2005-10-27 | Hewlett-Packard Development Co Lp | Method of making tantalum layer and apparatus using tantalum layer |
| US20080127480A1 (en) * | 2006-12-05 | 2008-06-05 | Spansion Llc | Method of fabricating metal-insulator-metal (mim) device with stable data retention |
| US20140112059A1 (en) * | 2011-06-24 | 2014-04-24 | Feng Miao | High-reliability high-speed memristor |
| TW201327794A (en) * | 2011-12-27 | 2013-07-01 | Ind Tech Res Inst | A resistive random access memory and its fabrication method |
| WO2017019068A1 (en) * | 2015-07-29 | 2017-02-02 | Hewlett Packard Enterprise Development Lp | Non-volatile resistance memory devices including a volatile selector with copper and tantalum oxide |
| US20190088870A1 (en) * | 2017-09-19 | 2019-03-21 | Toshiba Memory Corporation | Memory element |
| CN109411602A (en) * | 2018-11-22 | 2019-03-01 | 上海华力微电子有限公司 | Tantalum oxide-based resistance-variable storing device and its manufacturing method |
| CN110112096A (en) * | 2019-05-17 | 2019-08-09 | 长江存储科技有限责任公司 | Metal interconnection structure and forming method thereof |
Non-Patent Citations (1)
| Title |
|---|
| CARLOS M. M. ROSÁRIO等: "Metallic filamentary conduction in valence change-based resistive switching devices: the case of TaOx thin film with x ~ 1", 《NANOSCALE》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112599665A (en) * | 2020-11-27 | 2021-04-02 | 上海华力微电子有限公司 | RRAM Cell stack TaOx manufacturing method and structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111799372B (en) | 2023-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108369956B (en) | Ferroelectric capacitor, ferroelectric field effect transistor and method for use in forming electronic component comprising conductive material and ferroelectric material | |
| US9112144B2 (en) | Method of fabricating a resistive non-volatile memory device | |
| US9343677B2 (en) | GCIB-treated resistive device | |
| US9343673B2 (en) | Method for forming metal oxides and silicides in a memory device | |
| US8148765B2 (en) | Resistive random access memory | |
| US20140264237A1 (en) | Resistive ram and fabrication method | |
| US10460798B2 (en) | Memory cells having a plurality of resistance variable materials | |
| CN102656692B (en) | Non-volatile memory device | |
| WO2012162867A1 (en) | Resistive random access memory using electric field enhancement layer and method for manufacturing same | |
| CN101159309A (en) | Method for implementing low power consumption resistance memory | |
| KR101942606B1 (en) | Method for forming resistive switching memory elements | |
| CN111584711B (en) | RRAM device and method for forming RRAM device | |
| TW201411814A (en) | Resistance memory cell, resistance memory array and method of forming the same | |
| CN111799372B (en) | Method for forming RRAM resistive switching structure | |
| US20140138599A1 (en) | Nonvolatile memory element and method for manufacturing the same | |
| US8872152B2 (en) | IL-free MIM stack for clean RRAM devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |