CN116157003A

CN116157003A - Resistive random access memory element, memory device and preparation method thereof

Info

Publication number: CN116157003A
Application number: CN202310207630.5A
Authority: CN
Inventors: 刘业帆; 张冠群; 周烽; 陈亮
Original assignee: Xinyuan Semiconductor Hangzhou Co ltd; Xinyuan Semiconductor Shenzhen Co ltd; Xinyuan Semiconductor Shanghai Co ltd
Current assignee: Xinyuan Semiconductor Hangzhou Co ltd; Xinyuan Semiconductor Shenzhen Co ltd; Xinyuan Semiconductor Shanghai Co ltd
Priority date: 2023-03-06
Filing date: 2023-03-06
Publication date: 2023-05-23

Abstract

The invention provides a resistance random access memory element, a memory device and a preparation method thereof, wherein the memory element comprises a first electrode, a resistance change memory layer and a second electrode which are sequentially arranged; the material of the second electrode is MNx, and the material of the resistive random access memory layer is MOy, wherein M is selected from one of Ti, ta and Al. According to the invention, the metal atoms of the second electrode and the metal atoms of the resistive memory layer are set to be the same metal atoms, and meanwhile, the metal atoms are the same as the metal atoms of the conductive channel, so that the M metal atoms participating in the conductive channel can be effectively prevented from being excessively enriched, the service life and durability of the device are improved, the holding capacity of the device is improved, and better device performance is obtained. According to the invention, the N proportion in the second electrode is controlled, so that the second electrode has conductivity, and meanwhile, the migration and diffusion of metal ions into the resistive memory layer are more controllable.

Description

Resistive random access memory element, memory device and preparation method thereof

Technical Field

The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a resistive random access memory element, a memory device and a preparation method thereof.

Background

A resistive random-access memory (ReRAM) belongs to a non-volatile memory (NVM), and has the characteristics of smaller size, fast read-write, long data storage time, low energy consumption, good reliability, compatibility with semiconductor manufacturing processes, and the like, so that the ReRAM is receiving attention in the field. The basic structure of the resistance random access memory is that a variable resistance layer is clamped between an upper electrode and a lower electrode, a variable resistance material is converted between a high resistance state (high resistance state, HRS) and a low resistance state (low resistance state, LRS) by applying voltage, and then different resistance states are compiled into 1 or 0 to achieve the purpose of storing and distinguishing data.

The current resistive random access memory (ReRAM) is mainly divided into Conductive Bridge Random Access Memory (CBRAM) and oxide random access memory (Oxygen-vacancy random access memory, oxRAM), and its structure mainly includes three parts of Top Electrode (TE), resistive layer (SL) and Bottom Electrode (BE). In an oxide random access memory, oxygen ions in a resistive layer (SL) migrate under the action of an electric field, and finally form a conductive channel (filevent) composed of oxygen vacancies. In a conductive bridge random access memory, metal in one side electrode ionizes under the action of an electric field and enters a resistive layer (SL), and finally a conductive channel composed of metal particles is formed. The conventional resistive random access memory device often suffers from various reliability problems, such as limited cycle characteristics and retention capability due to materials.

It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a resistive random access memory device, a resistive random access memory device and a method for manufacturing the same, which are used for solving the problem of insufficient reliability of the resistive random access memory in the prior art.

To achieve the above and other related objects, the present invention provides a resistive random access memory element comprising: the first electrode, the resistance change storage layer and the second electrode are sequentially arranged; and the material of the second electrode is MNx, wherein M is one of Ti, ta and Al, and x is more than or equal to 0 and less than or equal to 1.

Optionally, the second electrode MNx includes N second sub-electrode layers, N is greater than or equal to 2, and N proportion x in the N second sub-electrode layers decreases from the resistive memory layer toward a direction away from the resistive memory layer.

Optionally, the difference of the N ratio x in the two adjacent second sub-electrode layers is greater than or equal to 0.05.

Optionally, among the N second sub-electrode layers, the thickness of the second sub-electrode layer with the largest N proportion x is less than or equal to 5 nanometers.

Optionally, among the N second sub-electrode layers, the thickness of the second sub-electrode layer increases as the N ratio x thereof decreases.

Optionally, the N proportion x in the second electrode MNx decreases linearly from the resistive memory layer toward a direction away from the resistive memory layer.

Optionally, the N ratio x in the second electrode MNx is greater than or equal to 0.3 and less than or equal to the stoichiometric ratio of M and N.

Optionally, the resistive memory layer is made of MOy, and metal atoms in the resistive memory layer MOy are the same as metal atoms in the second electrode MNx, wherein M is selected from one of Ti, ta and Al, and y is more than or equal to 0 and less than or equal to 1.

Optionally, the metal atom of the conductive channel of the resistive random access memory element is M, which is the same as the metal atom in the second electrode MNx and the resistive memory layer MOy, where the metal atom M migrates to the second electrode and forms a conductive channel composed of the metal atom M in the resistive memory layer, so that the resistive memory layer is turned into a low-resistance state, or/and O in the resistive memory layer migrates to form a conductive channel formed by oxygen holes in the resistive memory layer, so that the resistive memory layer is turned into a low-resistance state.

Optionally, the material of the first electrode is an inert metal or a metal nitride, wherein the inert metal comprises one of W and Pt, and the metal nitride comprises one of TiN and TaN.

Optionally, side wall structures are further formed on the side walls of the first electrode, the resistive random access memory layer and the second electrode.

Optionally, the resistive random access memory element further comprises: an interlayer dielectric layer disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer, and the electrode hole structure comprises a Damascus structure; and the electrode hole structure is filled with a metal electrode, and metal atoms in the metal electrode are M and the same as metal atoms in the second electrode MNx.

The invention also provides a resistive random access memory device comprising an array of a plurality of resistive random access memory elements as described in any of the above aspects.

The invention also provides a preparation method of the resistance random access memory element, which comprises the following steps: and forming a first electrode, a resistive random access memory layer and a second electrode which are sequentially arranged, wherein the material of the second electrode is MNx, M is selected from one of Ti, ta and Al, and x is more than or equal to 0 and less than or equal to 1.

Optionally, forming the second electrode includes: and growing N layers of second sub-electrode layers layer by layer on the resistive random access memory layer by a deposition method, and reducing the N proportion x in the N second sub-electrode layers layer by layer from the resistive random access memory layer towards the direction away from the resistive random access memory layer by controlling the N proportion in each layer of the second sub-electrode layers.

Optionally, forming the second electrode includes: growing N layers of second sub-electrode layers layer by layer on the resistive random access memory layer by a deposition method, and controlling the proportion of N in each layer of second sub-electrode layers to enable the proportion x of N in N second sub-electrode layers to be reduced layer by layer from the resistive random access memory layer towards a direction away from the resistive random access memory layer; and (3) performing an annealing process in an N atmosphere to diffuse N in the second sub-electrode layer, so that the proportion x of N in the second electrode MNx linearly decreases from the resistive memory layer towards a direction away from the resistive memory layer.

Optionally, the proportion of N in each of the second sub-electrode layers is adjusted by controlling the ambient atmosphere, power and bias voltage during the deposition process.

Optionally, the preparation method further comprises the steps of: and forming a side wall structure on the side walls of the first electrode, the resistive random access memory layer and the second electrode.

Optionally, the preparation method further comprises the steps of: forming an interlayer dielectric layer on the second electrode; forming an electrode hole structure exposing the second electrode in the interlayer dielectric layer, wherein the electrode hole structure comprises a Damascus structure; and forming a metal electrode in the electrode hole structure, wherein metal atoms in the metal electrode are M and the same as those in the second electrode MNx and the resistive random access memory layer MOy.

Optionally, forming the resistive memory layer includes: and growing a plurality of MOy material layers layer by a deposition method, and regulating the proportion of O in each MOy material layer by controlling the ambient atmosphere, power and bias voltage in the deposition process.

As described above, the resistive random access memory device and the method for manufacturing the same of the present invention have the following advantages:

according to the invention, the material of the second electrode is MNx, the material of the resistive memory layer is MOy, the metal atoms of the second electrode and the metal atoms of the resistive memory layer are set to be the same metal atoms, and meanwhile, the conductive channel and the conductive channel have the same metal atoms, so that the M metal atoms participating in the conductive channel can be effectively prevented from being excessively enriched, the service life and the durability of the device are improved, the holding capacity of the device is improved, and better device performance is obtained.

The invention can realize that the second electrode has conductivity and the migration and diffusion of metal ions into the resistive memory layer have higher controllability by controlling the proportion of N in the second electrode MNx.

The preparation process can control the proportion of N in the second electrode MNx according to different requirements, is convenient for adjusting the performance of the device, and has stronger controllability.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some of the embodiments of the present application.

FIG. 1 is a schematic diagram of a resistance random access memory device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of another resistance random access memory device according to an embodiment of the invention.

Fig. 3 to 11 are schematic structural diagrams showing steps of a method for manufacturing a resistive random access memory device according to an embodiment of the invention.

FIG. 12 is a graph showing the cycle characteristics of a resistive random access memory device according to an embodiment of the present invention.

Fig. 13 shows a cycle characteristic diagram of a resistive random access memory element implemented for a conventional method.

Description of element reference numerals

101. First electrode

102. Resistive memory layer

103. 104 second electrode

1031. 1032, 1033 second sub-electrode layer

201. Metal layer

202. Interlayer dielectric layer

203. Conductive hole

105. Side wall structure

106. Insulating layer

107. Electrode hole structure

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

As shown in fig. 1, the present embodiment provides a resistive random access memory element, which includes: a first electrode 101, a resistive memory layer 102, and a second electrode 103 arranged in this order; the material of the second electrode 103 is MNx (metal nitride), and the material of the resistive memory layer 102 is MOy (metal oxide), where M is one selected from Ti (titanium), ta (tantalum) and Al (aluminum), x is 0-1, and y is 0-1. For example, the material of the second electrode 103 may be TiNx, the material of the resistive memory layer 102 may be TiOy, or the material of the second electrode 103 may be TaNx, the material of the resistive memory layer 102 may be TaOy, or the material of the second electrode 103 may be AlNx, and the material of the resistive memory layer 102 may be AlOy. According to the invention, the material of the second electrode 103 is MNx, the material of the resistive random access memory layer 102 is MOy, the metal atoms of the second electrode 103 and the metal atoms of the resistive random access memory layer 102 are set to be the same metal elements, and meanwhile, the conductive channel has the same metal atoms, so that the M metal atoms participating in the conductive channel can be effectively prevented from being excessively enriched, the service life and the durability of the device are improved, the holding capacity of the device is improved, and better device performance is obtained.

In one embodiment, the material of the first electrode 101 is an inert metal or a metal nitride, specifically, the inert metal may be one of W and Pt, and the metal nitride may be one of TiN and TaN.

In one embodiment, the second electrode 103 includes N second

sub-electrode layers

1031, 1032, 1033, N being equal to or greater than 2, and the N (nitrogen) ratio x in the N second

sub-electrode layers

1031, 1032, 1033 decreases from the resistive memory layer 102 in a direction away from the resistive memory layer 102.

As shown in fig. 1, in a specific example, the second electrode 103 includes 3 second

sub-electrode layers

1031, 1032, 1033,3, and the N ratio in the second

sub-electrode layers

1031, 1032, 1033 may be x1, x2, and x3, respectively, where x1, x2, and x3 decrease from the resistive memory layer 102 toward a direction away from the resistive memory layer 102, i.e., x1 > x2 > x3.

In one embodiment, the N ratio x in the second electrode 103 is greater than or equal to 0.3 to ensure that the N ratio x has a better control effect on migration and diffusion of metal ions into the resistive memory layer 102, and the N ratio x is less than or equal to the stoichiometric ratio of M and N, so as to avoid that the structural stability and conductivity of the second electrode 103 are affected by too high N ratio, and the difference of the N ratio x in the adjacent two second

sub-electrode layers

1031, 1032, 1033 is greater than or equal to 0.05, so that a better control effect on migration and diffusion of metal ions is formed by the N ratio gradient.

In a specific example, taking the second electrode 103 as AlNx as an example, the stoichiometric ratio of Al to N is 1, and the N ratio x thereof may be in a range of 0.3 to 1, for example, in AlNx, the values of x1, x2 and x3 may be 1, 0.8 and 0.6, respectively, that is, the materials of the three second

sub-electrode layers

1031, 1032 and 1033The materials are AlN and AlN respectively _0.8 、AlN _0.6 . Of course, the values of x1, x2 and x3 may be 0.8, 0.5 and 0.3, i.e. the materials of the three second

sub-electrode layers

1031, 1032 and 1033 are AlN respectively _0.8 、AlN _0.5 And AlN _0.3 . Of course, the value of N of each of the second

sub-electrode layers

1031, 1032, 1033 in AlNx may be set according to the actual device requirement, and is not limited to the above-listed examples. In other embodiments, the material of the second electrode 103 may be TiNx or TaNx, and the specific value thereof may be set according to the parameter requirement of the device. The number of the second

sub-electrode layers

1031, 1032, 1033 included in the second electrode 103 may be set to be larger, for example, 4 to 10 layers. The invention can realize that the second electrode 103 has conductivity and the migration and diffusion of metal ions into the resistive memory layer 102 have higher controllability by controlling the N proportion in the second electrode 103.

In one embodiment, among the N second

sub-electrode layers

1031, 1032, 1033, the thickness of the

second sub-electrode layer

1031, 1032, 1033 with the largest N proportion x is less than or equal to 5 nm, so as to ensure that the subsequent metal atoms can reach the resistive memory layer 102 and form a conductive channel through the

second sub-electrode layer

1031, 1032, 1033 with the largest N proportion x. In one embodiment, among the N second

sub-electrode layers

1031, 1032, 1033, the thickness of the second

sub-electrode layers

1031, 1032, 1033 increases as the N ratio x thereof decreases.

In one embodiment, fig. 2 is a schematic structural diagram of another resistive random access memory device, in which the N ratio x in the second electrode 104 decreases linearly from the resistive memory layer 102 toward a direction away from the resistive memory layer 102 in the resistive random access memory device of fig. 2. The resistive random access memory element removes the stepwise change of the N proportion in the embodiment, and the N proportion x is set to be linear change, so that migration and diffusion of metal atoms are smoother and the controllability is higher.

In one embodiment, the metal atom of the conductive channel of the resistive random access memory element is M, which is the same as the metal atom in the second electrode 103 and the resistive memory layer 102, where the metal atom M migrates into the second electrode 103 and the resistive memory layer 102 to form a conductive channel composed of the metal atom M, so that the resistive memory layer 102 is turned into a low resistance state, or/and O (oxygen) in the resistive memory layer 102 migrates into the resistive memory layer 102 to form a conductive channel formed by an oxygen hole, so that the resistive memory layer 102 is turned into a low resistance state.

In one embodiment, referring to fig. 10 or 11, the sidewalls of the first electrode, the resistive memory layer, and the second electrode may be further formed with a sidewall structure 105.

In one embodiment, referring to fig. 10 or 11, the resistive random access memory device may further include: an interlayer dielectric layer 106 disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer 106, and the electrode hole structure comprises a damascene structure; the electrode hole structure is filled with a metal electrode 107, and metal atoms in the metal electrode 107 are the same as metal atoms in the second electrode MNx.

The present embodiment also provides a resistive random access memory device comprising an array of a plurality of resistive random access memory elements according to any one of the above aspects.

As shown in fig. 3 to 11, the present embodiment further provides a method for manufacturing a resistive random access memory device, where the method includes the steps of: the first electrode 101, the resistive random access layer 102 and the second electrode 103 which are sequentially arranged are formed, the material of the second electrode 103 is MNx, the material of the resistive random access layer 102 is MOy, wherein M is selected from one of Ti, ta and Al, x is more than or equal to 0 and less than or equal to 1, and y is more than or equal to 0 and less than or equal to 1.

Specifically, the preparation method comprises the following steps:

as shown in fig. 3, step 1) is first performed, and a circuit substrate is provided, where the substrate includes a substrate, a metal layer 201 disposed on the substrate, an insulating layer 106 disposed on the metal layer 201, and a conductive via 203 disposed in the insulating layer 106.

The substrate may be, for example, a silicon substrate, a germanium-silicon substrate, a group iii-v compound substrate, a silicon carbide substrate, an SOI substrate, or the like. Various circuit elements, such as NMOS transistors, PMOS transistors, capacitors, resistors, etc., may be formed in the substrate to achieve corresponding circuit functions.

As shown in fig. 4, step 2) is then performed, and the first electrode 101 is formed on the circuit substrate by using a deposition method, wherein the material of the first electrode 101 is an inert metal or a metal nitride, specifically, the inert metal may be one of W and Pt, and the metal nitride may be one of TiN and TaN.

As shown in fig. 5, step 3) is then performed to form a resistive memory layer 102 on the first electrode 101, and specifically, a plurality of MOy material layers may be grown layer by a deposition method, and the proportion of O in each MOy material layer may be adjusted by controlling the ambient atmosphere, power, and bias voltage during the deposition.

As shown in fig. 6, step 4) is performed next, and the second electrode 103 is formed on the resistive memory layer 102.

In one embodiment, forming the second electrode 103 includes the steps of: n second

sub-electrode layers

1031, 1032, 1033 are grown layer by layer on the resistive memory layer 102 by a deposition method, and the proportion of N in each of the second

sub-electrode layers

1031, 1032, 1033 is controlled such that the proportion of N x in the N second

sub-electrode layers

1031, 1032, 1033 decreases layer by layer from the resistive memory layer 102 in a direction away from the resistive memory layer 102. Specifically, the proportion of N in each of the second

sub-electrode layers

1031, 1032, 1033 may be adjusted by controlling the ambient atmosphere, power and bias voltage during the deposition.

In another embodiment, forming the second electrode 104 includes: growing N second sub-electrode layers layer by layer on the resistive memory layer 102 by a deposition method, and controlling the proportion of N in each second sub-electrode layer so that the proportion x of N in N second sub-electrode layers is reduced layer by layer from the resistive memory layer 102 towards a direction away from the resistive memory layer 102; by performing an annealing process in an N atmosphere, N in the second sub-electrode layer is diffused, so that the N proportion x in the second electrode 104 decreases linearly from the resistive memory layer 102 toward a direction away from the resistive memory layer 102, and the device structure finally formed is as shown in fig. 11.

As shown in fig. 7, step 5) is performed next, and the second electrode 103 and the resistive memory layer 102 are patterned, specifically, the second electrode 103 and the resistive memory layer 102 may be etched using silicon nitride as a mask after patterning the silicon nitride by photolithography and etching by growing silicon nitride as a hard mask to form a desired pattern.

As shown in fig. 8, step 6) is performed, and sidewall structures 105 are formed on sidewalls of the first electrode 101, the resistive memory layer 102, and the second electrode 103. Specifically, the sidewall structure 105 may be formed by a deposition method, and then the silicon nitride hard mask described above is removed.

As shown in fig. 9, step 7) is performed next, and an interlayer dielectric layer 202 is formed on the second electrode 103. The interlayer dielectric layer 202 may be, for example, silicon dioxide or the like.

As shown in fig. 10, finally, step 8) is performed, and an electrode hole structure 107 exposing the second electrode 103 is formed in the interlayer dielectric layer 202; a metal electrode is formed in the electrode hole structure 107, and metal atoms in the metal electrode are M and the same as those in the second electrode 103 and the resistive memory layer 102.

In one embodiment, the electrode aperture structure 107 comprises a damascene structure.

Fig. 12 shows the cycle characteristics of a resistive random access memory device implemented in accordance with the present invention, and fig. 13 shows the cycle characteristics of a resistive random access memory device implemented in accordance with a conventional method. Wherein the dots are high resistance of the device, and the triangular dots are low resistance of the device. As can be seen from a comparison of fig. 12 and fig. 13, the resistive random access memory device implemented in fig. 12 has a more convergent high-low resistance value, and in 1000 cycle tests, the resistive random access memory device implemented in the present invention basically succeeds in cycling 1000 times, while the resistive random access memory device implemented in the conventional method in fig. 13 has a large number of cycle failures. Therefore, the service life and the durability of the device can be effectively improved, the holding capacity of the device is improved, and better device performance is obtained.

As described above, the resistive random access memory element, the memory device and the method of manufacturing the same of the present invention have the following advantageous effects:

According to the invention, the N proportion in the second electrode is controlled, so that the second electrode has conductivity, and meanwhile, the migration and diffusion of metal ions into the resistive memory layer are more controllable.

The preparation process can control the proportion of N in the second electrode according to different requirements, is convenient for adjusting the performance of the device, and has stronger controllability.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A resistive random access memory element, the resistive random access memory element comprising:

the first electrode, the resistance change storage layer and the second electrode are sequentially arranged;

and the material of the second electrode is MNx, wherein M is one of Ti, ta and Al, and x is more than or equal to 0 and less than or equal to 1.

2. The resistive random access memory element of claim 1, wherein: the second electrode MNx comprises N second sub-electrode layers, N is more than or equal to 2, and the proportion x of N in the N second sub-electrode layers is reduced layer by layer from the resistive memory layer towards the direction away from the resistive memory layer.

3. The resistive random access memory element of claim 2, wherein: the difference of the N proportion x in the two adjacent second sub-electrode layers is larger than or equal to 0.05.

4. The resistive random access memory element of claim 2, wherein: and in the N second sub-electrode layers, the thickness of the second sub-electrode layer with the largest N proportion x is less than or equal to 5 nanometers.

5. The resistive random access memory element of claim 2, wherein: the thickness of the N second sub-electrode layers increases with the decrease of the N proportion x.

6. The resistive random access memory element of claim 1, wherein: the N ratio x in the second electrode MNx decreases linearly from the resistive memory layer toward a direction away from the resistive memory layer.

7. The resistive random access memory element of claim 1, wherein: the N ratio x in the second electrode MNx is greater than or equal to 0.3 and less than or equal to the stoichiometric ratio of M and N.

8. The resistive random access memory element of claim 1, wherein: the resistive memory layer is made of MOy, and metal atoms in the resistive memory layer MOy are the same as metal atoms in the second electrode MNx, wherein M is selected from one of Ti, ta and Al, and y is more than or equal to 0 and less than or equal to 1.

9. The resistive random access memory element of claim 8, wherein: the metal atoms of the conductive channel of the resistive random access memory element are M, which are the same as the metal atoms in the second electrode MNx and the resistive memory layer MOy, wherein the metal atoms M migrate to the second electrode and form the conductive channel composed of the metal atoms M in the resistive memory layer, so that the resistive memory layer is converted into a low-resistance state, or/and the O in the resistive memory layer migrates to form the conductive channel formed by oxygen holes in the resistive memory layer, so that the resistive memory layer is converted into a low-resistance state.

10. The resistive random access memory element of claim 1, wherein: the material of the first electrode is an inert metal or a metal nitride, wherein the inert metal comprises one of W and Pt, and the metal nitride comprises one of TiN and TaN.

11. The resistive random access memory element of claim 1, wherein: and side wall structures are formed on the side walls of the first electrode, the resistance change storage layer and the second electrode.

12. The resistive random access memory element of claim 1, wherein: the resistive random access memory element further includes: an interlayer dielectric layer disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer, and the electrode hole structure comprises a Damascus structure; and the electrode hole structure is filled with a metal electrode, and metal atoms in the metal electrode are M and the same as metal atoms in the second electrode MNx.

13. A resistive random access memory device comprising an array of a plurality of resistive random access memory elements according to any one of claims 1 to 12.

14. A method of manufacturing a resistive random access memory element according to any one of claims 1 to 12, comprising the steps of:

and forming a first electrode, a resistive random access memory layer and a second electrode which are sequentially arranged, wherein the material of the second electrode is MNx, M is selected from one of Ti, ta and Al, and x is more than or equal to 0 and less than or equal to 1.

15. The method of manufacturing a resistive random access memory device according to claim 14, wherein: forming the second electrode includes:

and growing N layers of second sub-electrode layers layer by layer on the resistive random access memory layer by a deposition method, and reducing the N proportion x in the N second sub-electrode layers layer by layer from the resistive random access memory layer towards the direction away from the resistive random access memory layer by controlling the N proportion in each layer of the second sub-electrode layers.

16. The method of manufacturing a resistive random access memory device according to claim 14, wherein: forming the second electrode includes:

growing N layers of second sub-electrode layers layer by layer on the resistive random access memory layer by a deposition method, and controlling the proportion of N in each layer of second sub-electrode layers to enable the proportion x of N in N second sub-electrode layers to be reduced layer by layer from the resistive random access memory layer towards a direction away from the resistive random access memory layer;

and (3) performing an annealing process in an N atmosphere to diffuse N in the second sub-electrode layer, so that the proportion x of N in the second electrode MNx linearly decreases from the resistive memory layer towards a direction away from the resistive memory layer.

17. The method of manufacturing a resistive random access memory device according to claim 15 or 16, wherein: the proportion of N in each second sub-electrode layer is regulated by controlling the ambient atmosphere, power and bias voltage in the deposition process.

18. The method of manufacturing a resistive random access memory device according to claim 14, wherein: the method also comprises the steps of: and forming a side wall structure on the side walls of the first electrode, the resistive random access memory layer and the second electrode.

19. The method of manufacturing a resistive random access memory device according to claim 14, wherein: the method also comprises the steps of:

forming an interlayer dielectric layer on the second electrode;

forming an electrode hole structure exposing the second electrode in the interlayer dielectric layer, wherein the electrode hole structure comprises a Damascus structure;

and forming a metal electrode in the electrode hole structure, wherein metal atoms in the metal electrode are M and the same as those in the second electrode MNx and the resistive random access memory layer MOy.

20. The method of manufacturing a resistive random access memory device according to claim 14, wherein: forming the resistive memory layer includes:

and growing a plurality of MOy material layers layer by a deposition method, and regulating the proportion of O in each MOy material layer by controlling the ambient atmosphere, power and bias voltage in the deposition process.