CN112596578A - Clock monitoring circuit and monitoring method - Google Patents
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Abstract
Disclosed are a clock monitoring circuit and a monitoring method, the clock monitoring circuit including: the clock monitoring system comprises a test clock module, a reference clock module and a clock monitoring module; the clock monitoring module is used for generating a test stopping signal according to counting monitoring results of a current reference clock signal and a current test clock signal; the test clock module is used for responding to the test stopping signal and selecting a clock signal to be tested from at least one test clock signal to update the current test clock signal; the reference clock module is configured to determine, in response to the test stop signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal among the at least one reference clock signal to update the current reference clock signal. According to the technical scheme provided by the disclosure, under the condition that the central processing unit is not involved, switching among the test clock signals can be realized, the performance of the central processing unit is improved, the circuit design is simple, and the power consumption is low.
Description
Technical Field
The present disclosure relates to the field of electronic circuit technologies, and more particularly, to a clock monitoring circuit and a monitoring method.
Background
When the integrated circuit chip works, at least one clock signal is needed to determine the cooperative work of each component in the integrated circuit chip, and if the clock has a problem, the integrated circuit chip cannot work normally. At present, when at least one clock signal of an integrated circuit chip is monitored, each clock signal is generally monitored independently by using an independent monitoring circuit under the control of a central processing unit, and the circuit design is complex and the power consumption is large.
Disclosure of Invention
In order to solve the above technical problem, embodiments of the present disclosure provide a clock monitoring circuit and a monitoring method, where switching between test clock signals can be implemented without intervention of a central processing unit, so as to avoid occupation of resources of the central processing unit, improve performance of the central processing unit, and have a simple circuit design and low power consumption.
According to a first aspect of the present disclosure, there is provided a clock monitoring circuit comprising: the clock monitoring system comprises a test clock module, a reference clock module and a clock monitoring module;
the clock monitoring module is used for generating a test stopping signal according to counting monitoring results of a current reference clock signal and a current test clock signal;
the test clock module is used for responding to the test stopping signal and selecting a clock signal to be tested from at least one test clock signal to update the current test clock signal;
the reference clock module is configured to determine, in response to the test stop signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal among the at least one reference clock signal to update the current reference clock signal.
According to a second aspect of the present disclosure, there is provided a clock monitoring method, comprising:
generating a test stopping signal by using a clock monitoring module according to counting monitoring results of a current reference clock signal and a current test clock signal;
responding to the test stopping signal by using a test clock module, and selecting a clock signal to be tested from at least one test clock signal to update the current test clock signal;
and responding to the test stopping signal by using a reference clock module, and determining a clock signal to be referred corresponding to the clock signal to be tested in at least one parameter clock signal so as to update the current reference clock signal.
Compared with the prior art, the clock monitoring circuit and the monitoring method provided by the disclosure at least have the following beneficial effects:
on one hand, in the embodiment, the clock monitoring module generates the test stopping signal according to the counting monitoring results of the current reference clock signal and the current test clock signal; the test clock module and the reference clock module respectively respond to the test stopping signal and respectively update the current test clock signal and the current reference clock signal, so that the clock monitoring module enters the counting of the updated current test clock signal and the current reference clock signal, the automatic switching of a plurality of test clock signals and a plurality of reference clock signals is realized, a monitoring circuit does not need to be independently arranged on each clock, the circuit design is simple, and the power consumption is reduced.
On the other hand, the switching between the test clock signal and the reference clock signal is based on the test stopping signal generated by the clock monitoring module, and the switching between the test clock signals can be realized under the condition that the central processing unit is not involved, thereby avoiding occupying the resources of the central processing unit and improving the performance of the central processing unit.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.
FIG. 1 is a first schematic diagram of a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
FIG. 2 is a first schematic diagram illustrating a structure of a clock monitoring module in a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a test clock module in a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
FIG. 4 is a first schematic diagram illustrating a structure of a reference clock module in a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a reference clock module in a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a clock monitoring module in a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
FIG. 7 is a second schematic diagram of a clock monitoring circuit according to an exemplary embodiment of the present disclosure;
FIG. 8 is a first flowchart illustrating a clock monitoring method according to an exemplary embodiment of the present disclosure;
FIG. 9 is a flowchart illustrating a step 81 in a clock monitoring method according to an exemplary embodiment of the disclosure;
fig. 10 is a flowchart illustrating a clock monitoring method according to an exemplary embodiment of the present disclosure;
FIG. 11 is a flowchart illustrating a step 82 of a clock monitoring method according to an exemplary embodiment of the present disclosure;
FIG. 12 is a flowchart illustrating a step 83 in a clock monitoring method according to an exemplary embodiment of the disclosure;
fig. 13 is a third schematic flowchart of a clock monitoring method according to an exemplary embodiment of the present disclosure;
FIG. 14 is a fourth flowchart illustrating a clock monitoring method according to an exemplary embodiment of the disclosure;
fig. 15 is a fifth flowchart illustrating a clock monitoring method according to an exemplary embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.
Summary of the application
When the integrated circuit chip works, at least one clock signal is needed to determine the cooperative work of each component in the integrated circuit chip, and if the clock has a problem, the integrated circuit chip cannot work normally. At present, when at least one clock signal of an integrated circuit chip is monitored, each clock signal is generally monitored independently by using an independent monitoring circuit under the control of a central processing unit, and the circuit design is complex and the power consumption is large.
In the embodiment, the clock monitoring module generates the test stopping signal according to the counting monitoring results of the current reference clock signal and the current test clock signal; the test clock module and the reference clock module respectively respond to the test stopping signal and respectively update the current test clock signal and the current reference clock signal, so that the clock monitoring module enters the counting of the updated current test clock signal and the current reference clock signal, the automatic switching of a plurality of test clock signals and a plurality of reference clock signals is realized, a monitoring circuit does not need to be independently arranged on each clock, the circuit design is simple, and the power consumption is reduced. Furthermore, the switching between the test clock signal and the reference clock signal is based on the stop test signal generated by the clock monitoring module, and the switching between the test clock signals can be realized under the condition that the central processing unit is not involved, thereby avoiding occupying the resources of the central processing unit and improving the performance of the central processing unit.
Exemplary Circuit
Fig. 1 is a schematic structural diagram of a clock monitoring circuit according to an exemplary embodiment of the present disclosure, which includes at least the following modules:
the clock monitoring module 11 is configured to generate a test stop signal according to counting monitoring results of the current reference clock signal and the current test clock signal.
In one embodiment, the current test clock signal refers to the clock signal being monitored at the current time.
In one embodiment, the current reference clock signal refers to a standard clock signal for providing timing corresponding to the test clock signal at the current time. The clock monitoring module 11 performs count monitoring on the current reference clock signal and the current test clock signal respectively, and generates a stop test signal according to a count monitoring result.
The test clock module 12 is configured to select a clock signal to be tested from at least one test clock signal in response to the test stop signal to update the current test clock signal.
In one embodiment, at least one test clock signal refers to one or more clock signals that need to be monitored.
In one embodiment, the clock signal to be tested refers to the next monitored test clock signal selected from the at least one test clock signal. After the clock signal to be tested is determined, the current test clock signal is updated by using the clock signal to be tested, so that the clock monitoring module 11 enters into the monitoring work of the updated current test clock signal.
The reference clock module 13 is configured to determine, in response to the test stop signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal among the at least one reference clock signal to update the current reference clock signal.
In one embodiment, the at least one reference clock signal refers to a standard clock signal that is used to provide timing relative to the at least one test clock signal.
In one embodiment, the clock signal to be referenced refers to a reference clock signal corresponding to the clock to be tested, which is selected from at least one reference clock signal.
In an embodiment, after determining the clock signal to be tested, the reference clock module selects a clock signal to be referenced corresponding to the clock signal to be tested, and updates the current reference clock signal by using the clock signal to be referenced, so that the clock monitoring module monitors the updated current test clock signal by using the updated current reference clock signal.
The clock monitoring circuit provided by the embodiment at least has the following beneficial effects:
on one hand, in the embodiment, the clock monitoring module generates the test stopping signal according to the counting monitoring results of the current reference clock signal and the current test clock signal; the test clock module and the reference clock module respectively respond to the test stopping signal and respectively update the current test clock signal and the current reference clock signal, so that the clock monitoring module enters the counting of the updated current test clock signal and the current reference clock signal, the automatic switching of a plurality of test clock signals and a plurality of reference clock signals is realized, a monitoring circuit does not need to be independently arranged on each clock, the circuit design is simple, and the power consumption is reduced.
On the other hand, the switching between the test clock signal and the reference clock signal is realized according to the situation that the test stopping signal generated by the clock monitoring module is not inserted into the central processing unit, so that the resources of the central processing unit are avoided being occupied, and the performance of the central processing unit is improved.
Fig. 2 shows a schematic structural diagram of the clock monitoring module 11 in the embodiment shown in fig. 1, which is specifically shown as follows:
the clock monitoring module 11 comprises a reference clock counter 111 and a test clock counter 112;
the reference clock counter 111 is configured to generate a stop test signal when a count monitoring result of the current reference clock signal meets a first preset condition.
In one embodiment, the count monitoring result of the current reference clock signal may be presented by a count value obtained when the reference clock signal counter stops counting.
In one embodiment, the first predetermined condition is that a set value corresponding to the current reference clock signal is reached, wherein the set value can be set according to a time required for the integrated circuit chip component to perform a certain operation. Specifically, the set duration is predetermined, and the set value is determined according to the pulse frequency of the reference clock signal, for example, the set value may be 100, and when the count value of the count monitoring result of the current reference clock signal is 100, the stop test signal is generated.
The test clock counter 112 is configured to determine a count monitoring result of the current test clock signal in response to the stop test signal. In one possible implementation, in response to the stop test signal, the test clock timer stops counting, and the count monitoring result of the current test clock signal shows a count value of 98, i.e., the count monitoring result is presented as a count value. In another possible implementation manner, the count value obtained when the test clock counter stops counting is converted, and a frequency value corresponding to the count value, such as 350MHz, is determined, that is, the count monitoring result is presented at the frequency corresponding to the count value.
In the above embodiment, the reference clock counter 111 is used to perform counting monitoring on the current reference clock signal, when the counting monitoring result of the current reference clock signal reaches the preset value corresponding to the current reference clock signal, the counting is stopped and the test stop signal is generated, and the test clock counter 112 is used to stop counting the current test clock signal in response to the test stop signal, so as to obtain the counting monitoring result of the current test clock signal. Thus, the parameter clock counter 111 and the test clock counter 112 are used to complete the accurate monitoring of the current test clock signal.
It should be noted that, because there may be a plurality of test clock signals with different pulse frequencies in the integrated circuit chip, when the current test clock signal changes, for example, the test clock signal with the pulse frequency of 350MHz is converted into the test clock signal with the pulse frequency of 400MHz, at this time, the reference clock signal is converted from 1 to 2, and the pulse frequencies and the corresponding setting durations of the reference clock signals 1 and 2 are different, so the respective setting values of the reference clock signal 1 and the reference clock signal 2 are different, for example, the setting value of the reference clock signal 1 is 100 and the setting value of the reference clock signal 2 is 120, so different test clock signals may correspond to different reference clock signals, and different reference clock signals may correspond to different setting values. The current reference clock signal is changed and the set value in the first preset condition is changed when the current test clock signal is changed, so that monitoring of each test clock signal can be achieved by using the reference clock counter 111 and the test clock counter 112, providing a possibility for the test clock counters to use the same monitoring circuit.
In order to enable the test clock module 12 to accurately select the clock signal to be tested from the at least one test clock signal, there are two possible implementations:
in the first implementation manner, if the test stopping signal carries the clock selection logic, the test clock module 12 is configured to respond to the test stopping signal and select the clock signal to be tested from the at least one test clock signal according to the clock selection logic carried by the test stopping signal to update the current test clock signal; the reference clock module 13 is configured to respond to the test stopping signal, and determine, according to a clock selection logic carried by the test stopping signal, a to-be-referenced clock signal corresponding to the to-be-referenced clock signal among the at least one parameter clock signal to update the current reference clock signal.
In the above embodiment, the stop test signal is used to carry the clock selection logic, so as to avoid using the central processing unit to control the test sequence of each test clock signal, and under the condition that the central processing unit is not involved, the test clock signals can be switched, thereby avoiding occupying the resources of the central processing unit and improving the performance of the central processing unit.
In a second implementation manner, as shown in fig. 3, the test clock module 12 includes: a first storage unit 121 and a first selection unit 122;
the first storage unit 121 is configured to store the at least one test clock signal;
the first selecting unit 122 is configured to respond to the test stopping signal, read the at least one test clock signal stored in the first storage unit 121, and select a clock signal to be tested from the at least one test clock signal according to a preset selecting manner to update the current test clock signal.
In the above embodiment, the test clock module 12 may include a first storage unit 121 and a first selection unit 122, the first storage unit 121 is used to store one or more test clock signals, and the first selection unit 122 is used to respond to the stop test signal and select the clock signal to be tested. After the first selection unit 122 receives the stop test signal, the first selection unit directly selects the clock signal to be tested from the one or more test clock signals according to the set selection mode, for example, the plurality of test clock signals are sorted in advance, the selection mode is set to be sequential selection, when the clock signal to be tested selected last time is the second test clock signal, the third test clock signal should be selected this time as the clock signal to be tested, and under the condition that the central processing unit is not involved, switching among the test clock signals can be realized, so that resources of the central processing unit are avoided being occupied, and performance of the central processing unit is improved. Further, after the clock signal to be tested is selected, the current test clock signal is updated by using the clock signal to be tested, so that the clock monitoring module 11 counts the updated current test clock signal. Specifically, the test clock signal and the reference clock signal may be analog signals or digital signals, that is, the clock monitoring circuit may be adapted to various types of pulse signals, and has high adaptability.
In one possible implementation, the correspondence of at least one test clock signal and at least one reference clock signal is set, e.g. there are 3 test clock signals and 3 reference clock signals, i.e., test clock signal a, test clock signal B and test clock signal C, reference clock signal 1 and reference clock signal 2 and reference clock signal 3, a correspondence relationship is determined in advance, if the test clock signal a corresponds to the reference clock signal 1, the test clock signal B corresponds to the reference clock signal 2, the test clock signal C corresponds to the reference clock signal 3, after the clock signal to be tested is determined, the clock signal to be referenced can be selected from at least one reference clock signal according to the set corresponding relation, if the clock signal to be tested is determined to be the test clock signal B, then, according to the determined corresponding relationship, it can be determined that the clock signal to be referred is the reference clock signal 2.
In another possible implementation, as shown in fig. 4, the reference clock module 13 includes: a second storage unit 131 and a second selection unit 132;
the second storage unit 131 is configured to store the at least one reference clock signal;
the second selecting unit 132 is configured to respond to the test stopping signal, read the at least one reference clock signal stored in the second storage unit 132, and determine, according to a preset selecting manner, a to-be-referenced clock signal corresponding to the to-be-tested clock signal from the at least one parameter clock signal to update the current reference clock signal.
In the above implementation, the reference clock module 13 may include a second storage unit 131 and a second selection unit 132, the second storage unit 131 is used to store one or more reference clock signals, and the second selection unit 132 is used to respond to the stop test signal and select the clock signal to be referenced. The selection mode is preset, after the second selection unit 132 receives the stop test signal, the clock signal to be referenced is directly selected from one or more reference clock signals according to the set selection mode, and under the condition that the central processing unit is not involved, switching can be realized among the test clock signals, so that resources of the central processing unit are avoided being occupied, the performance of the central processing unit is improved, meanwhile, monitoring on the plurality of test clock signals can be realized by using one monitoring circuit, the design of the monitoring circuit is simple, and the power consumption can be reduced.
Specifically, as shown in fig. 5, the reference clock module 13 further includes a frequency divider 133; the frequency divider 133 is configured to perform frequency division processing on the clock signal to be referred to, and update the current reference clock signal with the clock signal to be referred to after the frequency division processing. In a possible case where the pulse frequency of the reference clock signal and the pulse frequency of the test clock signal do not match, the frequency divider 133 may be used to divide the selected clock signal to be referenced so that the pulse frequency of the reference clock signal matches the pulse frequency of the test clock signal. Specifically, if the pulse frequency of the test clock signal is 300MHz and the pulse frequency of the reference clock signal is 15MHz, if the reference clock signal is used to provide accurate timing for the test clock signal, the test clock signal and the reference clock signal need to be at the same speed, or the pulse frequency of the reference clock signal is much higher than the pulse frequency of the test clock signal, so that when the pulse frequency of the reference clock signal is lower than the pulse frequency of the test clock, the pulse frequency of the reference clock signal needs to be divided to obtain the reference clock signal at least at the same speed as the test clock signal, and therefore the frequency divider 133 can be used to better monitor the test clock signal by using the reference clock signal.
Fig. 6 shows a schematic structural diagram of the clock monitoring module 11 in the embodiment shown in fig. 1, which is specifically shown as follows:
the clock monitoring module 11 includes a sleep unit 113;
the sleep unit 113 is configured to generate a sleep signal according to the update times and preset times of the current test clock signal or the current reference clock signal; the clock monitoring module 11 performs a sleep state based on the sleep signal.
In the above embodiment, the number of times of updating the current test clock signal is recorded, the number of times of updating is increased by one after the current test clock signal is updated by selecting the clock signal to be tested each time, when the number of times of updating reaches the preset number of times, it is proved that monitoring of each test clock signal is completed, at this time, a sleep signal can be generated, the clock monitoring module 11 enters a sleep state based on the sleep signal, that is, when there is no current test clock signal, the clock monitoring module stops working without being in a working state, and the service life of the clock monitoring module 11 is increased while power consumption is reduced.
After the clock monitoring module 11 enters the sleep state, when the clock monitoring module 11 needs to be in the working state again, the clock monitoring module 11 needs to be provided with a wakeup unit 114, as shown in fig. 6, the clock monitoring module 11 further includes the wakeup unit 114; the wake-up unit 114 is configured to generate a wake-up signal and the test stop signal according to the sleep time of the clock monitoring module 11 and a preset sleep time; the wake-up signal is used to enable the clock monitoring module 11 to end the sleep state.
In the above embodiment, the wake-up unit 114 records the sleep time when the clock monitoring module 11 enters the sleep state, and when the recorded sleep time reaches the preset sleep time, the wake-up unit 114 generates a wake-up signal and a test stop signal, the clock monitoring module 11 ends the sleep state based on the wake-up signal and returns to the working state from the sleep state, and the test clock module 12 selects the clock signal to be tested based on the test stop signal and enables the reference clock module 13 to select the clock signal to be referred, i.e., to perform the next cycle of work.
Specifically, the wake-up unit may be a counter, when the clock monitoring module 11 enters a sleep state, the reference clock module 13 provides a sleep clock signal, the wake-up unit 114 counts the sleep clock signal, and when the count value of the sleep clock signal reaches a sleep preset value, the sleep time of the clock monitoring module 11 reaches a preset sleep time.
In particular, since the wake-up unit 114 generates the stop test signal, after the sleep unit 113 of the clock monitoring module 11 generates the sleep signal, not only the clock monitoring module 11 can enter the sleep state, but also the test clock module 12 and the reference clock module 13 can both enter the sleep state, and both the test clock module 12 and the reference clock module 13 can end the sleep state based on the stop test signal generated by the wake-up unit 114 and enter the working state. Therefore, the clock monitoring module 11 can be waken up at a required moment by using the wakening unit 114, and certainly, the test clock module 12 and the reference clock module 13 can also be waken up, so that the automatic sleep of the clock monitoring circuit is realized, the switching between the sleep state and the working state is automatically performed, the clock monitoring circuit is prevented from being always in the working state, the power consumption of the clock monitoring module 11, the test clock module 12 and the reference clock module 13 can be reduced, and the working duration of the clock monitoring circuit is prolonged.
FIG. 7 shows another schematic diagram of the clock monitoring circuit, which further includes an alarm module 14; the alarm module 14 is configured to generate an alarm signal according to the counting monitoring result of the current test clock signal and a second preset condition.
In the above embodiment, the alarm module 14 is provided for the clock monitoring circuit, so that when the counting monitoring result of the current test clock signal does not meet the second preset condition, an alarm signal is generated, so that the relevant staff can know the situation as soon as possible and take measures to restore the clock monitoring circuit to normal as soon as possible. In a possible implementation manner, the second preset condition may be that the second preset condition is smaller than an upper limit value of the current test clock signal or larger than a lower limit value of the current test clock signal, where the upper limit value may be a highest count value of the current test clock signal in a normal operating state that is set in advance according to experience, and the lower limit value may be a lowest count value of the current test clock signal in the normal operating state, for example, it is determined that the upper limit value of the current test clock signal a is 102 and the lower limit value is 97, if the count monitoring result of the current test clock signal a shows that the count value is 100, the current test clock signal a is in the normal operating state, and if the count monitoring result of the current test clock signal a shows that the count value is 105, the current test clock signal B is in the abnormal operating state, and an alarm needs to be performed. In another possible implementation manner, if the pulse frequencies of the current test clock signal and the current reference clock signal are completely the same, the second preset condition may be that an absolute value of a difference between the count monitoring result of the current reference clock signal and the current reference clock signal is smaller than a set amplitude value, for example, the set amplitude value is determined to be 3, if an absolute value of a difference between a count value of the current reference clock signal and a count value of the current test clock signal is 2, the current test clock signal is in a normal operating state, and if an absolute value of a difference between a count value of the current reference clock signal and a count value of the current test clock signal is 5, the current test clock signal is in an abnormal operating state, and an alarm needs to be performed. Therefore, when the counting monitoring result of the current test clock signal does not accord with the second preset condition, the clock monitoring circuit is proved to be in an abnormal working state, an alarm needs to be given, and the situation that the integrated circuit chip cannot work completely is avoided.
Exemplary method
Fig. 8 shows a clock monitoring method provided in this embodiment, which specifically includes the following steps:
and step 83, responding to the test stopping signal by using a reference clock module, and determining a clock signal to be referenced corresponding to the clock signal to be tested in at least one parameter clock signal so as to update the current reference clock signal.
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
Fig. 9 is a schematic flow chart illustrating the generation of the stop test signal by the clock monitoring module according to the count monitoring results of the current reference clock signal and the current test clock signal in the embodiment shown in fig. 8.
As shown in fig. 9, based on the embodiment shown in fig. 8, in an exemplary embodiment of the present application, the step 81 of generating the stop test signal by using the clock monitoring module according to the counting monitoring results of the current reference clock signal and the current test clock signal may specifically include the following steps:
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
In one possible case, the stop test signal carries clock selection logic; then, as shown in fig. 10, step 82 comprises step 82 a; step 83 includes step 83 a;
step 82a, responding to the test stopping signal by using a test clock module, and selecting a clock signal to be tested from at least one test clock signal according to clock selection logic carried by the test stopping signal to update the current test clock signal;
step 83a includes responding to the test stopping signal by using a reference clock module, and determining a clock signal to be referenced corresponding to the clock signal to be tested from among at least one parameter clock signal according to a clock selection logic carried by the test stopping signal to update the current reference clock signal.
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
FIG. 11 is a flow chart illustrating the process of selecting the clock signal to be tested from the at least one test clock signal to update the current test clock signal in response to the stop test signal by the test clock module in the embodiment shown in FIG. 8.
As shown in fig. 11, based on the embodiment shown in fig. 8, in an exemplary embodiment of the present application, the step 82 of using the test clock module to respond to the stop test signal and selecting a clock signal to be tested from at least one test clock signal to update the current test clock signal may specifically include the following steps:
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
Fig. 12 is a schematic flow chart illustrating that, in the embodiment shown in fig. 11, the reference clock module is used to determine, in response to the stop test signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal among the at least one parameter clock signal to update the current reference clock signal.
As shown in fig. 12, based on the embodiment shown in fig. 11, in an exemplary embodiment of the present application, step 83 is to determine, by using the reference clock module to respond to the stop test signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal in at least one parameter clock signal to update the current reference clock signal, which may specifically include the following steps:
a step 831 of storing the at least one reference clock signal by using a second storage unit of the reference clock module;
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
Fig. 13 is a schematic flow chart illustrating that, in the embodiment shown in fig. 8, a reference clock module is used to determine, in response to the stop test signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal among the at least one parameter clock signal to update the current reference clock signal.
As shown in fig. 13, based on the embodiment shown in fig. 11, in an exemplary embodiment of the present application, step 83 is to determine, by using the reference clock module to respond to the stop test signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal in at least one parameter clock signal to update the current reference clock signal, which may specifically include: a step 83 b;
and step 83b, responding to the test stopping signal by using a reference clock module, determining the clock signal to be tested in at least one parameter clock signal, performing frequency division processing on the clock signal to be referred by using a frequency divider of the reference clock signal, and updating the current reference clock signal by using the clock signal to be referred after the frequency division processing.
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
Fig. 14 shows a schematic flowchart that the clock monitoring method may further include in the embodiment shown in fig. 8.
As shown in fig. 14, on the basis of the embodiment shown in fig. 8, in an exemplary embodiment of the present application, the method may further include the following steps:
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
Fig. 15 shows a schematic flowchart that the clock monitoring method may further include in the embodiment shown in fig. 8.
As shown in fig. 15, on the basis of the embodiment shown in fig. 8, in an exemplary embodiment of the present application, the method may further include the following steps:
and 86, generating an alarm signal by using an alarm module according to the counting monitoring result of the current test clock signal and a second preset condition.
Specifically, this embodiment is a method embodiment corresponding to the above device embodiment, and specific effects are referred to the above device embodiment, which is not described in detail herein.
The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.
The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (10)
1. A clock monitoring circuit, comprising: the clock monitoring system comprises a test clock module, a reference clock module and a clock monitoring module;
the clock monitoring module is used for generating a test stopping signal according to counting monitoring results of a current reference clock signal and a current test clock signal;
the test clock module is used for responding to the test stopping signal and selecting a clock signal to be tested from at least one test clock signal to update the current test clock signal;
the reference clock module is configured to determine, in response to the test stop signal, a to-be-referenced clock signal corresponding to the to-be-tested clock signal among the at least one reference clock signal to update the current reference clock signal.
2. The clock monitoring circuit of claim 1, wherein the clock monitoring module comprises a reference clock counter and a test clock counter;
the reference clock counter is used for generating a test stopping signal when the counting monitoring result of the current reference clock signal meets a first preset condition;
and the test clock counter is used for responding to the stop test signal and determining the counting monitoring result of the current test clock signal.
3. The clock monitoring circuit of claim 1, wherein the stop test signal carries clock selection logic;
the test clock module is configured to respond to the test stopping signal and select a clock signal to be tested from at least one test clock signal according to a clock selection logic carried by the test stopping signal to update the current test clock signal;
and the reference clock module is used for responding to the test stopping signal and determining a clock signal to be referred corresponding to the clock signal to be tested in at least one parameter clock signal according to clock selection logic carried by the test stopping signal so as to update the current reference clock signal.
4. The clock monitoring circuit of claim 1, wherein the test clock module comprises: the device comprises a first storage unit and a first selection unit;
the first storage unit is used for storing the at least one test clock signal;
the first selecting unit is configured to read the at least one test clock signal stored in the first storage unit in response to the test stopping signal, and select a clock signal to be tested from the at least one test clock signal according to a preset selecting manner to update the current test clock signal.
5. The clock monitoring circuit of claim 4, wherein the reference clock module comprises: the second storage unit and the second selection unit;
the second storage unit is used for storing the at least one reference clock signal;
the second selecting unit is configured to read the at least one reference clock signal stored in the second storage unit in response to the test stopping signal, and determine a to-be-referenced clock signal corresponding to the to-be-tested clock signal from the at least one parameter clock signal according to a preset selecting manner to update the current reference clock signal.
6. The clock monitoring circuit of claim 1, wherein the reference clock module further comprises, a frequency divider;
the frequency divider is used for carrying out frequency division processing on the clock signal to be referred, and updating the current reference clock signal by using the clock signal to be referred after the frequency division processing.
7. The clock monitoring circuit of claim 1, wherein the clock monitoring module comprises, a sleep unit;
the sleep unit is used for generating a sleep signal according to the updating times and the preset times of the current test clock signal or the current reference clock signal; the sleep signal is used for enabling the clock monitoring module to be in a sleep state.
8. The clock monitoring circuit of claim 7, wherein the clock monitoring module further comprises, a wakeup unit;
the wake-up unit is used for generating a wake-up signal and the test stopping signal according to the sleep time of the clock monitoring module and the preset sleep time; the wake-up signal is used for enabling the clock monitoring module to end the sleep state.
9. The clock monitoring circuit of any of claims 1-8, wherein the clock monitoring circuit further comprises an alarm module;
and the alarm module is used for generating an alarm signal according to the counting monitoring result of the current test clock signal and a second preset condition.
10. A clock monitoring method, comprising:
generating a test stopping signal by using a clock monitoring module according to counting monitoring results of a current reference clock signal and a current test clock signal;
responding to the test stopping signal by using a test clock module, and selecting a clock signal to be tested from at least one test clock signal to update the current test clock signal;
and responding to the test stopping signal by using a reference clock module, and determining a clock signal to be referred corresponding to the clock signal to be tested in at least one parameter clock signal so as to update the current reference clock signal.
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| CN202011442043.7A CN112596578A (en) | 2020-12-08 | 2020-12-08 | Clock monitoring circuit and monitoring method |
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| CN202011442043.7A CN112596578A (en) | 2020-12-08 | 2020-12-08 | Clock monitoring circuit and monitoring method |
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