CN112582444A - Three-terminal resistive random access memory capable of inhibiting crosstalk current and preparation method thereof - Google Patents
Three-terminal resistive random access memory capable of inhibiting crosstalk current and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- G—PHYSICS
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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- H10N70/253—Multistable switching devices, e.g. memristors having three or more terminals, e.g. transistor-like devices
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Abstract
The invention provides a three-terminal resistive random access memory capable of inhibiting crosstalk current and a preparation method thereof. The base electrode, the set electrode and the reset electrode are used for setting, resetting and data output of the resistive random access memory device. The resistance change medium can form a conductive channel in a setting mode, and a device is changed from a high resistance state to a low resistance state; the conducting channel is disconnected in a reset mode, and the device is changed from a low-resistance state to a high-resistance state; the device state is read out in the output mode. The diode can be a PN junction diode or a Schottky diode, and the problem of crosstalk of the cross array structure of the resistive random access memory can be solved by utilizing the rectifying characteristic of the diode. The insulating medium limits current to be excessive in a set operation and suppresses crosstalk current in a read operation.
Description
Technical Field
The invention relates to a three-terminal resistive random access memory device capable of inhibiting crosstalk current, and belongs to the technical field of electronic circuit device preparation.
Background
The resistive random access memory realizes data storage by utilizing two or more different resistance states which are shown by certain thin film materials under the action of an external electric field. Resistance switching mechanisms of resistive random access memories are various, with electrochemical metallization (ECM) and valence-change mechanism (VCM) being the most common. The resistive random access memory has great potential in the fields of nonvolatile storage, memory calculation, nerve morphology calculation and the like. Serious crosstalk problems can exist in large-scale arrays of the resistive random access memory, and the current methods for solving the crosstalk problems include 1D1R, 1T1R, 1S1R and the like.
Wherein in the 1D1R device, the diode acts as a simple two-terminal device that will turn off when a reverse voltage is applied. 1D1R refers to a diode and a resistive random access memory connected in series as a unit. When reading data, the crosstalk current is suppressed by passing through a diode or an insulating medium in the reverse direction. However, the 1D1R has a problem that it is effective for a unipolar resistive random access memory, and when a bipolar resistive random access memory is connected in series with a diode, the bipolar resistive random access memory is difficult to reset because a reverse current of the diode is small. Therefore, how to design the structure of the resistive random access memory to solve the crosstalk problem is an important issue.
Disclosure of Invention
The technical problem is as follows: the invention aims to provide a three-terminal resistive random access memory device capable of suppressing crosstalk current, which can be used for suppressing the crosstalk current in a resistive random access memory cross array.
The technical scheme is as follows: the three-terminal resistive random access memory capable of inhibiting crosstalk current comprises a set electrode, a base electrode, a reset electrode, a resistive medium, an insulating medium, a first semiconductor doping area, a second semiconductor doping area and a substrate; structurally, a substrate is used as a base, a first semiconductor doping region and a second semiconductor doping region are embedded in the upper surface of the substrate, an insulating medium is located on the upper surfaces of the substrate, the first semiconductor doping region and the second semiconductor doping region, a set electrode is located above the first semiconductor doping region on the upper surface of the insulating medium, a resistance change medium penetrates through the insulating medium and is located above the first semiconductor doping region, a base electrode is arranged on the resistance change medium, and a reset electrode penetrates through the insulating medium and is located on the second semiconductor doping region; the set electrode, the base electrode and the reset electrode are used for setting, resetting and data output of the resistive random access memory device.
A transition electrode can be arranged on the first semiconductor doping area; when the transition electrode exists, the transition electrode is positioned below the resistance change medium, namely between the first semiconductor doping region and the resistance change medium, or the transition electrode is positioned below the resistance change medium and the insulating medium and between the first semiconductor doping region and the resistance change medium and between the first semiconductor doping region and the insulating medium.
The diode formed by the first semiconductor doping region and the second semiconductor doping region is a PN junction diode, the diode formed by the reset electrode and the first semiconductor doping region is a schottky diode, and the directions of the diodes include but are not limited to: perpendicular to the substrate, parallel to the substrate.
The base electrode, the set electrode, the reset electrode and the transition electrode are all made of conductive materials; the resistance change medium is a material with resistance change property; the insulating medium is a low conductivity material.
The conductive material comprises: copper, gold, silver, platinum, titanium nitride, aluminum, tungsten, tantalum nitride.
The material with the resistance change property comprises a ferroelectric polarization material, a phase change material, a magnetic tunneling resistance change material or an oxidation reduction resistance change material.
The ferroelectric polarization material, the phase change material, the magnetic tunneling resistance change material or the oxidation reduction resistance change material comprises zirconium oxide, zinc oxide, titanium oxide, hafnium oxide, aluminum oxide, tantalum oxide, manganese oxide, silicon oxide or silver sulfide.
The low-conductivity material comprises silicon oxide, hafnium oxide, zirconium oxide, tantalum oxide or titanium oxide.
The preparation method of the three-terminal resistive random access memory capable of inhibiting crosstalk current comprises the following steps: doping a Si substrate to form a first semiconductor doping region and a second semiconductor doping region PN junction diode; then growing an insulating medium layer on the substrate; patterning a resistance change medium area at one end of the PN junction by photoetching and etching the insulating medium, and forming a resistance change medium in the area; then, patterning a reset electrode area on the other end of the PN junction by photoetching and etching an insulating medium, and depositing a reset electrode material in the reset electrode area; and then forming a base electrode above the resistance change medium, and forming a set electrode above the insulating medium at one end of the PN junction, which is in contact with the resistance change medium.
The working process of the three-terminal resistive random access memory capable of inhibiting crosstalk current is as follows: the setting operation of the device is realized by applying bias voltages on the base electrode and the setting electrode; applying bias voltage to the base electrode and the reset electrode to realize the reset and read operation of the device; setting operation refers to the fact that the resistive switching medium layer is changed from a high resistance state to a low resistance state; the reset operation refers to the change of the resistive medium layer from a low resistance state to a high resistance state; the read operation refers to reading the resistance state of the device.
The resistance change medium can form a conductive channel in a setting mode, and a device is changed from a high resistance state to a low resistance state; the conducting channel is disconnected in a reset mode, and the device is changed from a low-resistance state to a high-resistance state; the device state is read out in the output mode. The diode can be a PN junction diode or a Schottky diode, and the problem of crosstalk of a cross array structure of the resistance change resistor can be solved by utilizing the rectification characteristic of the diode. The insulating medium limits current to be excessive in a set operation and suppresses crosstalk current in a read operation.
The cross array structure (fig. 8) is wired in the following way: the base line (BaseLine) is connected with the base electrode, the set line (SetLine) is connected with the set electrode, and the reset line (ResetLine) is connected with the reset electrode. Taking the unit selected by the base line 1, the set line 1 and the reset line 1 as an example, the operation method is as follows: when setting, base line 1 is connected with 0 potential, and bit line 1 is connected with set voltage VsetAll the other wires are connected with V set2; secondly, when resetting, the base line 1 is connected with 0 potential, and the reset line 1 is connected with a reset voltage VresetAll the other wires are connected with V reset2; ③ when reading, the base line 1 is connected with 0 potential, the reset line 1 is connected with the reading voltage VreadAll the other wires are connected with Vread/2。
In the cross array structure, the read operation can be performed by reading more than one timeEach cell stores data. The operation method comprises the following steps: a selected one of the reset lines VreadAnd all the other lines are connected with zero potential, and the resistance states of all the units connected with the reset line are read at one time.
Has the advantages that: the invention has the advantages that due to the three-terminal device, compared with the traditional 1D1R device, the problem that the reset is difficult in the 1D1R device is solved by the setting electrode, and the current is not limited during the setting operation. On the other hand, when the device is made into a cross array, the crosstalk problem of the resistive random access memory device in the cross array structure can be solved by using the rectification characteristic of the diode. Meanwhile, the method can be compatible with a CMOS (complementary metal oxide semiconductor) planar process, and the integration of the resistive random access memory and a circuit is realized.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from the provided drawings without inventive effort.
Fig. 1 shows a simplified circuit schematic of a three-terminal resistive memory device;
fig. 2 shows a schematic cross-sectional view of embodiment 1 of a three-terminal resistive memory device, in which a diode employs a pn junction;
fig. 3 shows a schematic cross-sectional view of embodiment 2 of a three-terminal resistive memory device, the diode of which employs a schottky junction;
fig. 4 shows a schematic cross-sectional view of embodiment 3 of a three-terminal resistive memory device, in which a diode forms a pn junction using a p-well n-doped region;
fig. 5 shows a schematic cross-sectional view of embodiment 4 of a three-terminal resistive memory device in which a transition electrode is present in its structure;
fig. 6 is a schematic cross-sectional view showing embodiment 5 of a three-terminal resistive memory device, in which a transition electrode is present and a diode employs a schottky junction;
fig. 7 is a schematic cross-sectional view showing embodiment 6 of a three-terminal resistive memory device, in which a diode direction is perpendicular to a substrate, so that a device footprint is reduced.
Fig. 8 shows a cross array structure of a three-terminal resistive memory device in a wiring manner that can suppress crosstalk current.
Description of the symbols:
the semiconductor device comprises a set electrode 11, a base electrode 12, a reset electrode 13, a transition electrode 14, a diode upper electrode 15, an insulating medium 21, a resistive medium 22, a first semiconductor doping region 31, a second semiconductor doping region 32, an oxide semiconductor 33 and a substrate 41.
Detailed Description
In an embodiment, the resistive memory device includes a base electrode, a set electrode, a reset electrode, a resistive medium, a diode, and an insulating medium. The base electrode, the set electrode and the reset electrode are used for setting, resetting and data output of the resistive random access memory device. The resistance change medium can form a conductive channel in a setting mode, and a device is changed from a high resistance state to a low resistance state; the conducting channel is disconnected in a reset mode, and the device is changed from a low-resistance state to a high-resistance state; the device state is read out in the output mode. The diode can be a PN junction diode or a Schottky diode, and the problem of crosstalk of the cross array structure of the resistive random access memory can be solved by utilizing the rectifying characteristic of the diode. The insulating medium limits current to be excessive in a set operation and suppresses crosstalk current in a read operation.
The three-terminal resistive random access memory is characterized in that: firstly, forming a diode on a substrate; the resistance change medium and the insulating medium are in contact with the same end of the diode; forming a base electrode on the resistance change medium, and forming a set electrode on the insulating medium; and a reset electrode is formed at the other end of the diode in a contact mode.
One of the manufacturing methods of the three-terminal resistive random access memory comprises the following steps: doping a Si substrate to form a PN junction diode; then growing an insulating medium layer on the substrate; patterning a resistance change medium area above the first semiconductor doping area by photoetching and etching an insulating medium, and forming a resistance change medium in the area; then, patterning a reset electrode area above the second semiconductor doping area by photoetching and etching an insulating medium, and depositing a reset electrode material in the area; and then forming a base electrode above the resistance change medium, and forming a set electrode on the upper surface of the insulating medium above the first semiconductor doping area. The three-terminal resistive random access memory can also allow a transition electrode to exist, and when the transition electrode exists, the transition electrode can be only positioned below the resistive random access medium and is only arranged between the diode and the resistive random access medium. Or the transition electrode is simultaneously positioned below the resistance change medium and the insulating medium and is arranged between the diode and the resistance change medium and between the diode and the insulating medium.
The operation method of the three-terminal resistive random access memory comprises the following steps: the setting operation of the device is realized by applying bias voltages on the base electrode and the setting electrode; applying bias voltage to the base electrode and the reset electrode to realize the reset and read operation of the device; setting operation refers to the fact that the resistive switching medium layer is changed from a high resistance state to a low resistance state, and large bias voltage is adopted; the reset operation refers to that the resistive medium layer is changed from a low-resistance state to a high-resistance state, and a larger bias voltage is adopted; the read operation refers to reading the resistance state of the device, using a smaller bias voltage.
The following disclosure provides many different embodiments for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Also, spatially relative terms such as "below …", "below …", "below", "over …", "over" and the like may be used herein to describe one element or component's relationship to another (or other) element or component as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
1) Fig. 1 is a schematic diagram of a simplified circuit of a three-terminal resistive random access memory device capable of suppressing crosstalk current, in which, during a set operation, a bias voltage is applied between a set electrode and a base electrode, which may generate a voltage drop across a resistive random access medium, so that the device is changed from a high resistance state to a low resistance state, which is similar to a complementary resistive random access memory; during reset operation, applying bias voltage between the reset electrode and the base electrode to make the device change from a low-resistance state to a high-resistance state; in a read operation, a bias voltage is applied between the reset electrode and the base electrode to read the state of the device.
2) Further, during a read operation, a diode or an insulating medium in a reverse direction may exist on a crosstalk current path. Due to the rectifying action of the diode, the cross-talk current is greatly suppressed due to the low conductivity of the insulating medium.
3) Further, in some embodiments, the resistive memory device includes a base electrode, a set electrode, a reset electrode, a resistive medium, a diode, and an insulating medium. The base electrode, the set electrode and the reset electrode are used for setting, resetting and data output of the resistive random access memory device. The resistance change medium can form a conductive channel in a setting mode, and a device is changed from a high resistance state to a low resistance state; the conducting channel is disconnected in a reset mode, and the device is changed from a low-resistance state to a high-resistance state; the device state is read out in the output mode. The diode can be a PN junction diode or a Schottky diode, and the problem of crosstalk of the cross array structure of the resistive random access memory can be solved by utilizing the rectifying characteristic of the diode. The insulating medium limits current to be excessive in a set operation and suppresses crosstalk current in a read operation.
4) Further, the three-terminal resistive random access memory can also allow a transition electrode to exist, and when the transition electrode exists, the transition electrode can be only located below the resistive random access medium and is only located between the diode and the resistive random access medium. Or the transition electrode is positioned below the resistance change medium and the insulating medium and is arranged between the diode and the resistance change medium and between the diode and the insulating medium.
5) Further, the three-terminal resistive random access memory is prepared from the following materials: base electrode, set electrode, reset electrode and transition electrodeAre conductive materials including, but not limited to, copper (Cu), gold (Au), silver (Ag), platinum (Pt), titanium (Ti), titanium nitride (TiN), aluminum (Al), tungsten (W), tantalum (Ta), tantalum nitride (TaN). The resistive random access memory is a material with resistive random access property, including ferroelectric polarization material, phase change material, magnetic tunneling resistive random access material, and oxidation-reduction resistive random access material, specifically including but not limited to zirconium oxide (ZrO)2) Zinc oxide (ZnO), titanium oxide (TiOx), hafnium oxide (HfOx), and aluminum oxide (Al)2O3) Tantalum oxide (TaOx), manganese oxide (MnO), silicon oxide (SiO)2) Isooxide and Ag2S, etc. fast ion conductor. The insulating medium is a low conductivity material including, but not limited to, silicon oxide (SiO)2) Hafnium oxide (HfOx), zirconium oxide (ZrO)2) Tantalum oxide (TaOx), titanium oxide (TiOx).
6) Further, a specific simplified step of manufacturing the three-terminal resistive random access memory shown in fig. 2 is: cleaning a silicon wafer by using acetone and absolute ethyl alcohol; spin-coating photoresist after dehydration and baking; thirdly, placing the sample on a photoetching machine for exposure; clamping a sample by using a pair of tweezers, and vertically immersing the sample into a developing solution for developing; forming an n heavily doped region on the substrate 41 by ion implantation; sixthly, repeating the steps from the first step to the fourth step, and forming a p-doped region through ion implantation; depositing a layer of SiO on the sample by atomic layer deposition2As an insulating medium; repeating the steps from the first step to the fourth step, and etching off partial SiO above the n-doped region of the diode2(ii) a Ninthly depositing a layer of ZrO on the sample by atomic layer deposition2As a resistance change medium, repeating the steps from the first step to the fourth step to ZrO2Etching to form a resistance change medium 22; r repeating the steps from r to etch off part of SiO above the p-doped region of the diode2；
Repeating the first step to the fourth step, and forming a reset electrode in the etched area through magnetron sputtering;
repeating the steps from the first step to the fourth step to form a base above the resistance change mediumAn electrode;
repeating the first step to the fourth step, and forming a set electrode above the insulating medium.
7) Further, the structure of embodiment 2 shown in fig. 3 has fewer manufacturing steps than embodiment 1. The reset electrode 13 is contacted with the semiconductor doped region 31 to form a Schottky junction as a diode, and only one time of ion implantation is needed to be carried out on the substrate. On the other hand, the Schottky junction is selected as the diode, so that the operation speed of the device can be improved.
8) Further, the structure of embodiment 3 shown in fig. 4 is more advantageous in forming a pn junction than embodiment 1. Taking a p-well as an example, the specific implementation of the diode is as follows: a p-well doped region, i.e., the second semiconductor doped region 32, is first formed on the substrate by ion implantation, and then an n-heavily doped region, i.e., the first semiconductor doped region 31, is formed within the p-doped region by ion implantation. The manufacturing process has reduced alignment requirements on the mask when forming the pn junction.
9) Further, in the embodiments shown in fig. 2, 3, and 4, the resistive medium and the insulating medium may be interchanged in position, that is, the insulating medium and the set electrode are located near the reset electrode, and the resistive medium and the base electrode are located far from the reset electrode.
10) Further, in the structure of embodiment 4 shown in fig. 5, a transition electrode is present, compared to embodiment 1. This advantageously reduces the voltage drop across the diode during operation of the device. The operating voltage of the device is reduced, the switching ratio of the device is improved, and conductive substances in the resistive medium are prevented from migrating into the diode.
11) Further, the structure of embodiment 5 shown in fig. 6 has fewer manufacturing steps than embodiment 4. On one hand, the reset electrode 13 is contacted with the first semiconductor doping region 31 to form a Schottky junction as a diode, and ohmic contact is formed between the transition electrode 14 and the semiconductor doping region 31; on the other hand, the transition electrode 14 may be in contact with the first semiconductor doping region 31 to form a schottky junction as a diode, and the reset electrode 13 may be in ohmic contact with the first semiconductor doping region 31.
12) Further, in addition to the structures shown in fig. 5 and 6, the transition electrode may be present only below the resistance variable medium and only between the resistance variable medium and the diode.
13) Further, in embodiment 6 shown in fig. 7, the diode direction is perpendicular to the substrate, which can reduce the device area and facilitate integration. In which there is a substrate 41, a reset electrode 13; the reset electrode 13, the oxide semiconductor 33, and the diode upper electrode 15 constitute a diode; the transition electrode 14 is also arranged, and the resistance change medium 22 is an insulating medium 21; base electrode 12, set electrode 11. A specific simplified step of manufacturing the three-terminal resistive random access memory shown in fig. 7 is: cleaning a silicon wafer by using acetone and absolute ethyl alcohol; spin-coating photoresist after dehydration and baking; thirdly, placing the sample on a photoetching machine for exposure; clamping a sample by using a pair of tweezers, and vertically immersing the sample into a developing solution for developing; performing magnetron sputtering on Pt, and cleaning a silicon wafer (performing metal stripping) to be used as a reset electrode 13; depositing TiO by atomic layer deposition2Repeating the steps from the first step to the fourth step on the TiO2Etching is performed to form an oxide semiconductor 33; seventhly, the steps from the first step to the fourth step are repeated, metal Ti and metal Pt are sputtered in sequence, and a silicon wafer is cleaned (stripped) and serves as an upper electrode 15 and a transition electrode 14 of the diode, wherein a reset electrode Pt and TiO2Forming a Schottky junction as a diode; (iii) depositing ZrO by adopting an atomic layer deposition technology2As a resistance change medium, repeating the steps from the first step to the fourth step to ZrO2Etching to form a graphic representation 22; ninthly, adopting atomic layer deposition technology to deposit HfO2As an insulating medium, repeating the steps from (i) to (iv) for HfO2Etching to form the graphic representation 21; c, repeating the steps from the first step to the fourth step, carrying out magnetron sputtering on Ag, and cleaning the silicon wafer to be used as a base electrode 12;
and repeating the steps from the first step to the fourth step, performing magnetron sputtering on Pt, and cleaning the silicon wafer to obtain the set electrode 11.
14) Further, fig. 8 shows a wiring pattern of a cross array structure of a three-terminal resistive memory device that can suppress crosstalk current. A base line (BaseLine) connected with the base electrode, a set line (SetLine) connected with the set electrodeThe electrodes are connected, and a reset line (ResetLine) is connected with the reset electrode. The illustration shows a 2 x 2 array, which can be extended to n x m with reference to the illustrated wiring pattern. Taking the unit selected by the base line 1, the set line 1 and the reset line 1 as an example, the operation method is as follows: when setting, base line 1 is connected with 0 potential, and bit line 1 is connected with set voltage VsetAll the other wires are connected with V set2; secondly, when resetting, the base line 1 is connected with 0 potential, and the reset line 1 is connected with a reset voltage VresetAll the other wires are connected with V reset2; ③ when reading, the base line 1 is connected with 0 potential, the reset line 1 is connected with the reading voltage VreadAll the other wires are connected with Vread/2. In addition, the read operation may read a plurality of cell storage data at a time. The operation method comprises the following steps: a selected one of the reset lines VreadAnd all the other lines are connected with zero potential, and the resistance states of all the units connected with the reset line are read at one time.
Claims (10)
1. A three-terminal resistive random access memory capable of suppressing crosstalk current is characterized by comprising a set electrode (11), a base electrode (12), a reset electrode (13), a resistive medium (22), an insulating medium (21), a first semiconductor doping region (31), a second semiconductor doping region (32) and a substrate (41); structurally, a substrate (41) is taken as a base, a first semiconductor doping region (31) and a second semiconductor doping region (32) are formed on the substrate (41), an insulating medium (21) is located on the upper surfaces of the substrate (41), the first semiconductor doping region (31) and the second semiconductor doping region (32), a set electrode (11) is located above the first semiconductor doping region (31) on the upper surface of the insulating medium (21), a resistance changing medium (22) penetrates through the insulating medium (21) and is located above the first semiconductor doping region (31), a base electrode (12) is arranged on the resistance changing medium (22), and a reset electrode (13) penetrates through the insulating medium (21) and is located on the second semiconductor doping region (32); the set electrode (11), the base electrode (12) and the reset electrode (13) are used for setting, resetting and data output of the resistive memory device.
2. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 1, wherein: a transition electrode (14) can be arranged on the first semiconductor doping region (31); when the transition electrode (14) exists, the transition electrode (14) is located below the resistive medium (22), namely between the first semiconductor doping region (31) and the resistive medium (22), or the transition electrode (14) is located below the resistive medium (22) and the insulating medium (21) at the same time and between the first semiconductor doping region (31) and the resistive medium (22), between the first semiconductor doping region (31) and the insulating medium (21).
3. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 2, wherein: the diode formed by the first semiconductor doping region (31) and the second semiconductor doping region (32) is a PN junction diode, the diode formed by the reset electrode (13) and the first semiconductor doping region (31) is a Schottky diode, and the directions of the diode include but are not limited to: perpendicular to the substrate, parallel to the substrate.
4. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 1, wherein the base electrode (12), the set electrode (11), the reset electrode (13) and the transition electrode (14) are all made of conductive materials; the resistance change medium (22) is a material with resistance change property; the insulating medium (21) is a low conductivity material.
5. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 1, wherein the conductive material comprises: copper, gold, silver, platinum, titanium nitride, aluminum, tungsten, tantalum nitride.
6. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 1, wherein the material having resistive characteristics comprises a ferroelectric polarization material, a phase change material, a magnetic tunneling resistive material, or an oxidation-reduction resistive material.
7. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 1, wherein the ferroelectric polarization material, the phase change material, the magnetic tunneling resistive material or the oxidation-reduction resistive material comprises: zirconium oxide, zinc oxide, titanium oxide, hafnium oxide, aluminum oxide, tantalum oxide, manganese oxide, silicon oxide, or silver sulfide.
8. The three-terminal resistive random access memory capable of suppressing crosstalk current according to claim 1, wherein the low conductivity material comprises: silicon oxide, hafnium oxide, zirconium oxide, tantalum oxide, or titanium oxide.
9. The preparation method of the three-terminal resistive random access memory capable of inhibiting crosstalk current according to claim 1, characterized by comprising the following steps: doping is carried out on a Si substrate (41) to form a first semiconductor doping region (31) and a second semiconductor doping region (32) PN junction diode; then growing an insulating medium (21) on the substrate (41); patterning a resistance change medium area on the first semiconductor doping area (31) by photoetching and etching the insulating medium (21), and forming a resistance change medium (22) in the area; then, patterning a reset electrode region (13) on the second semiconductor doping region (32) by photoetching and etching the insulating medium (22), and depositing a reset electrode material in the region; then, a base electrode (12) is formed above the resistance change medium (22), and a set electrode (11) is formed on the upper surface of the insulating medium (21) on the first semiconductor doping region (31).
10. The method for operating a three-terminal resistive memory device capable of suppressing a crosstalk current according to claim 1, wherein: applying bias voltage on the base electrode (12) and the set electrode (11) to realize the set operation of the device; and applying bias voltage to the base electrode (12) and the reset electrode (13) to realize the reset and read operations of the device.
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| CN102569337A (en) * | 2012-03-15 | 2012-07-11 | 北京大学 | Anti-crosstalk flexible transparent memory array and preparation method thereof |
| CN102593142A (en) * | 2012-03-15 | 2012-07-18 | 北京大学 | Anti-crosstalk flexible transparent memory array and production method thereof |
| CN107301875A (en) * | 2016-04-14 | 2017-10-27 | 中芯国际集成电路制造(上海)有限公司 | A kind of memory cell, memory unit and memory cell array |
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| CN102569337A (en) * | 2012-03-15 | 2012-07-11 | 北京大学 | Anti-crosstalk flexible transparent memory array and preparation method thereof |
| CN102593142A (en) * | 2012-03-15 | 2012-07-18 | 北京大学 | Anti-crosstalk flexible transparent memory array and production method thereof |
| CN107301875A (en) * | 2016-04-14 | 2017-10-27 | 中芯国际集成电路制造(上海)有限公司 | A kind of memory cell, memory unit and memory cell array |
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