RU2468471C1 - Method of obtainment of nonvolatile storage element - Google Patents

Method of obtainment of nonvolatile storage element Download PDF

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RU2468471C1
RU2468471C1 RU2011113573/28A RU2011113573A RU2468471C1 RU 2468471 C1 RU2468471 C1 RU 2468471C1 RU 2011113573/28 A RU2011113573/28 A RU 2011113573/28A RU 2011113573 A RU2011113573 A RU 2011113573A RU 2468471 C1 RU2468471 C1 RU 2468471C1
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resistive switching
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Вадим Вячеславович Путролайнен
Андрей Александрович Величко
Генрих Болеславович Стефанович
Александр Лионович Пергамент
Николай Александрович Кулдин
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Государственное образовательное учреждение высшего профессионального образования "Петрозаводский государственный университет"
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Abstract

FIELD: electricity.
SUBSTANCE: method of obtainment of nonvolatile storage element includes creation of lower conductive electrode, buffer insulating layer, layer with resistive switching and upper conductive electrode. According to the method, contact of nanosized scale is created to layer with resistive switching by means of electrical moulding of structure. Buffer insulating layer and layer with resistive switching are made of binary oxides using low-temperature vacuum-deposition technique. Availability of contact of nanosized scale to layer with resistive switching localises switch area.
EFFECT: increasing relation of resistances in low-resistance and high-resistance state, stabilising switch parameters, reducing risk of structure degradation, increasing total quantity of switch cycles.
3 cl, 2 dwg

Description

Application area

The invention relates to the field of microelectronics and can be used in the manufacture of two-electrode resistive non-volatile elements of memory devices.

State of the art

Currently, in the field of microelectronics there are a number of problems, the solution of which is not possible on the basis of standard silicon technology (CMOS, etc.). One of the most pressing problems is to further increase the degree of integration of microcircuits. By setting the physical size of the chip, the necessary increase in the number of components requires a transition from planar two-dimensional to three-dimensional (3D) integration (the microcircuit grows upward), which is impossible in the framework of the standard high-temperature (over 700 ° C) silicon technology - the creation of the upper layers of the elements will destroy the underlying components. This is especially noticeable when developing memory chips. The required amount of memory (more than 1 TB) can be implemented on the basis of a multi-storey (stackable) design. The creation of such microcircuits requires the use of low-temperature methods of deposition of materials and the development of fundamentally new effective electronic components based on these materials.

Flash technology allows you to implement fast memory (nanosecond access scale) of a sufficiently large volume, which can combine two classes of computer memory - to perform the functions of both operational and long-term, non-volatile storage of information. To determine this memory, IBM researchers have introduced a special term - storage class memory (SCM).

However, numerous and expensive studies have shown that flash technology based on the use of the standard (but practically no alternative) planar process (CMOS) of silicon technology does not allow SCM memory to be implemented. The main obstacle is the uncontrolled runaway of the information charge in nanoscale structures. In addition, an elementary examination shows that in order to realize the same information volume that is implemented in modern HDDs, a transition to 3D integration is necessary, which is impossible in the modern planar process of silicon technology.

The most promising 3D technology at the moment is considered a multilayer memory structure (stackable memory), each layer of which is organized in the form of a system of perpendicular metal conductors, at the intersection points of which are located cells that store information (cross-point memory).

For implementation, it should be noted that such a memory design highlights the requirement for the use of low-temperature processes. SCM 3D memory considers a number of physical phenomena: the ferroelectric transition in nanoscale capacitors, the change in the magnetization of nanoscale domains, the electrochemical growth of conductive nanoclusters, and resistive switching. Each phenomenon has a number of limitations, and the most advanced effect (without physically insurmountable restrictions) is currently considered to be resistive switching in thin films of chalcogenide amorphous materials or oxide films (RRAM).

The resistive transition in chalcogenide materials is determined by the electrically stimulated reversible transition from the amorphous to the crystalline state, with different resistivities. However, this transition does not allow to achieve the necessary operational characteristics. In particular, the current of erasing information is quite high and there is no physical possibility of reducing it.

Resistive Random Access Memory (ReRAM) switching in oxide films looks more promising, which is realized in numerous oxide families obtained by various low-temperature methods. The advantages of ReRAM are the simplicity of the structure, relatively easy scalability, the ability to create multi-level structures.

Non-volatile resistive switching was found in a wide range of transition metal oxides, both in simple binary oxides: Nb 2 O 5 [1], Ta 2 O 5 [2], TiO 2 [3], NiO [4], etc., and in complex multicomponent oxides of perovskite-like structure: RSMO [5], Cr: SZO [6], SrTiO 3 [7], Nb: STO [8], etc.

The following requirements are set for non-volatile resistive memory elements:

1) a large difference in the resistance of structures in a high-resistance and low-resistance state;

2) high performance during recording and reading;

3) long information storage time;

4) ease of manufacture, cheap and efficient production technology;

5) small cell sizes.

At the moment, the main method for the production of non-volatile resistive memory elements includes the following steps:

- the formation of the lower conductive electrodes,

- the formation of an oxide layer having resistive switching,

- application of the upper conductive electrodes.

A known element of non-volatile memory using oxides of transition metals as a layer having a resistive switching located between two electrodes. The memory element consists of two conductive layers (electrodes) and a layer of non-stoichiometric metal oxide with resistive switching between them. Non-stoichiometric oxides may exhibit better resistive switching properties than stoichiometric. Particularly suitable are the following metal oxides: Ti x O y , Zr x O y , Hf x O y , V x O y , Nb x O y , Ta x O y , Cr x O y , Mo x O y and W x O y . The metal oxide contains at least one dopant, for example Ti, Co, Zr, V, Al, Nb. Dopants can be introduced at any suitable concentration (for example, an atomic concentration of 0-30%).

The first conductive layer may be formed of metal nitride. The second electrode contains a material selected from the group consisting of Pt, Ir, Ru, Rh, Re, Pd, Ti x Al y N z , Ta x Al y N z , W x Al y N z , IrO 2 and RuO 2 . The conductive layers can form an ohmic contact or a Schottky contact with the oxide layer. All layers may contain sublayers. Electrical devices, such as diodes, can be connected in series with memory elements.

A method of obtaining a memory element according to patent CN 101711431

1. A lower conductive layer consisting of metal nitrides is applied to a dielectric substrate by vacuum deposition methods.

2. Next, a layer having a resistive switching is applied, consisting, as a rule, of non-stoichiometric transition metal oxides such as Ti x O y , Zr x O y , Hf x O y , V x O y , Nb x O y , Ta x O y , Cr x O y , Mo x O y and W x O y . Also, these oxides can be alloyed with metals such as Li, Cr, Ca or La.

3. On the layer with resistive switching, the upper conductive layer is applied, which is made of metals: Pt, Ir, Ru, Rh, Re, Pd, Ti x Al y N z , Ta x Al y N z , W x Al y N z , IrO 2 and RuO 2 .

The disadvantage of this memory element is that the resistive switching in memory elements using non-stoichiometric transition metal oxides is in most cases unstable: switching parameters, such as the value of the current strength in the high-resistance and low-resistance state, the threshold voltage of the transitions from one state to another, can vary from cycle to cycle. The total number of switching is small (10 1 -10 3 ), after which, as a rule, there is a degradation of the structure, in which the structure irreversibly goes into a low-resistance state.

A non-volatile resistive memory element is also known that uses a perovskite-like oxide layer as a data storage material. The switchable resistive device is a multilayer thin-film structure located between the upper and lower conductive electrodes. Multilayer thin film structures include a perovskite layer with a buffer layer on one side or a perovskite layer with buffer layers on either side of the perovskite layer. Reversible changes in resistance are induced in the device when electrical impulses are applied. Changes in the resistance of the device are saved after applying electrical pulses. The functions of the buffer layer added to the device include: increasing the resistance of the switching area, reducing the voltage pulse required to switch the device, protecting the device from damage by a shock current pulse, increasing the temperature, and also increasing the stability of the device, allowing it to be used for various memory applications ( Patent US 7608467 from 10.27.2009).

A method of obtaining a memory element according to patent US 7608467

1. A lower conductive layer is applied to the substrate by vacuum deposition methods.

2. A buffer layer consisting of SiO 2 , CeO 2 , MgO, ZnO and Y 2 O 3 or perovskite-like oxides without resistive switching is applied to the lower electrodes: LaMnO 3 , Ba 1-x Sr x TiO 3 (BST), Pb (Zr, Ti) O 3 (PZT), La doped PZT (PLZT) and Pb 3 Ge 5 O 11 (PGO).

3. Next, a layer having a resistive switching is applied, consisting of oxides of a perovskite-like structure: LnBa (Co, M) 2 O 5 + x , ReBMnO 3 , ReВСоO 3 and doped compounds based on them, where Ln = Eu or Gd, M = Cu , Fe, Re is a rare-earth ion, and B = Li + , Na + or K + .

4. On the layer with resistive switching, the upper conductive layer is applied.

The disadvantage of this memory element is the low resistance ratio in the low-resistance and high-resistance state (less than 1 order), which is one of the main parameters of the memory element. In addition, the use of complex oxides of the perovskite structure, the preparation of which is a separate technological task and is carried out at high temperatures, which impedes the process of three-dimensional integration of the memory chip. The use of simpler binary oxides with resistive switching is more advantageous in terms of the cost of production of memory elements.

The technical result of the invention consists in increasing the ratio of resistances (3 orders of magnitude) in the low-resistance and high-resistance state, as well as simplifying the technology and lowering the temperatures in the process of obtaining a buffer insulation layer and a layer having resistive switching, which makes it possible to reduce the cost of manufacturing non-volatile memory elements and perform three-dimensional integration chips based on them, significantly increasing the amount of memory.

The technical result is achieved by creating a contact of nanoscale scale (less than 50 nm) to a layer having resistive switching by electrical molding of the structure. The buffer insulation layer and the resistive switching layer are made of binary oxides using low-temperature (less than 350 ° C) vacuum deposition methods. Non-stoichiometric binary transition metal oxides Ti x O y , Zr x O y , Hf x O y , V x O y , Nb x O y , Ta x O y , Cr x O y , are used as the material of the layer with resistive switching. Mo x O y , W x O y or their doped compounds. The following oxides with high dielectric constant are used as the material of the buffer layer: SiO 2 , Ta 2 O 5 , TiO 2 , Al 2 O 3 , HfO 2 , Y 2 O 3 , La 2 O 3 , ZrO 2 , Gd 2 O 3 , Er 2 O 3 , Sc 2 O 3 , SrTiO 3 . As the material of the electrodes, metals or semiconductors with low resistivity are used.

List of figures

Figure 1 shows the general structure of the memory cell: 1 - the upper conductive electrode, 2 - the layer with resistive switching, 3 - buffer insulation layer, 4 - the lower conductive electrode, 5 - the conductive channel resulting from electrical molding.

Figure 2 shows the switching in the structure of Si-SiO 2 -V 2 O 5 -Au after molding.

A method of obtaining a non-volatile memory element is the creation of lower and upper conductive electrodes, between which a two-layer structure is created, which is: a buffer insulation layer adjacent to the lower conductive electrode and a layer with resistive switching adjacent to the upper conductive electrode (see Fig. one). All steps of manufacturing a non-volatile memory element are performed using low temperature methods.

A method of obtaining a non-volatile memory element:

1. A lower electrode consisting of a metal or a semiconductor with a low resistivity is applied to the substrate by vacuum deposition methods.

2. A buffer layer consisting of oxides with a high dielectric constant is applied to the lower electrodes: SiO 2 , Ta 2 O 5 , TiO 2 , Al 2 O 3 , HfO 2 , Y 2 O 3 , La 2 O 3 , ZrO 2 , Gd 2 O 3 , Er 2 O 3 , Sc 2 O 3 , SrTiO 3 .

3. Next, a resistive switching layer is applied, consisting of non-stoichiometric binary transition metal oxides Ti x O y , Zr x O y , Hf x O y , V x O y , Nb x O y , Ta x O y , Cr x O y , Mo x O y , W x O y or their doped compounds.

4. On the layer with resistive switching, the upper electrode is applied.

In the initial state (IS), the structure is in a state with a high resistance determined by the buffer insulating layer. When a positive voltage is applied to the upper conductive electrode with a value sufficient for electrical breakdown of the buffer insulating layer (depending on its material and thickness), the structure abruptly (stepwise) goes into a state with low resistance. This process is called electrical molding. The molding voltage is due to electrical breakdown of the buffer insulating layer and depends on the material of this layer and its thickness. As a result of electrical molding, a conductive channel is formed in the buffer insulating layer, which creates a nanoscale contact to the layer with resistive switching. To obtain a nanoscale contact, it is necessary to limit the current during molding (10 6 -10 5 A) using a voltage source or series resistance. Under conditions of current limitation, the main source of energy released during electrical molding is the discharge of a capacitor structure formed by a buffer insulating layer. In this case, a thin conducting channel is formed in the dielectric layer, creating a channel of precisely the nanoscale scale. Further expansion of the conductive channel does not occur due to the relatively small release of thermal energy in the conductive channel due to the limitation of the flowing current.

The presence of a nanoscale contact to a layer with resistive switching localizes the switching region. In this case, the parameters of the memory element change: the ratio of resistances in the low-resistance and high-resistance state increases, the switching parameters are stabilized, the probability of degradation of the structure decreases, increasing the total number of switching cycles (more than 10 6 ).

After electrical molding, a non-volatile switching is observed in the structure (see FIG. 2), namely, upon subsequent supply of a negative voltage to the upper electrode, the structure (I-II) switches to the high-resistance state (BC) (III-IV). When a sufficiently large positive voltage (IV-V) is reached, the structure returns to the low-impedance state (HC) (VI-I).

The physical principle of the functioning of the present invention as an element of non-volatile memory is based on a reversible change in the resistance of the boundary between the layer with resistive switching and the conductive channel in the buffer insulation layer due to the electric field migration of oxygen ions, accompanied by a change in the concentration of oxygen vacancies.

The implementation of the invention

An oxide film is deposited on a oxidized silicon Si-SiO 2 silicon substrate (p-type KDB, oxide thickness ~ 100 nm) by thermal spraying of V 2 O 5 powder in a vacuum at a VUP-5M industrial unit at room temperature (20 ° C) of the substrate vanadium pentoxide (V 2 O 5 ) ~ 100 nm thick. A gold (Au) top electrode is sprayed onto the V 2 O 5 layer. Formation of the structure occurs when a voltage of 100 V is applied to the structure, after which the structure goes into a state that has switching with memory.

The switching technical characteristics are as follows: the ratio of resistances in the low-resistance and high-resistance state during switching is 10 3 (from 1 GΩ in the high-resistance to 1 MΩ in the low-resistance state, with a positive voltage of 5 V); stable switching of the memory element for at least 10 6 cycles; switching remains stable at temperatures up to 100 ° C, while the switching voltage changes by no more than 0.5 V.

Figure 00000001

Claims (3)

1. A method of obtaining a non-volatile memory element, including the creation of a lower conductive electrode, a buffer insulation layer, a layer having a resistive switching, and an upper conductive electrode, characterized in that they create a nanoscale contact to a layer having a resistive switching, by electrically forming the structure, a buffer the insulating layer and the resistive switching layer are made from binary oxides using low temperature vacuum spray methods i.
2. The method of producing a non-volatile memory element according to claim 1, characterized in that non-stoichiometric metal oxides are used as the material of the layer having resistive switching: Ti x O y , Zr x O y , Hf x O y , V x O y , Nb x O y , Ta x O y , Cr x O y , Mo x O y , W x O y , or their doped compounds.
3. The method of producing a non-volatile memory element according to claim 1, characterized in that binary oxides with a high dielectric constant are used as the material of the buffer insulating layer: SiO 2 , Ta 2 O 3 , TiO 2 , Al 2 O 3 , HfO 2 , Y 2 O 3 , La 2 O 3 , ZrO 2 , Gd 2 O 3 , Er 2 O 3 , Sc 2 O 3 .
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RU2540486C1 (en) * 2013-09-27 2015-02-10 федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский национальный исследовательский университет информационных технологий, механики и оптики" (Университет ИТМО) Method of obtainment of resistance storage element

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RU2516771C1 (en) * 2012-10-23 2014-05-20 Федеральное государственное бюджетное учреждение науки Институт физики полупроводников им. А.В. Ржанова Сибирского отделения Российской академии наук (ИФП СО РАН) Resistive flash memory element
KR20170131189A (en) * 2016-05-20 2017-11-29 크로스바, 인크. Non-stochastic resistive switching memory device and fabrication methods

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