CN112563269A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN112563269A
CN112563269A CN202011023396.3A CN202011023396A CN112563269A CN 112563269 A CN112563269 A CN 112563269A CN 202011023396 A CN202011023396 A CN 202011023396A CN 112563269 A CN112563269 A CN 112563269A
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layer
dielectric layer
region
fin
semiconductor
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萧琮介
陈柏勳
蔡宗裔
李宗霖
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/938,580 external-priority patent/US11437372B2/en
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Publication of CN112563269A publication Critical patent/CN112563269A/zh
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Abstract

本发明实施例提供一种半导体装置，包括位于半导体基板上鳍状结构。鳍状结构包括底部与顶部。底部与顶部包括不同材料。装置亦包括位于底部的侧壁上的衬垫层、位于衬垫层的侧表面上的介电层、界面层、与位于介电层上并接合鳍状结构的栅极结构。衬垫层的上表面延伸低于顶部的下表面。界面层的第一部分位于底部的侧壁表面上并与其直接接触，且界面层的第二部分位于顶部的上表面与侧壁表面上并与其直接接触。栅极结构包括高介电常数的介电层，与高介电常数的介电层上的金属栅极。高介电常数的介电层直接接触界面层的第一部分。

Description

半导体装置
技术领域
本发明实施例涉及集成电路与半导体装置以及其形成方法，特别涉及半导体装置所用的衬垫层结构，其可改善装置特性如关闭状态的漏电流。
背景技术
半导体集成电路产业已经历快速成长。在集成电路演进中，功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小的工艺通常有利于增加产能并降低相关成本。然而尺寸缩小亦会增加设计与制造含有这些集成电路的装置的复杂度。为实现这些进展，装置的制作方法亦须类似发展。
随着集成电路装置的几何尺寸持续缩小，维持装置可信度与电源效率变得更具挑战性。关闭状态的漏电流为电源效率不足的主要原因，且通常视作未来微处理器整合的限制因素。目前发现若p型场效晶体管含有氮化硅为主的衬垫层，有时会造成关闭状态的漏电流提高。虽然现有的衬垫层与其制造方法适用于其发展目的，但仍无法符合所有方面的需求。
发明内容
本发明一实施例关于半导体装置，其包括半导体基板与位于半导体基板上的鳍状结构。鳍状结构包括由第一材料制成的底部与由第二材料制成的顶部。第一材料与第二材料不同。半导体装置亦包括位于底部的侧壁上的衬垫层。衬垫层的上表面延伸低于顶部的下表面。半导体装置还包括位于半导体基板上与衬垫层的侧表面上的介电层，以及界面层。界面层具有第一部分和第二部分，第一部分设于底部的侧壁表面上并与其直接接触，第二部分设于顶部的上表面与侧壁表面上并与其直接接触。半导体装置亦包括位于介电层上并接合鳍状结构的栅极结构。栅极结构包括高介电常数的介电层，与高介电常数的介电层上的金属栅极。高介电常数的介电层直接接触界面层的第一部分。
本发明一实施例关于半导体装置，其包括半导体基板、鳍状结构、衬垫层、介电层以及栅极结构；鳍状结构位于半导体基板上；衬垫层位于鳍状结构的侧壁上；介电层位于半导体基板上并覆盖衬垫层的上表面与侧表面；栅极结构位于介电层上并接合鳍状结构的通道部分。
本发明一实施例关于半导体装置的形成方法，其包括接收半导体结构。半导体结构包括半导体基板、鳍状结构、衬垫层以及第一介电层；鳍状结构位于半导体基板上；衬垫层位于鳍状结构的侧壁上；第一介电层位于半导体基板与衬垫层的侧表面上。方法亦包括使第一介电层与衬垫层凹陷，以形成凹陷的第一介电层与凹陷的衬垫层，并露出鳍状结构的第一部分。方法还包括沉积第二介电层于第一介电层与修整的鳍状结构上。第二介电层的上表面延伸高于修整的鳍状结构的上表面。此外，方法包括使第二介电层凹陷以露出修整的鳍状结构的第二部分。凹陷的第二介电层的上表面延伸高于凹陷的衬垫层的上表面并低于修整的鳍状结构的上表面。方法额外包括形成栅极结构于凹陷的第二介电层与修整的鳍状结构上，使栅极结构接合鳍状结构的通道部分。
附图说明
图1是本发明一些实施例中，制作半导体装置的方法的流程图。
图2、3、4、5、6、7A、7B、及7C是本发明一些实施例中，半导体装置于工艺的不同阶段的剖视图。
图8A及8B是本发明一些实施例中，制作半导体装置的方法的流程图。
图9、10、11、12、13、14、15、16、17、及18是本发明一些实施例中，半导体装置于工艺的不同阶段的剖视图。
附图标记说明如下：
10,20A,20B,20C,20D,20E,20F,20G:半导体结构
100A,100B:方法
101:半导体基板
101A:n型掺杂区
101B:p型掺杂区
102,202:基底部分
103,203:鳍状结构
104,404:介电层
106,108:衬垫层
110,210:通道部分
112,212:抗击穿区
114,114A:盖层
114B:下侧部分
116:栅极介电层
118:栅极层
120,122,124,308:距离
140:栅极结构
150,250:肩部表面
158,192,258,292:侧壁表面
168,268:角度
172,182,272,282:横向宽度
190,290:上表面
310:通道高度
312,314:高度
1010A,1010B,1020A,1020B,1030A,1030B,1040A,1040B,1050A,1050B,1060A,1060B,1070A,1070B,1080B,1090B,1100B:步骤
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。特定构件与配置的实施例用以简化本发明内容而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触的实施例，或两者之间隔有其他额外构件而非直接接触的实施例。此外，本发明的多个实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中，结构可直接接触另一结构，或可形成额外结构于结构及另一结构之间。此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。此外，当数值或数值范围的描述有“约”、“近似”、或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围介于4.5nm至5.5nm之间。
本发明实施例一般关于集成电路与半导体装置以及其形成方法。本发明实施例特别关于半导体装置所用的新颖衬垫层结构，其可改善装置特性如关闭状态的漏电流。衬垫层常用于半导体装置中。举例来说，衬垫层可围绕鳍状结构、在接点开口中、以及位于多种栅极层之间。衬垫层可作为阻挡层以避免材料越过衬垫层而造成不想要的扩散、可作为黏着层以提供衬垫层两侧上的材料特性不类似的两种层状物之间较佳的黏着性、或可作为间隔物层以在衬垫层之间提供适当的电性绝缘。一般常用的衬垫层材料包括氧化硅、氮化硅、金属氧化物、金属氮化物、或上述的组合。然而一些衬垫层(如氮化硅衬垫层与氧化硅-氮化硅的组合衬垫层)若直接接触栅极，则会固定正电荷于衬垫层表面。这些正电荷会妨碍抗击穿区的功能，造成其缓解关闭状态的漏电流的效果下降。
在此考量下，抗击穿区为有源区的一部分，其形成于晶体管通道下且掺质浓度高于有源区的其余部分。对鳍状场效晶体管而言，抗击穿区可为鳍状结构的一部分。P型鳍状场效晶体管中的抗击穿区可掺杂n型掺质，而n型鳍状场效晶体管区中的抗击穿区可掺杂p型掺质。实施抗击穿区可阻止关闭状态中的电荷载子(或漏电流)自漏极空乏区迁移至源极空乏区的问题。当衬垫层与抗击穿区(比如p型场效晶体管区中的鳍状结构的抗击穿区)相邻时，会固定大量电荷于其表面(比如当衬垫层直接接触栅极结构时)，而电子在操作循环时通过静电吸引力维持在衬垫层表面附近以平衡电荷。这些额外电子会静电排斥相邻的抗击穿区中的n型掺质。这会降低抗击穿区的有效掺质剂量，进而减少其效果。如此一来，关闭状态的底部漏电流变得更明显。在操作循环之后，此效应通常增加关闭状态漏电流的程度。在应力测试条件下，热载子注入之后(模拟操作条件的工艺)的关闭状态漏电流，可比热载子注入之前的关闭状态漏电流增加几千倍。本发明实施例提供缓解电荷累积于抗击穿区上的衬垫层表面的效应，进而维持低关闭状态电流。
本发明实施例可用于采用衬垫层的任何合适半导体装置，比如互补式金属氧化物半导体场效晶体管、互补式金属氧化物半导体装置、p型金属氧化物半导体装置、n型金属氧化物半导体装置、鳍状场效晶体管、全绕式栅极金属氧化物半导体场效晶体管如纳米线装置或纳米片装置、或其他多栅极场效晶体管。本技术领域中普通技术人员应理解，本发明实施例有利于其他半导体装置的例子。在集成电路或其部分(其可包含静态随机存取存储器及/或逻辑电路、无源构件如电阻、电容、或电感、与有源构件如p型场效晶体管、n型场效晶体管、鳍状场效晶体管、互补式金属氧化物半导体场效晶体管、互补式金属氧化物半导体晶体管、双极晶体管、高电压晶体管、高频晶体管、其他存储器单元、或上述的组合)的工艺时，可制作半导体装置。
图1与图8A至8B分别为本发明实施例中，用于制作半导体装置的两种方法100A及100B的流程图。图2至7与图9至18分别为本发明实施例中，半导体装置于方法100A及100B的不同工艺阶段的剖视图。
如图1的步骤1010A与图2所示，接收初始的半导体结构10。初始的半导体结构10包括半导体基板101。在一些实施例中，半导体基板101包含半导体材料如基体硅或单晶硅。在其他实施例或额外实施例中，半导体基板101中可包含另一半导体元素如结晶结构的锗。半导体基板101亦可包含半导体化合物如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、或上述的组合。半导体基板101亦可包含绝缘层上半导体基板如绝缘层上硅基板、绝缘层上硅锗基板、或绝缘层上锗基板。可掺杂半导体基板101的部分(如n型掺杂区101A与p型掺杂区101B)。举例来说，n型掺杂区101A可掺杂n型掺质如磷或砷，而p型掺杂区101B可掺杂p型掺质如硼或三氟化硼。在所述实施例中，半导体基板101的上表面沿着X-Y平面延伸，且X-Y平面由X方向与Y方向定义。
初始的半导体结构10更包含鳍状结构103形成于n型掺杂区101A之中或之上，以及鳍状结构203形成于p型掺杂区101B之中或之上。鳍状结构103及203各自沿着Z方向延伸，且Z方向垂直于X-Y平面。可由任何合适方法图案化鳍状结构103及203。举例来说，可采用一或多道光刻工艺图案化鳍状结构，包括双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光刻与自对准工艺，其产生的图案间距小于采用单一的直接光刻工艺所得的图案间距。举例来说，一实施例可形成牺牲层于基板上，并采用光刻工艺图案化牺牲层。采用自对准工艺，沿着图案化的牺牲层的侧部形成间隔物。接着移除牺牲层，而保留的间隔物如芯之后可用于图案化鳍状结构103及203。
鳍状结构103各自具有基底部分102与通道部分110。在一实施例中，基底部分102与通道部分110可包含不同材料。举例来说，基底部分102可包含基体硅(如单晶硅)，而通道部分110可包含硅锗、锗、或上述的组合。鳍状结构203亦各自具有基底部分202与通道部分210。在一实施例中，基底部分202与通道部分210均包含基体硅(如单晶硅)。通道部分110及210在操作后续形成的晶体管时，可各自接合栅极结构并连接一对源极/漏极结构。举例来说，一对p型掺杂的源极/漏极结构将形成于通道部分110的两侧上，而一对n型掺杂的源极/漏极结构将形成于通道部分210的两侧上。
基底部分102各自包含抗击穿区112，其位于基底部分102与通道部分110之间的界面的正下方。类似地，基底部分202各自包含抗击穿区212，其位于基底部分202与通道部分210之间的界面的正下方。如上所述，抗击穿区112的n型掺质密度高于基底部分102的其他部分的n型掺质密度，而抗击穿区212的p型掺质密度高于基底部分202的其他部分的p型掺质密度。鳍状结构103及203各自具有上表面190及290以及侧壁表面192及292。在一些实施例中，鳍状结构103的基底部分102与通道部分110各自具有横向宽度172(在侧壁表面192之间沿着X方向的尺寸)，且鳍状结构203的基底部分202与通道部分210各自具有横向宽度272(在侧壁表面292之间)。横向宽度272可与横向宽度172相同或不同，端视设计需求而定。举例来说，一些实施例的横向宽度272可设计为大于横向宽度172，使后续形成的n型场效晶体管的横向宽度大于后续形成的p型场效晶体管的横向宽度，其可提供较佳的电流平衡及/或增加装置速度。
初始的半导体结构10还包括衬垫层108以包覆鳍状结构103及203。举例来说，衬垫层108可顺应性地(比如具有实质上相同的厚度)形成于鳍状结构103及203的上表面与侧表面上。衬垫层108可包含氮化硅。在所述实施例中，衬垫层106夹设于鳍状结构103与衬垫层108之间，以及鳍状结构203与衬垫层108之间。因此初始的半导体结构10可包含结合的衬垫层结构。衬垫层106可为任何合适的衬垫材料。在所述实施例中，衬垫层106为氧化硅的衬垫层。在一些实施例中(未图示)，可省略衬垫层106。衬垫层106及108的形成方法可为任何合适技术。举例来说，顺应性沉积衬垫层106及/或108的方法可为毯覆性沉积工艺如化学气相沉积、原子层沉积、或类似工艺。在其他实施例中，可由热氧化工艺形成氧化硅的衬垫层，比如在湿式环境中加热初始的半导体结构10。衬垫层106及/或108的厚度选择取决于设计需求，其可介于约1nm至约5nm之间。若衬垫层厚度过小(比如小于1nm)，则衬垫层可能无法可信地符合其设计功能(比如阻挡层、黏着层、及/或保护鳍状结构免于氧化)。相反地，若厚度过大(比如大于5nm)，则厚衬垫层可能会占据相邻鳍状结构之间用于沉积介电层的空间，其可能造成介电层中的空洞。
初始的半导体结构10还包括介电层104形成于半导体基板101上且围绕鳍状结构103及203。可依序处理介电层104成隔离结构，比如浅沟槽隔离结构。在一些实施例中，介电层104的形成方法包括将一或多种介电材料如氧化硅、氮化硅、氮氧化硅、其他合适材料、或上述的组合填入鳍状结构103及203之间的沟槽。沉积介电层104的方法可为任何合适方法，比如化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、电浆辅助化学气相沉积工艺、电浆辅助原子层沉积工艺、或上述的组合。在其他实施例中，介电层104的形成方法可采用任何其他传统的隔离技术。在所述实施例中，介电层104主要包含氧化硅。
如图1的步骤1020A与图3所示，使介电层104与衬垫层106及108凹陷，以分别形成凹陷的介电层104、凹陷的衬垫层106、与凹陷的衬垫层108。凹陷工艺可实施任何合适的凹陷技术，比如湿蚀刻技术、干蚀刻技术、或上述的组合。与此同时，凹陷工艺可露出鳍状结构103及203的部分。综上所述，露出鳍状结构103及203的上表面190及290，以及鳍状结构103及203的侧壁表面192及292。具体而言，通道部分110与抗击穿区112(至少其顶部)暴露于n型掺杂区101A上，且通道部分210与抗击穿区212(至少其顶部)暴露于p型掺杂区101B上。综上所述，衬垫层106及108的上表面延伸于n型掺杂区101A上的抗击穿区112的上表面与下表面之间，并延伸于p型掺杂区101B上的抗击穿区112的上表面与下表面之间。然而如下所述，一些实施例中的衬垫层106及108其上表面延伸的水平可能低于抗击穿区112及212的下表面。如下详述，衬垫层108上的固定电荷对衬垫层108至少部分露出的抗击穿区112的影响，小于对衬垫层108完全覆盖抗击穿区112的影响。这有助于改善(比如降低)关闭状态的漏电流。
如图1的步骤1030A与图4所示，横向修整(或薄化)鳍状结构103及203的露出部分，使其各自具有缩小的横向宽度。在一些实施例中，实施修整工艺可控制鳍状结构103及203的尺寸以达所需的关键尺寸，并维持较宽的下侧部分以确保鳍状结构的稳定性。修整工艺可实施任何合适的修整技术。修整工艺造成鳍状结构103的通道部分110各自具有新的侧壁表面158，且鳍状结构203的通道部分210各自具有新的侧壁表面258。通道部分110在相对的侧壁表面158之间具有横向宽度182，其小于对应的横向宽度172。类似地，通道部分210各自在相对的侧壁表面258之间具有横向宽度282，其小于对应的横向宽度272。通道部分110及210之后可作为后续形成的晶体管的通道区。综上所述，横向宽度182及282可分别视作通道宽度。在一些实施例中，横向宽度182可与横向宽度282相同或不同，可视设计需求而定。举例来说，一些实施例的横向宽度282可设计为大于横向宽度182，以增加装置速度。
如图4所示，修整的鳍状结构103及203分别包括肩部表面150及250。这些肩部表面各自与相邻的鳍状结构的垂直侧壁之间具有角度。举例来说，肩部表面150与鳍状结构103的侧壁表面158之间具有角度168，而肩部表面250与鳍状结构203的侧壁表面258之间具有角度268。在一些实施例中，角度168及268各自为约90°至约180°。若角度168或268过小(比如小于90°)，后续沉积的盖层将无法可信地覆盖修整的鳍状结构103及203的整个表面。如此一来，可能形成空洞并劣化装置效能。在一些实施例中，修整工艺亦可分别调整鳍状结构103及203的上表面190及290的轮廓，使其轮廓比修整工艺之前的轮廓更圆润。
在所述实施例中，在修整工艺时部分地修整抗击穿区112及212。综上所述，抗击穿区112的顶部(比如高于衬垫层108的上表面延伸的水平的部分)的横向宽度与通道部分110一致，比如与横向宽度182大致相同。抗击穿区112的底部(比如低于衬垫层108的上表面延伸的水平的部分)的横向宽度与基底部分102一致，比如与横向宽度172大致相同。类似地，抗击穿区212的顶部的横向宽度与通道部分210一致，及与横向宽度282大致相同。抗击穿区212的底部的横向宽度与基底部分202一致，其与横向宽度272大致相同。换言之，抗击穿区112及212各自具有较宽的下侧部分与较窄的顶部，且抗击穿区112及212的侧壁各自具有露出的阶状轮廓(包含肩部表面150及250)。
如图1的步骤1040A与图5所示，顺应性地形成盖层114A于修整的鳍状结构103及203的露出表面上。换言之，在n型掺杂区101A上，盖层114A可包覆通道部分110其露出的上表面与侧表面，以及基底部分102其露出的侧表面。抗击穿区112的肩部表面150可与盖层114A直接交界。在p型掺杂区101B上，盖层114A可包覆通道部分210其露出的上表面与侧表面，以及基底部分202其露出的侧表面。抗击穿区212的肩部表面250与盖层114A直接交界。在所述实施例中，盖层114A为含硅层如结晶硅、多晶硅、或非晶硅。然而盖层114A可为任何合适的盖层材料。在一些实施例中，盖层114A保护通道部分110(比如硅锗材料)在后续处理时免于氧化。
如图1的步骤1050A与图6所示，进行退火工艺已将盖层114A转换成盖层114。在所述实施例中，退火工艺可将含硅的盖层114A转换成氧化物的盖层114(比如具有氧化硅)，且实质上不改变盖层轮廓。综上所述，与盖层114A相关的上述物理结构亦可用于盖层114。如图6所示，盖层114的下侧部分114B分别形成于肩部表面150及250上并与其直接交界。在一些实施例中，氧化物的盖层114可避免或消除通道部分110及/或210的组成与后续形成的栅极构件之间的扩散及/或反应(如下所述)。在一些实施例中，盖层114可作为界面层以改善鳍状结构与后续形成的栅极介电层之间的黏着性。在一些实施例中，界面层的存在实质上不损伤(有时可改善)电性接点，其位于其两侧上的两种材料之间。退火工艺可采用任何合适参数。在一些实施例中，退火工艺的温度可为约700℃至约1500℃。
如图1的步骤1060A与图7A至7C所示，形成栅极结构140以接合鳍状结构103的通道部分110与鳍状结构203的通道部分210。如图1的步骤1070A所示，完成制作半导体装置。在所述实施例中，栅极结构140延伸高于并越过鳍状结构103及203。栅极结构140包括栅极介电层116顺应性地形成于盖层114(含下侧部分114B)上并与其交界(见图6)。在一些实施例中，栅极介电层116为高介电常数的栅极介电层。高介电常数的介电层包含的介电材料其介电常数大于氧化硅的介电常数(近似3.9)。举例来说，栅极介电层116可包含氧化铪，其介电常数为约18至约40。在多种其他例子中，栅极介电层116可包含氧化锆、氧化钇、氧化镧、氧化钆、氧化钛、氧化钽、氧化铪铒、氧化铪镧、氧化铪钇、氧化铪钆、氧化铪铝、氧化铪锆、氧化铪钛、氧化铪钽、氧化锶钛、或上述的组合。栅极介电层116的形成方法可为任何合适工艺如化学气相沉积、物理气相沉积、原子层沉积、或上述的组合。
栅极结构140更包含栅极层118形成于栅极介电层116上。栅极层118可包含任何合适材料，比如氮化钛、氮化钽、钛铝、氮化钛铝、钽铝、氮化钽铝、碳化钽铝、碳氮化钽、铝、钨、铜、钴、镍、铂、或上述的组合。
如上所述，衬垫层108可包含氮化硅，且可固定正电荷于其上表面。这些固定电荷在操作循环时会捕获电子(由于栅极结构与衬垫层之间的直接接触)。这些额外电子可与抗击穿区112的n型掺质产生静电交互作用。然而抗击穿区112的不同部分上的静电相互作用程度可不同。举例来说，抗击穿区112的顶部远离固定电荷，且抗击穿区112的底部与固定电荷相邻。由于静电相互作用与两种相互作用的带电荷物种之间的距离平方成反比，抗击穿区112的顶部中的掺质上的固定电荷效应，实质上小于抗击穿区112的底部中的掺质上的固定电荷效应。此外，这效应亦实质上小于衬垫层108覆盖顶部的全部侧表面的设置。如上所述，静电相互作用会降低抗击穿区112的效果。如此一来，通过设置抗击穿区112的顶部远离衬垫层108，可改善抗击穿区112的效果并最小化关闭状态的漏电流。
如图7A所示，衬垫层108的上表面与通道部分110及210的下表面之间的距离(沿着正交于半导体基板101的表面的方向)为距离120。在一些实施例中，距离120小于约30nm。若距离120过大，比如大于约30nm，则相邻鳍状物的底部之间的空间狭窄，且在避免鳍状物之间的短接电路时可能产生挑战。在一些实施例中，距离120大于约20nm。综上所述，大部分的抗击穿区112及212远离固定电荷。如此一来，可最小化静电吸引力的效果。在一实施例中，抗击穿区112及212的厚度为距离122，且衬垫层108的上表面与抗击穿区112及212的下表面之间的距离为距离124。如图7A所示，距离122大于距离120，并等于距离120与距离124的总和。在此例中，抗击穿区112及212的下表面延伸高于介电层104的上表面。
图7B显示其他实施例。举例来说，距离122可小于距离120。综上所述，间隙具有衬垫层108的上表面与抗击穿区112的下表面之间的距离124。换言之，累积于衬垫层108的上表面的固定电荷远离整个抗击穿区112。综上所述，与图7A所示的实施例相较，可进一步降低固定电荷造成的静电相互作用。
虽然图7A及7B显示抗击穿区112及212的下侧表面延伸高于介电层104的上表面，但此非永远必要。举例来说，图7C显示的实施例通常类似于图7A的实施例。然而抗击穿区112及212的下表面延伸低于介电层104的上表面。因此这实施例提供的抗击穿区尺寸大于图7A及7B所示。在一些实施例中，此实施例具有优点，因为较大的抗击穿区可容纳较大量的初始掺质。
依据上述实施例形成的装置的关闭状态漏电流，实质上低于其他方法形成的装置(比如氮化硅衬垫层覆盖抗击穿区112的全部侧壁表面)的关闭状态漏电流。在一实施例中，依据图7A设置半导体结构10，且距离120为约5nm。换言之，抗击穿区112的顶部其高度为约5nm，并经由盖层114与栅极结构140相邻。在应变测试时，施加-2.3B的负偏压至装置约1000秒。在热载子注入之后的关闭状态电流，比热载子注入之前的关闭状态电流小100倍。与此相较，具有衬垫层108覆盖抗击穿区112的完整侧表面的装置在相同的应力测试条件下，热载子注入后的关闭状态电流增加几乎10000倍。换言之，通过保留抗击穿区的部分暴露至栅极结构(经由盖层114)，可实质上缓解关闭状态的漏电流(比如减少几百倍)。
上述实施例可暴露抗击穿区112的顶部至栅极结构140(经由盖层114而非夹设于衬垫层108之间)，及/或保留间隙于抗击穿区112与衬垫层108的上表面之间，以减轻电荷捕获。图8A及18与图9至17所示的其他实施例中，以方法100B制作类似的半导体结构20A。在半导体结构20A中，衬垫层108与栅极结构隔离有介电材料。因此在操作循环应力时，固定正电荷不会捕获衬垫层108的表面上的电子，且不会影响抗击穿层112的剂量，不论衬垫层108的相对位置为何。
如图8A的步骤1010B至1030B与图9至11所示，对初始的半导体结构20A进行工艺，以分别形成鳍状结构103及203于n型掺杂区101A及p型掺杂区101B之中或之上。方法100B与方法100A类似的部分已搭配图1至7说明如上。举例来说，图9的装置结构类似于图2所示的结构，且图10的装置结构类似于图3所示的结构。此外，图11所示的装置结构通常类似于图4所示的结构。举例来说，鳍状结构103及203各自包含基底部分102及202与通道部分110及210。此外，鳍状结构103的基底部分102与鳍状结构203的基底部分202各自具有横向宽度172及272，且鳍状结构103的通道部分110与鳍状结构203的通道部分210各自具有横向宽度182及282。如上所述，横向宽度182小于横向宽度172，且横向宽度282小于横向宽度272。鳍状结构103及203亦可自包含抗击穿区112及212。在所述实施例中，图11与图4的差距在于凹陷的衬垫层106及108垂直延伸至通道部分110及210的下表面(其亦为抗击穿区112及212的上表面)。换言之，抗击穿区112及212没有任何部分凹陷。综上所述，抗击穿区112及212具有平滑的侧壁轮廓，不同于图4所示的阶状轮廓。此外，通道部分110及210未分别覆盖抗击穿区112及212的上表面的一部分(如肩部表面150及250)。在所述实施例中，角度168及268各自为约90°。然而其他设置亦属可能，如下所述。举例来说，角度168及268可大于约90°并小于约180°。
如图8A的步骤1040B与图12所示，沉积介电层404于介电层104上以及修整的鳍状结构103及203上。介电层404覆盖全部的鳍状结构103及203。综上所述，介电层404的上表面延伸高于鳍状结构103及203的上表面。介电层404与介电层104的组合可形成隔离结构。在图12所示的实施例中，鳍状结构103及203各自具有通道高度310，且介电层404延伸高于鳍状结构103及203的上表面的距离为高度312。在一些实施例中，高度312与通道高度310的比例大于约0.4至约0.6。若比例过低，比如低于约0.4至约0.6，后续的平坦化工艺可能影响鳍状结构103及203的完整性。
如图8A的步骤1050B与图13所示，在介电层404上进行化学机械研磨工艺。此工艺可平坦化介电层404的上表面，以用于后续工艺。平坦化的介电层404延伸高于鳍状结构103及203的上表面的高度为高度314。综上所述，鳍状结构103及203完全埋置于介电层404的上表面之下。
如图8B的步骤1060B与图14所示，使介电层404凹陷以露出修整的鳍状结构103及203的一部分。然而凹陷工艺不完全移除介电层404且保留介电层404的一部分，使衬垫层108完全埋置于介电层404之下。举例来说，介电层404维持覆盖肩部表面150及250。如上所述，衬垫层108延伸低于肩部表面150及250。因此衬垫层108与任何后续形成的层状物(包含栅极结构)隔离。此设置具有优点，因为后续形成的栅极结构与衬垫层108分开。综上所述，施加至栅极结构的任何偏压不再造成电子实质上累积于衬垫层108的表面(由于不存在正电荷的实质累积)，不论衬垫层的材料为何。如此一来，降低抗击穿区112的有效剂量的静电相互作用不存在。因此可最小化关闭状态的漏电流。在一些实施例中，介电层404的上表面延伸高于衬垫层108的上表面的距离可为距离308。距离308为约1nm至约3nm。若距离308过小(比如小于1nm)，则薄介电层404可能无法作为有效阻挡层，且无法避免衬垫层108的上表面捕获电子。若距离308过大，则后续形成的栅极结构140无法有效控制通道的大部分。
如图8B的步骤1070B至1080B与图15及16所示，形成盖层114A于露出的修整的鳍状结构103及203上，接着退火盖层114A以形成盖层114。这与图1中的步骤1040A及1050A类似。如图8B的步骤1090B与图17所示，形成栅极结构140于介电层404上与盖层114上。这与图1的步骤1060A类似。如图8B的步骤1100B所示，完成制作半导体装置。图17的装置结构通常类似于图7A、7B、及/或7C的装置结构。图17与图7A、7B、及/或7C的差别在于介电层404的上表面延伸高于衬垫层108的上表面。
虽然图17所示的抗击穿区112及212的上表面各自沿着衬垫层108的上表面延伸，但其他设置亦属可能。图18显示半导体结构20B、20C、20D、20E、20F、与20G等其他实施例，但不局限于此。图18仅说明n型掺杂区101A中的半导体结构10的部分，以求说明清楚与简化。如图18所示，抗击穿区的位置与尺寸不同于图17所示。举例来说，抗击穿区112的上表面可延伸高于、齐平、或低于介电层404的上表面。举例来说，抗击穿区112的下表面亦可延伸高于、齐平、或低于介电层404的下表面。
此处所述的方法不只用于此技术节点，亦可用于之后发展的新技术节点。对关键尺寸小于5nm的技术节点而言，需最佳化衬垫层厚度。举例来说，衬垫层108的厚度可为约1nm至约5nm。若厚度过大(比如大于5nm)，图8A及8B所示的上述介电层404可能无法可信地填入鳍状结构之间的开口。若厚度过小(比如小于1nm)，则衬垫层106及/或衬垫层108可能不足以符合其设计功能(比如阻挡层、黏着层、及/或保护鳍状结构免于氧化)。
本发明实施例可提供优点至半导体工艺与半导体装置，但不局限于此。举例来说，公开的方法可缓解或消除抗击穿区上的氮化硅衬垫层的固定电荷的效应。对具体例子而言，氮化硅衬垫层只部分地覆盖抗击穿区的侧壁表面。因此抗击穿区的一部分远离固定电荷，并经由盖层暴露至栅极结构。对另一具体例子而言，氮化硅衬垫层与栅极结构隔离有介电材料。因此，衬垫层表面上不再捕获电子。综上所述，不再影响抗击穿区。综上所述，可维持抗击穿区的完整性与效果，并最小化关闭状态的底部漏电流。这有助于提高整体的装置电源效率。如此一来，本发明提供的方法可改善半导体装置的效能、功能、及/或可信度。
本发明一实施例关于半导体装置，其包括半导体基板与位于半导体基板上的鳍状结构。鳍状结构包括由第一材料制成的底部与由第二材料制成的顶部。第一材料与第二材料不同。半导体装置亦包括位于底部的侧壁上的衬垫层。衬垫层的上表面延伸低于顶部的下表面。半导体装置还包括位于半导体基板上与衬垫层的侧表面上的介电层，以及界面层。界面层具有第一部分以及第二部分，第一部分设于底部的侧壁表面上并与其直接接触，第二部分设于顶部的上表面与侧壁表面上并与其直接接触。半导体装置亦包括位于介电层上的栅极结构，并接合鳍状结构。栅极结构包括高介电常数的介电层，与高介电常数的介电层上的金属栅极。高介电常数的介电层直接接触界面层的第一部分。
在一些实施例中，衬垫层的上表面与顶部的下表面之间沿着垂直于半导体基板的上表面的第一方向的距离为约1nm至约5nm。在一些实施例中，衬垫层包括氮化硅。在一些实施例中，第一材料包括单晶硅，且第二材料包括硅锗。在一些实施例中，顶部为p型晶体管的通道区。在一些实施例中，鳍状结构为第一鳍状结构，且半导体装置还包括第二鳍状结构。第二鳍状结构的顶部为n型晶体管的通道区且包含第一材料。在一些实施例中，底部包括具有n型掺质的抗击穿区，抗击穿区与顶部以及界面层的第一部分交界。界面层的第一部分夹设于高介电常数的介电层与抗击穿区之间。在一些实施例中，抗击穿区的上表面远离衬垫层的上表面。
本发明一实施例关于半导体装置，其包括半导体基板、鳍状结构、衬垫层、介电层以及栅极结构；鳍状结构位于半导体基板上；衬垫层位于鳍状结构的侧壁上；介电层位于半导体基板上并覆盖衬垫层的上表面与侧表面；栅极结构位于介电层上并接合鳍状结构的通道部分。
在一些实施例中，介电层的一部分夹设于栅极结构与衬垫层之间并分隔栅极结构与衬垫层。在一些实施例中，上述侧壁为鳍状结构的第一侧壁，并沿着实质上垂直于半导体基板的上表面的第一方向延伸。鳍状结构包括第二侧壁，其位于鳍状结构与衬垫层的上表面相邻的肩部区域中。第二侧壁沿着第二方向延伸。此外，第一方向与第二方向定义的角度介于90°至180°之间。肩部区域埋置于介电层中。在一些实施例中，通道部分连接掺杂第一导电型态的第一掺质的一对源极/漏极结构，以及鳍状结构包括抗击穿区以与肩部区域相邻。抗击穿区掺杂第二导电型态的第二掺质，且第二导电型态与第一导电型态相反。在一些实施例中，鳍状结构包括通道部分之下的基底鳍状部分。基底鳍状部分包括第一半导体材料。通道部分包括第二半导体材料，且第一半导体材料与第二半导体材料不同。在一些实施例中，鳍状结构为第一鳍状结构。半导体装置还包括第二鳍状结构。第二鳍状结构包括延伸整个第二鳍状结构的高度的第一半导体材料。在一些实施例中，衬垫层包括氮化硅。
本发明一实施例关于半导体装置的形成方法，其包括接收半导体结构。半导体结构包括半导体基板、鳍状结构、衬垫层以及第一介电层；鳍状结构位于半导体基板上；衬垫层位于鳍状结构的侧壁上；第一介电层位于半导体基板与衬垫层的侧表面上。方法亦包括使第一介电层与衬垫层凹陷，以形成凹陷的第一介电层与凹陷的衬垫层，并露出鳍状结构的第一部分。方法还包括沉积第二介电层于第一介电层与修整的鳍状结构上。第二介电层的上表面延伸高于修整的鳍状结构的上表面。此外，方法包括使第二介电层凹陷以露出修整的鳍状结构的第二部分。凹陷的第二介电层的上表面延伸高于凹陷的衬垫层的上表面并低于修整的鳍状结构的上表面。方法额外包括形成栅极结构于凹陷的第二介电层与修整的鳍状结构上，使栅极结构接合鳍状结构的通道部分。
在一些实施例中，修整的鳍状结构的第一高度定义为凹陷的衬垫层的上表面与修整的鳍状结构的上表面之间的距离。第二介电层的一部分的第二高度定义为修整的鳍状结构的上表面与第二介电层的上表面之间的距离。此外，第二高度与第一高度的比例大于0.5。在一些实施例中，鳍状结构为第一鳍状结构。第一鳍状结构包含第一材料的基底鳍状部分与第二材料的通道部分。第一材料与第二材料不同。此外，基底鳍状部分还包括具有第一掺质的第一抗击穿区。此外，接收的半导体结构还包括第二鳍状结构，第二鳍状结构的整个高度为第一材料，且第二鳍状结构包括具有第二掺质的第二抗击穿区。第一掺质与第二掺质的导电型态相反。在一些实施例中，方法还包括修整鳍状结构的露出的第一部分，以形成修整的鳍状结构；以及在第二介电层上进行化学机械研磨工艺。在一些实施例中，修整鳍状结构的露出的第一部分的步骤形成与衬垫层的上表面相邻的肩部区域。肩部区域的肩部墙与侧壁的角度介于90°至180°之间。此外，使第二介电层凹陷的步骤包括以凹陷的第二介电层维持覆盖肩部墙。
上述实施例的特征有利于本技术领域中普通技术人员理解本发明。本技术领域中普通技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中普通技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。

Claims (1)

1.一种半导体装置，其特征在于，包括：
一半导体基板；
一鳍状结构，位于该半导体基板上，该鳍状结构包括一由第一材料制成的一底部与一由第二材料制成的一顶部，且该第一材料与该第二材料不同；
一衬垫层，位于该底部的侧壁上，其中该衬垫层的上表面延伸低于该顶部的下表面；
一介电层，位于该半导体基板上与该衬垫层的侧表面上；
一界面层，具有一第一部分以及一第二部分，该第一部分设于该底部的侧壁表面上并与其直接接触，该第二部分设于该顶部的上表面与侧壁表面上并与其直接接触；以及
一栅极结构，位于该介电层上并接合该鳍状结构，
其中该栅极结构包括一高介电常数的介电层，与该高介电常数的介电层上的一金属栅极，以及
其中该高介电常数的介电层直接接触该界面层的该第一部分。
CN202011023396.3A 2019-09-26 2020-09-25 半导体装置 Pending CN112563269A (zh)

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