CN112563137A - Antimonide high electron mobility transistor and preparation method thereof - Google Patents
Antimonide high electron mobility transistor and preparation method thereof Download PDFInfo
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- CN112563137A CN112563137A CN202011438021.3A CN202011438021A CN112563137A CN 112563137 A CN112563137 A CN 112563137A CN 202011438021 A CN202011438021 A CN 202011438021A CN 112563137 A CN112563137 A CN 112563137A
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- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 title claims abstract description 101
- 238000002360 preparation method Methods 0.000 title abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 230000000903 blocking effect Effects 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 349
- 238000002955 isolation Methods 0.000 claims description 39
- 239000002131 composite material Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 239000000463 material Substances 0.000 description 18
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 15
- 239000013078 crystal Substances 0.000 description 9
- 206010062575 Muscle contracture Diseases 0.000 description 8
- 208000006111 contracture Diseases 0.000 description 8
- 229910017115 AlSb Inorganic materials 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
The invention discloses an antimonide high electron mobility transistor and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate; forming an electron blocking layer on the surface of the substrate; and forming an antimonide epitaxial structure on the surface of the electron blocking layer. By designing and introducing an electron barrier layer between the antimonide epitaxial structure and the substrate, the problems that the diffusion of atoms in the substrate to an upper layer structure possibly causes device electric leakage, the uncontrollable diffusion of the substrate atoms increases the control difficulty of the electron concentration in a channel layer and the like are solved; the antimonide epitaxial structure not only ensures the normal work of the whole antimonide high-molecular mobility transistor, but also relieves the problem of lattice mismatch between a common substrate and an upper antimonide, thereby effectively improving the electron concentration of the channel of the antimonide high-electron mobility transistor and the electron mobility of the antimonide high-electron mobility transistor at room temperature.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an antimonide high-electron-mobility transistor and a preparation method thereof.
Background
Among High-speed compound semiconductor devices, a High Electron Mobility Transistor (HEMT) plays a significant role in terms of excellent performance such as High transconductance, low threshold voltage, High current cut-off frequency, and low gate leakage current, and the High electron mobility transistor based on a group iii-v compound semiconductor has been drawing continuous attention in recent years for applications to microwave and millimeter wave devices, monolithic integrated circuits, and logic integrated circuits.
The antimonide system material is an application material of a third-generation high-electron-mobility transistor, a narrow-band-gap material represented by InSb and InAsSb is taken as a channel layer, the carrier mobility and the saturation drift rate higher than those of GaAs and InP can be achieved, and the application potential in the high-frequency and high-speed field is huge. The carrier concentration and mobility of the channel layer are critical factors that determine device performance. However, the substrate of the conventional antimonide high electron mobility transistor adopts an InP or antimonide substrate which is relatively difficult to process and integrate, although Si is adopted as the substrate in some of the prior art, lattice mismatch still exists, the lattice mismatch can cause the electron mobility of a device channel layer to be reduced, and Si atom diffusion easily causes a leakage phenomenon in an upper layer structure.
Disclosure of Invention
Therefore, it is necessary to provide an antimonide high electron mobility transistor and a manufacturing method thereof to solve the problem of lattice mismatch between an antimonide and a substrate, and to eliminate the problem of device leakage caused by atomic diffusion in the substrate, thereby greatly improving the electron mobility of a channel layer.
In order to solve the above technical problem, a first aspect of the present application provides a method for manufacturing an antimonide high electron mobility transistor, including:
providing a substrate;
forming an electron blocking layer on the surface of the substrate;
and forming an antimonide epitaxial structure on the surface of the electron blocking layer.
In the preparation method of the antimonide high-electron-mobility transistor in the embodiment, the electron blocking layer and the antimonide epitaxial structure are sequentially formed on the provided substrate, and the electron blocking layer is designed and introduced between the antimonide epitaxial structure and the substrate, so that the problems of device electric leakage possibly caused by diffusion of atoms in the substrate to an upper layer structure, difficulty in controlling electron concentration in a channel layer increased by uncontrollable diffusion of atoms in the substrate and the like are solved; the antimonide epitaxial structure not only ensures the normal work of the whole antimonide high-molecular mobility transistor, but also relieves the problem of lattice mismatch between a common substrate and an upper antimonide, thereby effectively improving the electron concentration of the channel of the antimonide high-electron mobility transistor and the electron mobility of the antimonide high-electron mobility transistor at room temperature.
In one embodiment, the electron blocking layer comprises a P-type doped InAlSb layer.
In one embodiment, the forming of the antimonide epitaxial structure on the surface of the electron blocking layer includes:
forming a composite buffer layer on the surface of the electron blocking layer;
forming a channel layer on the surface of the composite buffer layer;
forming an antimonide isolation layer on the surface of the channel layer;
forming a barrier layer on the surface of the antimonide isolation layer;
and forming a cap layer on the surface of the barrier layer.
In one embodiment, the forming a composite buffer layer on the surface of the electron blocking layer includes:
forming a superlattice buffer layer on the surface of the electron blocking layer;
forming an inserting buffer layer on the surface of the superlattice buffer layer;
the inserting buffer layer comprises a first inserting buffer layer and a second inserting buffer layer arranged between the first inserting buffer layer and the adjacent first inserting buffer layer.
In the preparation method of the antimonide high electron mobility transistor in the embodiment, the effect of filtering lattice mismatch dislocation is optimized by strictly controlling the superlattice period number of the superlattice buffer layer; the interpenetration buffer layer blocks larger dislocation which can not be filtered by the superlattice buffer layer, such as contracture crystal and stacking fault, and plays a role in effectively decomposing contracture crystal defects and bending; the combination of the superlattice buffer layer and the interpenetration buffer layer efficiently solves the problem of lattice mismatch between the substrate and the channel layer, and improves the electron mobility of the channel layer of the antimonide high-electron-mobility transistor.
Further, the first interposed buffer layer comprises InAlxA Sb layer, the second interpenetration buffer layer comprising InAlyAnd in the Sb layer, the value range of x is 0.1-0.25, and the value range of y is 0.2-0.4.
In one embodiment, after the composite buffer layer and before the channel layer is formed, the method further includes:
forming a first doping layer on the surface of the composite buffer layer;
forming a first protective layer on the surface of the first doped layer;
and forming a doped isolation layer on the surface of the first protection layer.
In the preparation method of the antimonide high electron mobility transistor in the above embodiment, the first doping layer, the first protection layer and the doping isolation layer are sequentially disposed on the composite buffer layer, and at the moment when the first doping layer is deposited on the composite buffer layer, the element penetrating through the buffer layer to provide electrons is replaced, and n-type carriers, i.e., electrons, are provided as an n-type doping source; the first protective layer ensures that atoms of the first doping layer deposited at the early stage are not suddenly heated by the substrate to activate the doping atoms to form a p-type doping source; the doped isolation layer separates the channel layer from the n-type doped source, so that impurity ionization scattering is greatly reduced, and the electron mobility is improved.
Further, the first doping layer includes a deposition layer of Si atoms, and before the first doping layer is formed on the surface of the composite buffer layer, the method further includes:
and adjusting the temperature of the substrate with the composite buffer layer to a preset temperature, wherein the preset temperature is 280-320 ℃.
In one embodiment, after the antimonide isolation layer and before the barrier layer is formed, the method further comprises:
forming a second doping layer on the surface of the antimonide isolation layer;
and forming a second protective layer on the surface of the second doped layer.
A second aspect of the present application provides an antimonide high electron mobility transistor, comprising: the substrate, the electron blocking layer and the antimonide epitaxial structure are sequentially stacked.
Further, the antimonide epitaxial structure comprises: the composite buffer layer, the first doping layer, the first protection layer, the doping isolation layer, the channel layer, the antimonide isolation layer, the second doping layer, the second protection layer, the barrier layer and the cap layer are sequentially stacked.
In the antimonide high electron mobility transistor in the above embodiment, the electron blocking layer, the composite buffer layer, the first doping layer, the first protection layer, the doping isolation layer, the channel layer, the antimonide isolation layer, the second doping layer, the second protection layer, the barrier layer and the cap layer are sequentially formed on the provided substrate, so that the structure not only greatly improves the electron mobility of the channel layer of the antimonide high electron mobility transistor, but also stably improves the stability and reliability of the whole device.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a schematic flow chart of a method for manufacturing an antimonide high electron mobility transistor according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of an antimonide high electron mobility transistor provided in an embodiment of the present application;
FIG. 3 is a schematic flow chart of forming an antimonide epitaxial structure provided in an embodiment of the present application;
FIG. 4 is a cross-sectional structural view of an antimonide epitaxial structure provided in an embodiment of the present application;
FIG. 5 is a schematic flow chart of forming a composite buffer layer according to an embodiment of the present disclosure;
FIG. 6 is a schematic cross-sectional view of a composite buffer layer provided in an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a composite buffer layer provided in another embodiment of the present application;
fig. 8 is a schematic flow chart illustrating a process after forming a composite buffer layer and before forming a channel layer according to an embodiment of the present disclosure;
FIG. 9 is a schematic flow chart of a process after formation of an antimonide spacer layer and before formation of a barrier layer as provided in an embodiment of the present application;
fig. 10 is a schematic cross-sectional structure diagram of an antimonide high electron mobility transistor provided in another embodiment of the present application.
Description of reference numerals: 10-substrate, 20-electron blocking layer, 30-antimonide epitaxial structure, 31-composite buffer layer, 311-superlattice buffer layer, 312-interpenetration buffer layer, 3121-first interpenetration buffer layer, 3122-second interpenetration buffer layer, 32-channel layer, 33-antimonide isolation layer, 34-barrier layer, 35-cap layer, 40-first doping layer, 50-first protection layer, 60-doping isolation layer, 70-second doping layer and 80-second protection layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In order to explain the technical solution of the present application, the following description will be given by way of specific examples.
The preparation method of the antimonide High-electron-mobility transistor provided by the application is completed in an Ultra-High Vacuum system (UHV), and the pressure is less than 10-8Pa, the ultrahigh vacuum system can be an ultrahigh vacuum system equipped with a molecular beam epitaxial growth device, and when the film is epitaxially grown, a certain ultrahigh vacuum state is kept, so that the molecular beam epitaxial growth of the high-quality film is facilitated. The substrate used by the molecular beam epitaxy technology is low in temperature, the film layer growth rate is low, the beam intensity is easy to accurately control, the film layer components and the doping concentration can be rapidly adjusted along with the source change, and a single crystal film of one atomic layer and an ultrathin quantum microstructure material formed by alternately growing films with different components and different dopings can be prepared.
In a method for manufacturing an antimonide high electron mobility transistor provided in an embodiment of the present application, as shown in fig. 1, the method includes the following steps:
s10: providing a substrate 10;
s20: forming an electron blocking layer 20 on the surface of the substrate 10;
s30: an antimonide epitaxial structure 30 is formed on the surface of the electron blocking layer 20.
In the preparation method of the antimonide high-electron-mobility transistor in the embodiment, the electron blocking layer and the antimonide epitaxial structure are sequentially formed on the provided substrate, and the electron blocking layer is designed and introduced between the antimonide epitaxial structure and the substrate, so that the problems of device electric leakage possibly caused by diffusion of atoms in the substrate to an upper layer structure, difficulty in controlling electron concentration in a channel layer increased by uncontrollable diffusion of atoms in the substrate and the like are solved; the antimonide epitaxial structure not only ensures the normal work of the whole antimonide high-molecular mobility transistor, but also relieves the problem of lattice mismatch between a common substrate and an upper antimonide, thereby effectively improving the electron concentration of the channel of the antimonide high-electron mobility transistor and the electron mobility of the antimonide high-electron mobility transistor at room temperature.
In one embodiment, as shown in FIG. 2, the substrate 10 provided in step S10 includes at least a Si substrate, an antimonide substrate, or an InP substrate, among others. Preferably, a Si substrate which is low in cost and easy to obtain is selected as the substrate, and in addition, the Si substrate is simple in packaging process, can be used for large-size epitaxy, is suitable for industrial application, and greatly reduces the workload in the later period.
In one embodiment, with continued reference to fig. 2, the material of the electron blocking layer 20 formed in step S20 may be any one or a combination of two or more of InSb, AlSb, InAlSb and AlGaSb. Preferably, the electron blocking layer 20 is made of InAlSb material with the highest lattice matching degree, and P-type doping is performed on the InAlSb material to form the electron blocking layer. Wherein the P-type doping source can Be doped with Be, Mg, etc., with a doping concentration of 1016/cm3～1019/cm3. Specifically, the doping concentration may be 1016/cm3、1017/cm3、1018/cm3、1019/cm3. The P-type doped InAlSb layer has the advantages that on one hand, atoms in the Si substrate diffuse upwards to form doping to cause leakage of an n-type device, and on the other hand, the difficulty in controlling the electron concentration of the channel layer due to the fact that the Si atoms diffuse uncontrollably is avoided.
As an example, the molar content of Al in the InAlSb of the electron blocking layer is 0.1-0.3, the thickness is 500nm-800nm, and the growth temperature is 400 ℃ -440 ℃.
In a method for manufacturing an antimonide high electron mobility transistor provided in an embodiment of the present application, as shown in fig. 3, step S30: the formation of the antimonide epitaxial structure on the surface of the electron blocking layer comprises the following steps:
step S31: forming a composite buffer layer 31 on the surface of the electron blocking layer 20;
step S32: forming a channel layer 32 on the surface of the composite buffer layer 31;
step S33: forming an antimonide isolation layer 33 on the surface of the channel layer 32;
step S34: forming a barrier layer 34 on the surface of the antimonide isolation layer 33;
step S35: a cap layer 35 is formed on the surface of the barrier layer 34.
In one embodiment, as shown in fig. 4, the material of the channel layer 32 formed in step S32 includes any one of InSb, InAsSb, or InAlSb. Preferably, the material of the channel layer is InSb, the thickness is 30nm-50nm, the growth temperature is 400 ℃ -440 ℃, and the forbidden band width Eg is 0.17 eV.
In one embodiment, as shown in fig. 4, the material of the antimonide isolation layer 33 formed in step S33 is any one or a combination of two or more of InSb, AlSb, InAlSb, and AlGaSb. Preferably, the antimonide isolating layer is made of InAlSb, the molar content of Al is 0.1-0.3, the thickness is 6nm-10nm, and the growth temperature is 400-440 ℃.
In one embodiment, as shown in fig. 4, the material of the barrier layer 34 formed in step S34 is any one or a combination of two or more of InSb, AlSb, InAlSb, and AlGaSb. Preferably, the barrier layer is made of InAlSb, the molar content of Al is 0.1-0.3, the thickness is 80nm-130nm, and the growth temperature is 400 ℃ -440 ℃. The barrier layer has the function of limiting channel carriers on one hand, and provides a process space for the design of a grid electrode in a later device on the other hand.
In one embodiment, as shown in fig. 4, the material of the cap layer 35 formed in step S35 is any one or a combination of two or more of InSb, AlSb, InAlSb and AlGaSb. The cap layer is made of InSb, the thickness of the cap layer is 5nm-10nm, and the growth temperature is 400-440 ℃. The layer is used for protecting the lower layer structure from being oxidized on one hand, and on the other hand, the layer can be doped to form good ohmic contact with metal, so that the contact resistance is reduced, a lower threshold voltage is obtained, and the power consumption of the device is reduced.
In a method for manufacturing an antimonide high electron mobility transistor provided in an embodiment of the present application, as shown in fig. 5, step S31: the method for forming the composite buffer layer on the surface of the electron blocking layer comprises the following steps:
step S311: forming a superlattice buffer layer 311 on the surface of the electron blocking layer 20;
step S312: forming an interposed buffer layer 312 on the surface of the superlattice buffer layer 311;
the interpenetration buffer layer 312 includes a first interpenetration buffer layer 3121 and a second interpenetration buffer layer 3122 disposed between adjacent first interpenetration buffer layers.
In the preparation method of the antimonide high electron mobility transistor in the embodiment, the effect of filtering lattice mismatch dislocation is optimized by strictly controlling the superlattice period number of the superlattice buffer layer; the interpenetration buffer layer blocks larger dislocation which can not be filtered by the superlattice buffer layer, such as contracture crystal and stacking fault, and plays a role in effectively decomposing contracture crystal defects and bending; the combination of the superlattice buffer layer and the interpenetration buffer layer efficiently solves the problem of lattice mismatch between the substrate and the channel layer, and improves the electron mobility of the channel layer of the antimonide high-electron-mobility transistor.
In one embodiment, as shown in fig. 6, the material of the superlattice buffer layer 311 formed in step S311 at least includes, but is not limited to, InSb/InAlSb, InSb/InGaSb, AlSb/InAlSb, AlSb/AlGaSb, and the like. The number of cycles of the superlattice buffer layer is 40-60, each cycle comprises two layers, and a periodical laminated structure is formed in sequence.
By way of example, the material of the superlattice buffer layer 311 is InSb/InAlSb, the InSb thickness in each period is 1nm-3nm, the InAlSb thickness is 4nm-6nm, the molar content of Al is 0.1-0.3, and the growth temperature of the superlattice buffer layer is 400-.
In one embodiment, as shown in fig. 6, the interposed buffer layer 311 formed in step S312 includes a first interposed buffer layer 3121 and a second interposed buffer layer 3122 disposed between adjacent first interposed buffer layers. Wherein a thickness of the first interleaving buffer layer 3121 is greater than a thickness of the second interleaving buffer layer 3122. The interpenetration buffer layer can block the larger dislocation which can not be filtered by the superlattice buffer layer, such as the contracture crystal and the stacking fault, and in addition, the thicker first interpenetration buffer layer provides enough reaction space for the decomposed contracture crystal dislocation. The interpenetration buffer layer is combined with the multicycle superlattice buffer layer, so that the problem of channel layer quality reduction caused by lattice mismatch between the Si substrate and the antimonide can be effectively solved.
As an example, the first and second interleaving buffer layers are overlapped with each other, a plurality of second interleaving buffer layers are interleaved between the plurality of first interleaving buffer layers, and 2 second interleaving buffer layers are interleaved, so as to form the structure shown in fig. 6; or 3 second interleaving buffer layers are interleaved to form the structure shown in fig. 7. Here, this is not limited, and the above two embodiments are only examples. In addition, the first interpenetration buffer layer can also be used as a lower barrier layer of the quantum well channel layer, and plays a role in limiting the electron movement of the channel layer.
Specifically, the first interposing buffer layer 3121 includes InAlxA Sb layer, the second interpenetration buffer layer 3122 including InAlyAnd in the Sb layer, the value range of x is 0.1-0.25, and the value range of y is 0.2-0.4. InAlxThe thickness of the Sb layer is 1um-2um, InAlyThe thickness of the Sb layer is 100nm-300nm, and the growth temperature of the interpenetration buffer layer is 400-440 ℃. The InAlSb layer interfaces with different Al molar contents play a role in decomposing and bending the contracture crystal defects, and the quantitative thickness provides enough contracture crystal dislocation and the like after decompositionA reaction space of (a).
In one embodiment of the present application, the method for manufacturing an antimonide high electron mobility transistor, as shown in fig. 8, further includes the following steps after the composite buffer layer and before the channel layer is formed:
step S313: forming a first doped layer 40 on the surface of the composite buffer layer 31;
step S314: forming a first passivation layer 50 on the surface of the first doped layer 40;
step S315: a doped isolation layer 60 is formed on the surface of the first passivation layer 50.
In the preparation method of the antimonide high electron mobility transistor in the above embodiment, the first doping layer, the first protection layer and the doping isolation layer are sequentially disposed on the composite buffer layer, and at the moment when the first doping layer is deposited on the composite buffer layer, the element penetrating through the buffer layer to provide electrons is replaced, and n-type carriers, i.e., electrons, are provided as an n-type doping source; the first protective layer ensures that atoms of the first doping layer deposited at the early stage are not suddenly heated by the substrate to activate the doping atoms to form a p-type doping source; the doped isolation layer separates the channel layer from the n-type doped source, so that impurity ionization scattering is greatly reduced, and the electron mobility is improved.
Specifically, the first doping layer 40 includes a deposited layer of Si atoms, and before forming the first doping layer 40 on the surface of the composite buffer layer 31, the method further includes:
step S316: and adjusting the temperature of the substrate with the composite buffer layer to a preset temperature, wherein the preset temperature is 280-320 ℃.
By way of example, the growth temperature of the first protective layer is 340 ℃ to 360 ℃, and the growth temperature of the doped isolation layer is 400 ℃ to 440 ℃.
In one embodiment, as shown in fig. 10, the growth temperature of the antimonide high electron mobility transistor structure is usually above 400 ℃, when the n-channel antimonide HEMT structure is manufactured, Si should be used as an n-type doping source, in order to avoid Si atoms from showing amphoteric doping characteristics in the InAlSb barrier layer, the substrate temperature when the Si modulation doping is performed is set to 280-320 ℃, because when the substrate temperature is high, the Si atoms acquire more energy and tend to show P-type doping characteristics instead of Sb position in the InAlSb barrier layer, so as to solve the Si amphoteric doping characteristics, the Si atom deposition layer provides redundant electrons to the channel layer, and the mobility of electrons in the channel layer is improved
In one embodiment, after doping is completed, before the substrate of the antimonide high electron mobility transistor is heated again, the first protective layer 50 is formed on the surface of the first doping layer to avoid that subsequent heating brings that Si atoms are activated by P-type again, and after occupation of the Si atoms is completed, the InAlSb doping isolation layer can grow according to a normal temperature window, so that a doping source and a channel layer are isolated, impurity ionization scattering is greatly reduced, and the electron mobility of the channel layer is improved.
As an example, the material of the first protective layer 50 is any one or a combination of two or more of InSb, AlSb, InAlSb, and algassb.
In one embodiment, the doped spacer layer 60 is fabricated from the same material as the antimonide spacer layer 33 and functions to separate the n-type dopant source from the channel layer. Si atoms are deposited on the surface of the InAlSb of the first interpenetration buffer layer to replace In/Al bits to provide electrons capable of moving freely, and positive charged ionization centers Si & lt + & gt are formed, and the Si & lt + & gt has a binding effect on electron movement due to electrical reasons, namely impurity ionization scattering. On the Si atom sedimentary deposit, grow the InSb channel layer behind the InAlSb isolation layer growth, formed the band offset, the electron at isolation layer one end is because the lower InSb channel layer of conduction band is transferred to automatically to the electric potential effect, and keeps apart with ionization center Si +, the impurity ionization scattering greatly reduced that consequently receives, electron mobility promotes, and then improves antimonide high electron mobility transistor's electron mobility.
In one embodiment of the present application, a method for manufacturing an antimonide high electron mobility transistor, as shown in fig. 9, after forming the antimonide isolation layer 33 and before forming the barrier layer 34, further includes:
step S331: forming a second doped layer 70 on the surface of the antimonide isolation layer 33;
step S332: a second passivation layer 80 is formed on the surface of the second doped layer 70.
In one embodiment, the material, the preparation condition and the function of the second doped layer 70 are completely consistent with those of the first doped layer 40, and the material, the preparation condition and the function of the second passivation layer 80 are completely consistent with those of the first passivation layer 50, which will not be described herein again.
Referring to fig. 10 in conjunction with fig. 1 to 9, in an embodiment of the present application, an antimonide hemt includes a substrate, an electron blocking layer and an antimonide epitaxial structure sequentially stacked. Wherein, antimonide epitaxial structure includes: the composite buffer layer, the first doping layer, the first protection layer, the doping isolation layer, the channel layer, the antimonide isolation layer, the second doping layer, the second protection layer, the barrier layer and the cap layer are sequentially stacked. Because the doping source in the first doping layer is separated from the channel layer by the doping isolation layer, the room temperature mobility of two-dimensional electron gas in the channel layer can reach 6 multiplied by 104cm2Vs, low temperature mobility of 2.8X 105cm2Vs, the two-dimensional electron gas concentration of the room temperature channel layer reaches 2 multiplied by 1012cm-2～5×1012cm-2The reliability of the antimonide high electron mobility transistor is effectively improved.
In the antimonide high electron mobility transistor in the above embodiment, by sequentially forming the electron blocking layer 20, the composite buffer layer 30, the first doping layer 40, the first protection layer 50, the doping isolation layer 60, the channel layer 32, the antimonide isolation layer 33, the second doping layer 70, the second protection layer 80, the barrier layer 34 and the cap layer 35 on the provided substrate 10, the structure not only greatly improves the electron mobility of the channel layer of the antimonide high electron mobility transistor, but also stably improves the stability and reliability of the whole device due to the existence of the doping isolation layer, the antimonide isolation layer, the first protection layer and the second protection layer.
For specific limitations on the preparation method of the antimonide high electron mobility transistor in the above embodiments, reference may be made to the above limitations on the preparation method of the antimonide high electron mobility transistor, and details are not repeated here.
It should be understood that the steps described are not to be performed in the exact order recited, and that the steps may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps described may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least some of the sub-steps or stages of other steps.
It should be noted that the above-mentioned embodiments are only for illustrative purposes and are not meant to limit the present invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for preparing an antimonide high electron mobility transistor is characterized by comprising the following steps:
providing a substrate;
forming an electron blocking layer on the surface of the substrate;
and forming an antimonide epitaxial structure on the surface of the electron blocking layer.
2. The method of claim 1, wherein the electron blocking layer comprises a P-doped InAlSb layer.
3. The method of claim 1, wherein the forming of the antimonide epitaxial structure on the surface of the electron blocking layer comprises:
forming a composite buffer layer on the surface of the electron blocking layer;
forming a channel layer on the surface of the composite buffer layer;
forming an antimonide isolation layer on the surface of the channel layer;
forming a barrier layer on the surface of the antimonide isolation layer;
and forming a cap layer on the surface of the barrier layer.
4. The method of claim 3, wherein the forming of the composite buffer layer on the surface of the electron blocking layer comprises:
forming a superlattice buffer layer on the surface of the electron blocking layer;
forming an inserting buffer layer on the surface of the superlattice buffer layer;
the inserting buffer layer comprises a first inserting buffer layer and a second inserting buffer layer arranged between the first inserting buffer layer and the adjacent first inserting buffer layer.
5. The method of claim 4 wherein said first intervening buffer layer comprises InAlxA Sb layer, the second interpenetration buffer layer comprising InAlyAnd in the Sb layer, the value range of x is 0.1-0.25, and the value range of y is 0.2-0.4.
6. The method for manufacturing an antimonide high electron mobility transistor according to any one of claims 3 to 5, wherein after the composite buffer layer and before the channel layer is formed, the method further comprises:
forming a first doping layer on the surface of the composite buffer layer;
forming a first protective layer on the surface of the first doped layer;
and forming a doped isolation layer on the surface of the first protection layer.
7. The method as claimed in claim 6, wherein the first doping layer comprises a deposited layer of Si atoms, and the method further comprises, before forming the first doping layer on the surface of the composite buffer layer:
and adjusting the temperature of the substrate with the composite buffer layer to a preset temperature, wherein the preset temperature is 280-320 ℃.
8. The method as claimed in any one of claims 3 to 5, further comprising, after the formation of the barrier layer and before the formation of the antimonide isolation layer:
forming a second doping layer on the surface of the antimonide isolation layer;
and forming a second protective layer on the surface of the second doped layer.
9. An antimonide high electron mobility transistor, comprising: the substrate, the electron blocking layer and the antimonide epitaxial structure are sequentially stacked.
10. The antimonide high electron mobility transistor of claim 9, wherein the antimonide epitaxial structure comprises: the composite buffer layer, the first doping layer, the first protection layer, the doping isolation layer, the channel layer, the antimonide isolation layer, the second doping layer, the second protection layer, the barrier layer and the cap layer are sequentially stacked.
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Address after: 518051 Yuanhua complex building, Liyuan Road, wenzhuyuan community, zhaoshang street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Altman (Fujian) semiconductor technology Co.,Ltd. Address before: 518051 Yuanhua complex building, Liyuan Road, wenzhuyuan community, zhaoshang street, Nanshan District, Shenzhen City, Guangdong Province Applicant before: Altman (Shenzhen) semiconductor technology Co.,Ltd. Address after: 518051 Yuanhua complex building, Liyuan Road, wenzhuyuan community, zhaoshang street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Etman Semiconductor Technology Co.,Ltd. Address before: 518051 Yuanhua complex building, Liyuan Road, wenzhuyuan community, zhaoshang street, Nanshan District, Shenzhen City, Guangdong Province Applicant before: Altman (Fujian) semiconductor technology Co.,Ltd. |
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Application publication date: 20210326 |