CN108288644A - InSb high mobility transistors and preparation method thereof - Google Patents
InSb high mobility transistors and preparation method thereof Download PDFInfo
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- CN108288644A CN108288644A CN201810051859.3A CN201810051859A CN108288644A CN 108288644 A CN108288644 A CN 108288644A CN 201810051859 A CN201810051859 A CN 201810051859A CN 108288644 A CN108288644 A CN 108288644A
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- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 title claims abstract description 101
- 238000002360 preparation method Methods 0.000 title claims description 14
- 238000000926 separation method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 150000001875 compounds Chemical class 0.000 claims abstract description 14
- 229910017115 AlSb Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims 1
- 230000037230 mobility Effects 0.000 description 21
- 238000005516 engineering process Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
A kind of InSb high electron mobility transistor comprising：One substrate；One compound buffer layer, growth is on substrate；One InAlSb lower barrierlayers, growth is on compound buffer layer；One InSb sub-channel layers, growth is on InAlSb lower barrierlayers；Separation layer under one InAlSb, growth is in InSb sub-channel layers；One InSb tap drain channel layer, growth is at InAlSb on separation layer；Separation layer on one InAlSb, growth is in InSb tap drain channel layer；One N-shaped doped layer, growth is on InAlSb on separation layer；Barrier layer on one InAlSb, growth is on N-shaped doped layer；One InSb cap layers, growth is on InAlSb on barrier layer.The present invention can cause ionization by collision to avoid the excessive electronics of kinetic energy in tap drain channel layer, reduce it is reverse-biased under the conditions of influence of the ionization by collision to output conductance, improve the stability and reliability of transistor.
Description
Technical field
The invention belongs to technical field of semiconductors, refer in particular to be based on InSb high electron mobility transistor structures and its system
Preparation Method.
Technical background
Free electron and impurity ionization center are spatially segregated from out by quantum well structure in high mobility transistor, can be with
The mobility for greatly improving transistor device has good development prospect in terms of making high-frequency high-speed high power device.Antimony
Object semiconductor lattice constant exists mostlyNear, and larger forbidden band range is covered, in the Quantum Well for making Lattice Matching
Configuration aspects have apparent advantage, and high-quality, large area and uniform antimonide amount can be grown using advanced technologies such as MBE
Sub- well structure.
Indium antimonide (InSb) is that energy gap is minimum in binary antimonide semi-conducting material, and energy gap is
0.17eV, and antimonide semiconductor has the advantageous properties such as high electron mobility, high electron saturation velocities, therefore InSb is in high electricity
Transport factor devices field has good application.InSb materials are combined with quantum well structure, InSb Quantum Well Gao Qian is made
Shifting rate transistor can give full play to the excellent electrical properties of InSb materials, meet with a response speed faster, and cutoff frequency higher is anti-
Answer more sensitive signal conveying equipment.
Invention content
The object of the present invention is to provide a kind of material structures of high electron mobility transistor structure and preparation method thereof, lead to
It crosses and uses compound buffer layer so that the quality of epitaxial material is significantly improved, this structure is in InSb quantum well structures
In InSb tap drains channel layer below be inserted into one layer of InSb sub-channel layer, the larger electronics transfer of kinetic energy is to sub-channel in tap drain channel layer
Layer in, avoid the excessive electronics of kinetic energy and cause ionization by collision in tap drain channel layer, reduce it is reverse-biased under the conditions of ionization by collision to defeated
The influence for going out conductance improves the stability and reliability of transistor.
The present invention provides a kind of InSb high electron mobility transistor comprising：
One substrate；
One compound buffer layer, growth is on substrate；
One InAlSb lower barrierlayers, growth is on compound buffer layer；
One InSb sub-channel layers, growth is on InAlSb lower barrierlayers；
Separation layer under one InAlSb, growth is in InSb sub-channel layers；
One InSb tap drain channel layer, growth is at InAlSb on separation layer；
Separation layer on one InAlSb, growth is in InSb tap drain channel layer；
One N-shaped doped layer, growth is on InAlSb on separation layer；
Barrier layer on one InAlSb, growth is on N-shaped doped layer；
One InSb cap layers, growth is on InAlSb on barrier layer.
The present invention also provides a kind of preparation methods of InSb high electron mobility transistor, include the following steps：
Step 1：Select substrate；
Step 2：On substrate successively under growing mixed buffer layer, InAlSb lower barrierlayers, InSb sub-channel layers, InAlSb
Separation layer, InSb tap drains channel layer, the upper separation layers of InAlSb, N-shaped doped layer, the upper barrier layers of InAlSb and InSb cap layers.
It will the invention has the advantages that being inserted into one layer of InSb sub-channel layer below its InSb tap drains channel layer in the structure
In main Quantum Well in the larger electronics transfer to sub-channel layer of kinetic energy, avoids the excessive electronics of kinetic energy and cause to touch in tap drain channel layer
Hit ionization, reduce it is reverse-biased under the conditions of influence of the ionization by collision to output conductance, improve the output reliability of transistor and steady
It is qualitative.
Description of the drawings
To further illustrate the present invention content, below in conjunction with specific implementation mode, and with reference to attached drawing, the present invention is done with detailed
Thin description, wherein：
Fig. 1 is the structural schematic diagram of high mobility transistor of the present invention；
Fig. 2 is 20 structural schematic diagram of compound buffer layer in Fig. 1；
Fig. 3 is the preparation flow figure of the present invention.
Specific implementation mode
As shown in Figs.1 and 2, the present invention provides a kind of InSb high electron mobility transistor comprising：
One substrate 10, the material of the substrate 10 are the GaAs substrates of semi-insulated (001) crystal orientation；
One compound buffer layer 20, on substrate 10,20 structure of the compound buffer layer includes growth：
One low temperature AI Sb buffer layers 21, for growth in GaAs semi-insulating substrate 10, which can effectively inhibit Twin Defects
Appearance, promote interface shape dislocation in 90 ° formation AlSb island structures as much as possible between substrate and upper layer of material, favorably
In the AlSb high temperature buffer layers of growth high quality；
One AlSb buffer layers 22, for growth on low temperature AI Sb buffer layers 21, which has higher resistivity, can subtract significantly
The leakage current of gadget, while can limit break-through dislocation epitaxial layers in the interface of low temperature AI Sb and high temperature AlSb and extend,
Reduce dislocation density；
One InAlSb buffer layers 23, for growth on AlSb buffer layers 22, which has been effectively relieved quantum well layer and substrate
Between lattice mismatch, further discharge lattice mismatch caused by stress, most of dislocation is limited in this layer；
One InSb/InAlSb super-lattice buffer layers 24, on InAlSb buffer layers 23, number of superlattice cycles are growth
The defects of 20-60, the main function of this layer is using each superlattices interface filtering dislocation, to grow smooth interface and matter
Good InSb quantum well layers are measured to prepare.
The thickness of the low temperature AI Sb buffer layers 21 is 3-20nm；The thickness of the AlSb buffer layers 22 is 1000-
2000nm；The thickness of the InAlSb buffer layers 23 is 1000-2000nm, and wherein the molar content of Al is 0.1-0.3；It is described
The thickness of InSb/InAlSb super-lattice buffer layers 24 is 2-10nm/2-10nm, number of superlattice cycles 20-60, wherein InAlSb
The molar content of middle Al is 0.1-0.3.
One InAlSb lower barrierlayers 30, for growth on compound buffer layer 20, this layer of one side further alleviates lattice mistake
Electronics is limited in by the dislocation before matching and stopping in growth course well on the one hand as the nuclear structure of Quantum Well
In Quantum Well.
One InSb sub-channel layers 40, growth is on InAlSb lower barrierlayers 30, the introducing of InSb sub-channel layers 40, enhancing
Control actions of the grid to electronics in raceway groove, with the alive increase of institute, Fermi's energy of InSb sub-channel layers 40 between source and drain
Grade gradually rises, when the fermi level for the InSb tap drains channel layer 60 chatted after the fermi level of InSb sub-channel layers 40 is higher than, electricity
Son has the possibility of bigger by 60 tunnelling of InSb tap drains channel layer to InSb sub-channel layers 40, to reduce in InSb tap drains channel layer 60
Impact ionization.In addition, the electric current unsaturation caused by ionization by collision is improved, mutual conductance increases, current cut-off frequency
Reach 700GHz.
Separation layer 50 under one InAlSb, for growth in InSb sub-channel layers 40, this layer of one side effectively limits electronics
System is in InSb tap drain channel layer, and on the one hand its separation layer as InSb sub-channels and InSb tap drains road, reduces between raceway groove
Electric property interferes with each other.
One InSb tap drains channel layer 60, for growth at InAlSb on separation layer 50, InSb tap drains channel layer 60 is InSb quantum
The component part of the most important structure of trap high mobility transistor, electronics forms two-dimensional electron gas in channel layer, due to doped source
It is separated by separation layer and raceway groove, the room temperature mobilities of electronics in raceway groove is made to reach 65000cm2/ Vs, low temperature mobility reach
280000cm2/ Vs, and effectively improve the reliability of transistor.
Separation layer 70 on one InAlSb, growth is in InSb tap drains channel layer 60, and separation layer 70 is chatted with after on the InAlSb
N-shaped doped layer 80 separate, effectively avoid scattering process of the ionized impurity to electronics in raceway groove in doped layer, improve ditch
The mobility of electronics in road.
One N-shaped doped layer 80, growth on InAlSb on separation layer 70, modulate by the plane which is Te
Doping, this plane modulation doping technology can effectively improve electron mobility and electron areal density in channel layer so that ditch
The surface density of two-dimensional electron gas reaches 1-3 × 10 in road12/cm2, to improve response frequency and signal strength.
Barrier layer 90 on one InAlSb, growth is on N-shaped doped layer 80, and barrier layer 90 has two aspects to make on the InAlSb
With, on the one hand be used as hole blocking layer, effectively reduce due to gate leak current caused by holes-leakage；On the other hand as guarantor
Sheath protects raceway groove and doped layer not oxidation by air.
One InSb cap layers 100, for growth on InAlSb on barrier layer 90, on the one hand which protects lower layer
On the other hand structure can form good Ohmic contact with metal, reduce contact resistance, obtain lower threshold voltage, from
And reduce the power consumption of device.
Wherein the thickness of the lower barrierlayer 30 is 1000-2000nm, and the molar content of Al is 0.1-0.3；The InSb
The thickness of sub-channel layer 40 is 2-10nm；The thickness of separation layer 50 is 3-10nm under the InAlSb, and the molar content of Al is
0.1-0.3；The thickness of the InSb tap drains channel layer 60 is 10-60nm；The thickness of separation layer 70 is 10- on the InAlSb
The molar content of 60nm, Al are 0.1-0.3；The δ that the N-shaped doped layer 80 is Te is adulterated, and doping concentration is 3 × 1017-2×
1018cm3；The thickness of barrier layer 90 is 100-300nm on the InAlSb, and the molar content of Al is 0.1-0.3；The InSb caps
The thickness of layer 100 is 10-100nm.
Referring to Fig. 3, and combining refering to fig. 1 and Fig. 2, the present invention provide a kind of system of InSb high electron mobility transistor
Preparation Method includes the following steps：
Step 1：Substrate 10 is selected, the material of the substrate 10 is the GaAs of semi-insulated (001) crystal orientation；
Step 2：, growing mixed buffer layer 20, InAlSb lower barrierlayers 30, InSb sub-channel layers successively on substrate 10
40, separation layer 50, InSb tap drains channel layer 60, the upper separation layers 70 of InAlSb, N-shaped doped layer 80, the upper potential barriers of InAlSb under InAlSb
90 and InSb of layer cap layers 100.
Preparation method of the present invention uses molecular beam epitaxial growth technology, and english abbreviation MBE, this is a kind of new crystal life
Long technology and a kind of special vacuum coating technology, extension are a kind of new technologies preparing monocrystal thin films, he is appropriate
Substrate with it is suitable under the conditions of, along the method for substrate material crystalline axis direction successively growing film, the advantages of technology is to use
Underlayer temperature is low, and coating growth rate is slow, and beam intensity is easy to accurately control, and film layer component and doping concentration can be with the variations in source
And adjust rapidly, can have been prepared with this technology thin to tens atomic layers monocrystal thin films and alternating growth different component,
The films of difference doping and the superthin layer quantum microstructure material that is formed.
Wherein the compound buffer layer 20 includes：
One low temperature AI Sb buffer layers 21, thickness 3-20nm, growth temperature are 400-500 DEG C；
One is grown in the AlSb buffer layers 22 on low temperature AI Sb buffer layers 21, thickness 1000-2000nm, growth temperature
It is 500-600 DEG C；
One is grown in the InAlSb buffer layers 23 on AlSb buffer layers 22, thickness 1000-2000nm, and growth temperature is
380-450 DEG C, the molar content of Al is 0.1-0.3；
One is grown in the InSb/InAlSb super-lattice buffer layers 24 on InAlSb buffer layers 23, thickness 2-10nm/2-
10nm, superlattice period 20-60, growth temperature are 380-450 DEG C.
Wherein the thickness of the lower barrierlayer 30 is 1000-2000nm, and growth temperature is 380-450 DEG C, and wherein Al's rubs
Your content is 0.1-0.3；The thickness of the InSb sub-channel layers 40 is 2-10nm, and growth temperature is 380-450 DEG C；It is described
The thickness of separation layer 50 is 3-10nm under InAlSb, and growth temperature is 380-450 DEG C, and wherein the molar content of Al is 0.1-0.3；
The thickness of the InSb tap drains channel layer 60 is 10-60nm, and growth temperature is 380-450 DEG C；Separation layer 70 on the InAlSb
Thickness is 10-60nm, and growth temperature is 380-450 DEG C, and wherein the molar content of Al is 0.1-0.3；The N-shaped doped layer 80 is
The δ of Te is adulterated, and doping concentration is 3 × 1017-2×1018cm3；The thickness of barrier layer 90 is 100-300nm on the InAlSb, raw
Long temperature is 380-450 DEG C, and wherein the molar content of Al is 0.1-0.3；The thickness of the InSb cap layers 100 is 10-100nm,
Growth temperature is 380-450 DEG C.
When wherein growing InSb sub-channel layers 40, which is all the interfaces InSb, the interfaces InSb
It can be obtained by controlling MBE valve switch sequence.
When wherein growing InSb tap drain channel layer 60,60 upper and lower interface of InSb channel layers is all raw under the conditions of rich group-v element
Long, which can switch to obtain, is conducive to obtain high-quality channel layer upper and lower interface under the environment, carry by control valve
High device performance.
The invention has the characteristics that and advantage：
The present invention provides a kind of material structure and preparation method of high electron mobility transistor, uses narrow gap semiconductor
For InSb as channel layer, narrow bandgap semiconductor material has higher electron mobility and saturated electrons compared with other materials
Drift velocity, simultaneously because the band gap very little of InSb can reach electronics saturation drift velocity under very low electric field strength, from
And InSb high electron mobility transistor is made to have the advantages that low-power consumption.High electron mobility transistor also has high transconductance,
Low threshold voltage, high current cut-off frequency, the excellent performances such as low gate leak current.Present invention optimizes the structure of transistor and lifes
Long method, to obtain the InSb high mobility transistors with the above excellent performance.
The structure of the present invention uses semi-insulated GaAs epitaxial substrate, and GaAs substrates are at low cost and are easy to get.It is serving as a contrast
Growing mixed buffer layer structure, on the one hand keeps apart quantum well structure and substrate on bottom, and AlSb, InAlSb buffer layer all have
The characteristics of high value, growth are conducive to reduce device creepage, obtain the Quantum Well that resistance under zero-bias low temperature is higher than 10K Ω
Structure makes device dark current under low temperature, back bias voltage be less than 10nA/cm2；On the other hand, buffer layer can alleviate substrate and device
Lattice mismatch between structure, the defects of discharging stress and dislocation is isolated, to obtain the second best in quality epitaxial layer.
Invention introduces InSb/InAlSb super-lattice buffer layers, each interface can play the role of filtering dislocation,
The crystal quality of epitaxial layer is substantially increased, epitaxial layer halfwidth only has tens second of arcs, keeps the interface of growth channel layer smooth, lacks
It falls into and reduces so that Quantum Well dislocation surface density is less than 5 × 1017/cm2, twin line density is less than 500/cm.
Good well structure can be formed between InAlSb and InSb, electronics is effectively limited in well layer by InAlSb barrier layers
It is interior, two-dimensional electron gas surface density is improved, carrier concentration reaches 1-3 × 10 in room-temperature quantum trap12/cm2。
The structure of the present invention introduces InSb sub-channel layers, effectively inhibits the ionization by collision of tap drain channel layer, reduces
Gate leak current caused by ionization by collision and Kink effects.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (10)
1. a kind of InSb high electron mobility transistor comprising：
One substrate；
One compound buffer layer, growth is on substrate；
One InAlSb lower barrierlayers, growth is on compound buffer layer；
One InSb sub-channel layers, growth is on InAlSb lower barrierlayers；
Separation layer under one InAlSb, growth is in InSb sub-channel layers；
One InSb tap drain channel layer, growth is at InAlSb on separation layer；
Separation layer on one InAlSb, growth is in InSb tap drain channel layer；
One N-shaped doped layer, growth is on InAlSb on separation layer；
Barrier layer on one InAlSb, growth is on N-shaped doped layer；
One InSb cap layers, growth is on InAlSb on barrier layer.
2. the material of InSb high electron mobility transistor according to claim 1, wherein substrate is semi-insulated (001)
The GaAs single crystalline substrates of crystal orientation.
3. InSb high electron mobility transistor according to claim 1, wherein the compound buffer layer structure includes：
One low temperature AI Sb buffer layers；
One AlSb buffer layers, growth is on low temperature AI Sb buffer layers；
One InAlSb buffer layers, growth is on AlSb buffer layers；
One InSb/InAlSb super-lattice buffer layers, growth is on InAlSb buffer layers.
4. InSb high electron mobility transistor according to claim 3, wherein the thickness of the low temperature AI Sb buffer layers
For 3-20nm；The thickness of the AlSb buffer layers is 1000-2000nm；The thickness of the InAlSb buffer layers is 1000-
The molar content of Al is 0.1-0.3 in 2000nm, wherein InAlSb；The thickness of the InSb/InAlSb super-lattice buffer layers is
The molar content of Al is 0.1-0.3 in 2-10nm/2-10nm, number of superlattice cycles 20-60, wherein InAlSb.
5. InSb high electron mobility transistor according to claim 1, wherein the thickness of the lower barrierlayer is 1000-
The molar content of 2000nm, Al are 0.1-0.3；The thickness of the InSb sub-channel layers is 2-10nm；It is isolated under the InAlSb
The thickness of layer is 3-10nm, and the molar content of Al is 0.1-0.3；The thickness of the InSb tap drains channel layer is 10-60nm；It is described
The thickness of the upper separation layers of InAlSb is 10-60nm, and the molar content of Al is 0.1-0.3；The δ that the N-shaped doped layer is Te is adulterated,
Doping concentration is 3 × 1017-2×1018cm-3；The thickness of barrier layer is 100-300nm, the molar content of Al on the InAlSb
For 0.1-0.3；The thickness of the InSb cap layers is 10-100nm.
6. a kind of preparation method of InSb high electron mobility transistor as described in claim 1, includes the following steps：
Step 1：Select substrate；
Step 2：It is isolated under growing mixed buffer layer, InAlSb lower barrierlayers, InSb sub-channel layers, InAlSb successively on substrate
Layer, InSb tap drains channel layer, the upper separation layers of InAlSb, N-shaped doped layer, the upper barrier layers of InAlSb and InSb cap layers.
7. the material of the preparation method of InSb high electron mobility transistor according to claim 6, wherein substrate is half
The GaAs single crystalline substrates of (001) crystal orientation of insulation.
8. the preparation method of InSb high electron mobility transistor according to claim 6, wherein the compound buffer layer
Including：
One low temperature AI Sb buffer layers；
One is grown in the AlSb buffer layers on low temperature AI Sb buffer layers；
One is grown in the InAlSb buffer layers on AlSb buffer layers；
One is grown in the InSb/InAlSb super-lattice buffer layers on InAlSb buffer layers.
9. the preparation method of InSb high electron mobility transistor according to claim 8, wherein the low temperature AI Sb is slow
The thickness for rushing layer is 3-20nm, and growth temperature is 400-500 DEG C；The AlSb buffer layer thicknesses are 1000-2000nm, life
Long temperature is 500-600 DEG C；The thickness of the InAlSb buffer layers is 1000-2000nm, and growth temperature is 380-450 DEG C,
The molar content of Al is 0.1-0.3；The thickness of the InSb/InAlSb super-lattice buffer layers is 2-10nm/2-10nm, superlattices
Periodicity is 20-60, and the molar content of Al is 0.1-0.3 in wherein InAlSb.
10. the preparation method of InSb high electron mobility transistor according to claim 6, wherein the lower barrierlayer
Thickness is 1000-2000nm, and growth temperature is 380-450 DEG C, and wherein the molar content of Al is 0.1-0.3；The InSb cunettes
The thickness of channel layer is 2-10nm, and growth temperature is 380-450 DEG C；The thickness of separation layer is 3-10nm, growth under the InAlSb
Temperature is 380-450 DEG C, and wherein the molar content of Al is 0.1-0.3；The thickness of the InSb tap drains channel layer is 10-60nm, raw
Long temperature is 380-450 DEG C；The thickness of separation layer is 10-60nm on the InAlSb, and growth temperature is 380-450 DEG C, wherein
The molar content of Al is 0.1-0.3；6 doping that the N-shaped doped layer is Te, doping concentration is 3 × 1017-2×1018cm-3；Institute
The thickness for stating barrier layer on InAlSb is 100-300nm, and growth temperature is 380-450 DEG C, and wherein the molar content of Al is 0.1-
0.3；The thickness of the InSb cap layers is 10-100nm, and growth temperature is 380-450 DEG C.
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| CN102054862A (en) * | 2009-10-28 | 2011-05-11 | 中国科学院半导体研究所 | Antimonide transistor with high electron mobility and manufacturing method thereof |
| CN102324436A (en) * | 2011-09-22 | 2012-01-18 | 中国科学院半导体研究所 | Large-mismatch silicon-based substrate antimonide transistor with high electron mobility and manufacturing method thereof |
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| CN102054862A (en) * | 2009-10-28 | 2011-05-11 | 中国科学院半导体研究所 | Antimonide transistor with high electron mobility and manufacturing method thereof |
| CN102324436A (en) * | 2011-09-22 | 2012-01-18 | 中国科学院半导体研究所 | Large-mismatch silicon-based substrate antimonide transistor with high electron mobility and manufacturing method thereof |
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