CN112560383B

CN112560383B - LDO circuit layout method

Info

Publication number: CN112560383B
Application number: CN201910850325.1A
Authority: CN
Inventors: 林宇
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2019-09-10
Filing date: 2019-09-10
Publication date: 2022-05-24
Anticipated expiration: 2039-09-10
Also published as: CN112560383A

Abstract

An RC filter circuit is arranged at the bottom, isolation ground wires are arranged on the periphery of the RC filter circuit, an error amplifier is arranged above the isolation ground wires, and the input end of the error amplifier is adjacent to the RC filter circuit, so that signals after RC filtering are prevented from being interfered, and the power supply rejection ratio of the LDO circuit is improved.

Description

LDO circuit layout method

Technical Field

The invention relates to an LDO (low dropout regulator) technology, in particular to a layout method of an LDO circuit.

Background

An LDO circuit is a low dropout linear regulator circuit in an integrated circuit, and is required to have a high power Supply Rejection ratio psr (power Supply Rejection ratio) and low noise. The working principle of the LDO circuit is that the band gap reference BGR generates a reference voltage, the reference voltage is amplified into a desired voltage through the regulator circuit, the noise is filtered through the RC filter circuit to generate a purer voltage, the driving capability of the LDO circuit is improved through the rear-stage error amplifier EA, the buffer BUF and the POWER tube POWER, and the external change is resisted. The regulator circuit includes an operational amplifier OP, a second PMOS transistor M2, a second variable resistor R2, and a third resistor R3, where a negative input terminal of the operational amplifier OP is connected to a reference voltage terminal of a band gap reference BGR, a positive input terminal of the operational amplifier OP is connected to a ground terminal through a third resistor, an output terminal of the operational amplifier OP is connected to a gate of the second PMOS transistor M2, a source of the second PMOS transistor M2 is connected to a power voltage terminal VDD, a drain of the second PMOS transistor M2 is connected to a positive input terminal of the operational amplifier OP through a second variable resistor, a drain of the second PMOS transistor M2 is connected to a negative input terminal of the error amplifier EA through one path of the first resistor, and the other path is connected to the ground terminal through a first capacitor, a positive input terminal of the error amplifier EA is connected to an output voltage terminal VOUT, an output terminal of the error amplifier EA is connected to an input terminal of a buffer, an output terminal of the buffer is connected to a gate of the first PMOS transistor M1, the drain electrode of the first PMOS transistor M1 is connected to the output voltage terminal VOUT, the source electrode of the first PMOS transistor M1 is connected to the power voltage terminal VDD, and the output voltage terminal VOUT is connected to the ground terminal through a first current source. The difficulty of the Layout of the LDO circuit is that the relatively pure voltage after RC filtering has no driving capability, and is easily interfered by the internal wiring of the circuit, and the weak parasitic capacitance can deteriorate the power supply rejection ratio, so that the desired voltage stabilizing effect cannot be achieved. The inventor thinks that if the centered condition of the RC filter circuit is changed, the RC filter circuit is arranged at the bottom, the isolation ground wires are arranged around the RC filter circuit, the error amplifier is arranged above the isolation ground wires, and the input end of the error amplifier is adjacent to the RC filter circuit, so that the interference of the RC-filtered signals can be avoided, and the power supply rejection ratio of the LDO circuit is improved. In view of the above, the present inventors have completed the present invention.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides a layout method of an LDO circuit, wherein an RC filter circuit is arranged at the bottom, isolation ground wires are arranged around the RC filter circuit, an error amplifier is arranged above the isolation ground wires, and the input end of the error amplifier is adjacent to the RC filter circuit, so that the interference of signals after RC filtering is avoided, and the power supply rejection ratio of the LDO circuit is favorably improved.

The technical scheme of the invention is as follows:

the layout method of the LDO circuit is characterized by comprising an RC filter circuit, wherein the RC filter circuit is arranged at the bottom, isolation ground wires are arranged around the RC filter circuit, an error amplifier is arranged above the isolation ground wires, and the input end of the error amplifier is vertically adjacent to the RC filter circuit.

The RC filter circuit comprises a first resistor and a first capacitor, one end of the first capacitor is connected with the grounding end, the other end of the first capacitor penetrates through the negative input end of the isolation ground wire connected with the error amplifier, the other end of the first capacitor penetrates through one end of the first resistor, and the other end of the first resistor penetrates through the drain electrode of a second PMOS (P-channel metal oxide semiconductor) tube in the isolation ground wire connected with the voltage regulating circuit.

The periphery of a connecting line between the first capacitor and the error amplifier is provided with an isolation device.

A band gap reference voltage circuit is arranged above the isolation ground wire, and the error amplifier is adjacent to the band gap reference voltage circuit in the left and right directions.

A voltage regulating circuit is arranged above the band gap reference voltage circuit, and a buffer circuit is arranged above the error amplifier.

And a power circuit is arranged above the buffer circuit and covers the voltage regulating circuit and the buffer circuit.

The buffer circuit comprises a buffer and a first current source, the output end of the error amplifier is connected with the input end of the buffer, the output end of the buffer is connected with a grid electrode of a first PMOS (P-channel metal oxide semiconductor) tube in the power circuit, a source electrode of the first PMOS tube is connected with a power supply voltage end, a drain electrode of the first PMOS tube is connected with an output voltage end, and the output voltage end is connected with a grounding end through the first current source.

The voltage regulating circuit comprises an operational amplifier, a second PMOS (P-channel metal oxide semiconductor) tube, a second variable resistor and a third resistor, wherein the negative input end of the operational amplifier is connected with the output end of the band-gap reference voltage circuit, the positive input end of the operational amplifier is connected with the grounding end through the third resistor, the output end of the operational amplifier is connected with the grid electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the power supply voltage end, and the drain electrode of the second PMOS tube is connected with the positive input end of the operational amplifier through the second variable resistor.

The invention has the following technical effects: according to the layout method of the LDO circuit, the capacitor resistor is placed at the bottommost part (namely the bottommost part of the layout), the periphery is isolated by the ground wire, the input pair of the error amplifier EA is placed beside the capacitor resistor, and therefore the connection line between the capacitor resistor and the error amplifier EA is not interfered by other signals, and the power supply rejection ratio PSR of the LDO circuit is effectively improved. Isolation is also needed beside the connecting line. So that the PSR can be guaranteed.

Drawings

FIG. 1 is a schematic diagram of a layout method of an LDO circuit according to the present invention.

The reference numbers are listed below: a Power-Power circuit; BUF + other-buffer circuit; VREG-voltage regulating circuit (regulating circuit regulator comprising OP, M2, R2, R3); EA-error amplifying circuit or error amplifier; BGR-band gap reference voltage circuit or band gap reference voltage; CAP + RES-RC filter circuit (the RC filter circuit is positioned at the bottom, the solid line of the peripheral square box represents the peripheral isolation ground line, the RC is adjacent to the EA, and the side of the connection line between the RC and the EA can also be isolated to ensure higher Power Supply Rejection Ratio PSR); VDD-supply voltage or supply voltage terminal; GND-ground; VOUT-output voltage or output voltage terminal; m1-first PMOS tube or power tube; m2-second PMOS tube; a Buf-buffer; i1 — a first current source; an OP-operational amplifier; r1 — first resistance (filter resistance); r2 — a second variable resistance; r3 — third resistance; c1 — first capacitance (filter capacitance); m2 d-second PMOS transistor drain node.

Detailed Description

The invention is described below with reference to the accompanying drawing (fig. 1).

FIG. 1 is a schematic diagram of a layout method of an LDO circuit according to the present invention. As shown in fig. 1, an LDO circuit layout includes an RC filter circuit CAP + RES, the RC filter circuit CAP + RES is disposed at the bottom, isolation ground lines are disposed around the RC filter circuit CAP + RES, an error amplifier EA is disposed above the isolation ground lines, and an input end of the error amplifier EA is vertically adjacent to the RC filter circuit CAP + RES. The RC filter circuit CAP + RES comprises a first resistor R1 and a first capacitor C1, one end of the first capacitor C1 is connected with a ground end GND, one path of the other end of the first capacitor C1 passes through the negative input end (-) of the isolation ground wire connected with the error amplifier EA, the other path of the other capacitor C1 is connected with one end of the first resistor R1, and the other end of the first resistor R1 passes through the isolation ground wire and is connected with the drain electrode of a second PMOS tube M2 in the voltage regulating circuit VREG. The first capacitor C1 is isolated from the wiring of the error amplifier EA. A band gap reference voltage circuit BGR is arranged above the isolation ground wire, and the error amplifier EA is adjacent to the band gap reference voltage circuit BGR in the left-right direction. And a voltage regulating circuit VREG is arranged above the band-gap reference voltage circuit BGR, and a buffer circuit BUF + other is arranged above the error amplifier EA. And a Power circuit Power is arranged above the buffer circuit BUF + other and covers the voltage regulating circuit VREG and the buffer circuit BUF + other. Buffer circuit BUF + other includes buffer BUF and first current source I1, the input of buffer BUF is connected to the output of error amplifier EA, the grid of the first PMOS pipe M1 in the output connection power circuit of buffer BUF, the mains voltage end VDD is connected to the source of first PMOS pipe M1, output voltage end VOUT is connected to the drain electrode of first PMOS pipe M1, output voltage end VOUT passes through first current source I1 connects ground terminal GND. The voltage regulating circuit VREG includes an operational amplifier OP, a second PMOS transistor M2, a second variable resistor R2, and a third resistor R3, a negative input terminal (-) of the operational amplifier OP is connected to an output terminal of a band gap reference voltage circuit BGR, a positive input terminal (+) of the operational amplifier OP is connected to a ground terminal GND through the third resistor R3, an output terminal of the operational amplifier OP is connected to a gate of the second PMOS transistor M2, a source of the second PMOS transistor M2 is connected to a power supply voltage terminal VDD, and a drain of the second PMOS transistor M2 is connected to the positive input terminal (+) of the operational amplifier OP through the second variable resistor R2.

The invention can avoid the interference of the RC filtered signal, and is an LDO circuit with high power supply rejection ratio (PSR) and low noise, which can be conveniently and effectively manufactured.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalent, modified and/or simplified implementations as described above, e.g., implementations using other oscillator regulation circuits, etc., without departing from the spirit of the present invention, are intended to fall within the scope of the present invention.

Claims

1. The layout method of the LDO circuit is characterized by comprising an RC filter circuit, wherein the RC filter circuit is arranged at the bottom, isolation ground wires are arranged around the RC filter circuit, an error amplifier is arranged above the isolation ground wires, and the input end of the error amplifier is vertically adjacent to the RC filter circuit;

the RC filter circuit comprises a first resistor and a first capacitor, one end of the first capacitor is connected with a grounding end, one path of the other end of the first capacitor penetrates through the isolation ground wire and is connected with the negative input end of the error amplifier, the other path of the first capacitor is connected with one end of the first resistor, and the other end of the first resistor penetrates through the isolation ground wire and is connected with a drain electrode of a second PMOS (P-channel metal oxide semiconductor) tube in the voltage regulating circuit;

a band gap reference voltage circuit is arranged above the isolation ground wire, and the error amplifier is adjacent to the band gap reference voltage circuit left and right;

a voltage regulating circuit is arranged above the band gap reference voltage circuit, and a buffer circuit is arranged above the error amplifier;

a power circuit is arranged above the buffer circuit and covers the voltage regulating circuit and the buffer circuit;

the buffer circuit comprises a buffer and a first current source, the output end of the error amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the grid electrode of a first PMOS (P-channel metal oxide semiconductor) tube in the power circuit, the source electrode of the first PMOS tube is connected with a power supply voltage end, the drain electrode of the first PMOS tube is connected with an output voltage end, and the output voltage end is connected with a grounding end through the first current source;

2. The layout method of the LDO circuit of claim 1, wherein a periphery of a connection line between the first capacitor and the error amplifier has an isolation setting.