CN112542389B - Secondary etching forming method for high-precision lead - Google Patents
Secondary etching forming method for high-precision lead Download PDFInfo
- Publication number
- CN112542389B CN112542389B CN202011342154.0A CN202011342154A CN112542389B CN 112542389 B CN112542389 B CN 112542389B CN 202011342154 A CN202011342154 A CN 202011342154A CN 112542389 B CN112542389 B CN 112542389B
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- etching
- lead
- photoresist
- product
- chip
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- 238000005530 etching Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 239000007788 liquid Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000354 decomposition reaction Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 8
- 230000002950 deficient Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000003814 drug Substances 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/438—Post-treatment of the connector
- H01L2224/4383—Reworking
- H01L2224/43831—Reworking with a chemical process, e.g. with etching of the connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
The invention relates to a secondary etching forming method of a high-precision lead, and belongs to the technical field of high-precision circuit boards. In the design stage, the leads on the high-precision circuit board are connected to the internal circuits of the chip position or the leads on the two sides of the chip are connected with each other, photoresist is coated again after the circuit is formed by primary etching, the secondary exposure is carried out on the lead connection position, the photoresist at the secondary exposure position is developed, secondary etching is carried out, the final lead shape is formed, and the ideal etching effect of the front end shape of the high-precision lead is obtained. The beneficial effects of the invention are as follows: the etching positions are equidistant in one etching process, so that the etching effect is good; and when the front end of the secondary etched lead is formed, the secondary etched lead is only corroded by etching liquid in one direction, a larger bonding area of the bonding pad is obtained during bonding, the bonding force between the welded lead and the chip bonding pad is increased, the omission phenomenon of defective products is reduced, and the product yield and reliability during bonding operation are improved. The yield and the reliability of the product are improved.
Description
Technical Field
The invention relates to a secondary etching forming method of a high-precision lead, and belongs to the technical field of high-precision circuit boards.
Background
With the continuous improvement of the requirements of electronic products on chip processing capacity in the market, packaged chips rapidly develop to high speed, integration and miniaturization. The precision degree of the bonding pads on the chip is continuously improved, and meanwhile, the precision of the leads on the COF product corresponding to the precision degree is required to be synchronously improved. Along with the reduction of the width and the distance of the lead, the influence of the liquid medicine on the erosion effect of the lead front end is more obvious when the lead is etched, so that the situation that the reliability of a packaged product is reduced and even the size of the lead front end cannot meet the packaging requirement is caused. In order to solve the problems, the invention provides a secondary etching forming method of a high-precision lead, which improves the etching precision of the lead tip.
The existing high-precision lead processing steps have the following defects: 1. the leading end of the lead is corroded by etching liquid in three directions when being etched, the leading end is thinned, the shape of the leading end is in a pinpoint shape, the bonding area is reduced when bonding is carried out, and the bonding quality of a chip is easily affected due to insufficient virtual welding or welding bonding force. 2. Because the lead tips are tapered, lead breakage due to bonding pressure on the leads may occur during the chip bonding process, resulting in poor product functionality, as shown in fig. 10. 3. Because the leading end of the lead is thinned and has different shapes, the leading end area of the lead cannot be inspected in the automatic optical inspection process in the production process, and defective products can be missed. 4. Since the wire width of the lead tip is reduced, the bonding force between the metal lead and PI is reduced, and the lead may be peeled off due to curling or external force during COF product production and bonding process, as shown in fig. 11. 5. With the progress of the precision of the lead, the thinner the line tip is, the more significantly the etching effect of the etching solution is.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a secondary etching forming method of a high-precision lead, wherein the lead on a high-precision circuit board is connected to an internal circuit at a chip position or the leads at two sides of the chip are connected with each other in a design stage, and the final lead shape is formed through secondary etching, so that an ideal etching effect of the shape of the front end of the high-precision lead is obtained.
The invention is realized by the following technical scheme: a secondary etching forming method of a high-precision lead is characterized in that a metal lead is designed at a position corresponding to a chip bonding pad and is connected with an external circuit, a superposition area of the chip bonding pad and the metal lead is a bonding area, and the front end of the metal lead exceeds the chip bonding pad area by a certain length, and the secondary etching forming method comprises the following steps:
step A: in the design stage, the metal leads are directly connected to internal circuits at the chip position on the product or the metal leads at the two sides of the chip are mutually connected, so that the circuit does not have a front end breakpoint of the metal leads;
and (B) step (B): coating a layer of photoresist on copper of a product substrate, exposing the product substrate coated with the photoresist, and developing the photoresist subjected to decomposition reaction at an exposed part by using a developing solution to expose a copper layer below;
step C: etching the copper layer exposed on the surface of the developed product for one time by using etching solution to form a circuit;
step D: stripping photoresist on the surface of the etched circuit by using a stripping liquid, and removing the photoresist to form a comb-shaped circuit structure by the metal lead and the connected chip internal circuit;
step E: coating photoresist on the product after primary etching again, and carrying out secondary exposure on the connection part of the metal lead and the internal circuit of the chip;
step F: performing secondary development on the photoresist subjected to decomposition reaction at the secondary exposure position by using a developing solution to expose the copper layer below;
step G: carrying out secondary etching on the copper exposed on the surface of the product after secondary development by using etching liquid to form a metal lead front end, wherein the line distance part of the metal lead is protected by photoresist and only eroded by the etching liquid in one direction of the front end;
step H: and stripping the photoresist on the surface of the circuit after the secondary etching by using a stripping liquid.
The product substrate comprises an FPC product, a COF product or a hard board product.
The beneficial effects of the invention are as follows: 1. the etching positions of the leads in the invention are equidistant during one-time etching, and the etching effect is good; the etching solution only has one etching effect when the lead is etched for the second time, so that the lead can obtain a more standard line width value and a more standard lead shape, a larger bonding area of the bonding pad is obtained during bonding, the bonding force between the lead and the chip bonding pad after welding is increased, and the reliability is improved.
2. The shape change is very little for the design value after the lead wire front end forms, can carry out automatic optical inspection to lead wire front end region in the production process, reduces the omission of defective products and examines the phenomenon, promotes product quality.
3. After the width of the leading end of the lead wire is increased, the lead wire is not easy to be pressed and broken when being bonded, and the product yield and reliability are improved when the bonding operation is performed.
4. The width of the leading end of the lead wire is increased and stable, and the lead wire can provide stable and smaller impedance value for each functional pin on the chip after bonding with the chip, optimize the working environment of the chip and correspond to the bonding package of the chip with special requirements on the working environment.
5. The wider lead front end improves the binding force with the bearing PI, reduces the occurrence of poor lead stripping phenomenon, and improves the product yield and reliability.
6. The method provided by the invention has smaller influence due to the etching solution erosion effect, and can be more suitable for the high-precision development of future circuit board products.
Drawings
The invention is further described below with reference to the drawings and examples.
FIG. 1 is a schematic diagram of step A of the present invention;
FIG. 2 is a schematic diagram of step B of the present invention;
FIG. 3 is a schematic diagram of step C of the present invention;
FIG. 4 is a schematic diagram of step D of the present invention;
FIG. 5 is a schematic diagram of step E of the present invention;
FIG. 6 is a schematic diagram of step F of the present invention;
FIG. 7 is a schematic diagram of step G of the present invention;
FIG. 8 is a schematic diagram of step H of the present invention;
FIG. 9 is a schematic diagram of a comparison of etched leads and IC pads of the present invention;
FIG. 10 is a schematic diagram of a prior art lead fracture that may occur;
fig. 11 is a schematic diagram of a prior art wire lift-off that may occur when a product is curled or an external force is applied.
Detailed Description
A secondary etching forming method of a high-precision lead is characterized in that a metal lead 2 is designed at a position corresponding to a chip bonding pad 1 and is connected with an external circuit, a superposition area of the chip bonding pad 1 and the metal lead 2 is a bonding area, and the front end of the metal lead 2 exceeds the area of the chip bonding pad 1 by a certain length, and the secondary etching forming method comprises the following steps:
step A: in the design stage, as shown in fig. 1, the metal leads 2 are directly connected to the internal circuits of the chip position on the product or the metal leads 2 on two sides of the chip are connected with each other, so that the circuit does not have the front end break points of the metal leads 2, and the following steps are schematically described by taking the boxes in fig. 1 as enlarged areas;
and (B) step (B): a layer of photoresist 4 is coated on copper 3 of a product substrate, the product substrate coated with the photoresist 4 is subjected to exposure treatment, the photoresist 4 subjected to decomposition reaction at the exposure position is developed by using a developing solution, and a product stacking schematic after the development of the copper layer below is exposed is shown as a figure 2, wherein an arrow part shows a developing solution reaction direction schematic. The method comprises the steps of carrying out a first treatment on the surface of the
Step C: the copper layer exposed on the surface of the developed product is etched once by using etching liquid to form a circuit, the stacking schematic of the etched product is shown in figure 3, wherein the arrow part shows the reaction direction of the etching liquid, and the etching part of the liquid medicine is equidistant due to the absence of the break point of the front end of the metal lead 2, so that the uniformity of the etched circuit width is good.
Step D: stripping photoresist on the surface of the etched circuit by using a stripping liquid, removing the photoresist, and forming a comb-shaped circuit structure by the metal lead 2 and the connected chip internal circuit, wherein the stacking structure schematic of the stripped product is shown in fig. 4, and the arrow part is a film stripping liquid reaction direction schematic;
step E: coating photoresist on the product after the primary etching again, and performing secondary exposure on the connection part of the metal lead 2 and the internal circuit of the chip, wherein the position of an exposure area is shown in figure 5;
step F: carrying out secondary development on the photoresist subjected to decomposition reaction at the secondary exposure position by using a developing solution to expose the copper layer 3 below, wherein a stacking schematic after the secondary development is shown in fig. 6, and an arrow part is shown as a developing solution reaction direction schematic;
step G: carrying out secondary etching on the copper exposed on the surface of the product after secondary development by using etching solution to form the front end of the metal lead 2, wherein the structural schematic diagram after secondary etching is shown in fig. 7, the arrow part shows the reaction direction of the etching solution, and at the moment, the line distance part of the metal lead 2 is protected by photoresist and only eroded by the etching solution in one direction of the front end;
step H: and stripping the photoresist on the surface of the circuit after the secondary etching by using a stripping solution, wherein the product stacking structure after the stripping is shown in fig. 8, the arrow part shows the reaction direction of the stripping solution, and after the photoresist is removed, the lead front end and the circuit inside the chip can be found to be corroded by the etching solution in one direction, so that the shape change is smaller compared with the design shape.
As shown in fig. 9, comparing the etched leads to the IC pads may find that the area of the bonding region at this time is substantially equal to the design value.
The product substrate comprises an FPC product, a COF product or a hard board product.
Claims (2)
1. A secondary etching forming method of a high-precision lead is characterized in that a metal lead (2) is designed at a position corresponding to a chip bonding pad (1) and is connected with an external circuit, a superposition area of the chip bonding pad (1) and the metal lead (2) is a bonding area, and the front end of the metal lead (2) exceeds the area of the chip bonding pad (1) by a certain length, and the secondary etching forming method comprises the following steps:
step A: in the design stage, the metal leads (2) are directly connected to internal circuits at the chip position on the product or the metal leads (2) at the two sides of the chip are connected with each other, so that the circuit does not have the front end break points of the metal leads (2);
and (B) step (B): coating a layer of photoresist (4) on copper (3) of a product substrate, exposing the product substrate coated with the photoresist (4), and developing the photoresist (4) subjected to decomposition reaction at an exposed part by using a developing solution to expose a copper layer below;
step C: etching the copper layer exposed on the surface of the developed product for one time by using etching solution to form a circuit;
step D: stripping photoresist on the surface of the etched circuit by using a stripping liquid, and removing the photoresist to form a comb-shaped circuit structure by the metal lead (2) and the connected chip internal circuit;
step E: coating photoresist on the product after primary etching again, and performing secondary exposure on the connection part of the metal lead (2) and the internal circuit of the chip;
step F: performing secondary development on the photoresist subjected to decomposition reaction at the secondary exposure position by using a developing solution to expose the copper layer (3) below;
step G: carrying out secondary etching on the copper exposed on the surface of the product after secondary development by using etching liquid to form the front end of the metal lead (2), wherein the line distance part of the metal lead (2) is protected by photoresist and only eroded by the etching liquid in one direction of the front end;
step H: and stripping the photoresist on the surface of the circuit after the secondary etching by using a stripping liquid.
2. The method for secondarily etching and forming the high-precision lead according to claim 1, wherein the method comprises the following steps: the product substrate comprises an FPC product, a COF product or a hard board product.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011342154.0A CN112542389B (en) | 2020-11-25 | 2020-11-25 | Secondary etching forming method for high-precision lead |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011342154.0A CN112542389B (en) | 2020-11-25 | 2020-11-25 | Secondary etching forming method for high-precision lead |
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| Publication Number | Publication Date |
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| CN112542389A CN112542389A (en) | 2021-03-23 |
| CN112542389B true CN112542389B (en) | 2024-03-29 |
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| CN202011342154.0A Active CN112542389B (en) | 2020-11-25 | 2020-11-25 | Secondary etching forming method for high-precision lead |
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| CN113097094B (en) * | 2021-04-29 | 2022-11-25 | 云谷（固安）科技有限公司 | Substrate to be cut, display panel and preparation method of display panel |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07169895A (en) * | 1993-09-20 | 1995-07-04 | Sumitomo Electric Ind Ltd | Lead frame and manufacture of the same |
| KR20030013980A (en) * | 2001-08-10 | 2003-02-15 | 삼성테크윈 주식회사 | Chip scale package and lead frame for the same and the fabrication method thereof |
| CN1735963A (en) * | 2003-01-15 | 2006-02-15 | 先进互联技术有限公司 | Semiconductor packaging with partially patterned lead frames and its making methods |
| CN103050451A (en) * | 2012-12-17 | 2013-04-17 | 华天科技（西安）有限公司 | Double-row pin quad flat no lead packaging piece and insulating treatment method thereof |
| CN103094239A (en) * | 2012-12-14 | 2013-05-08 | 华天科技（西安）有限公司 | Auxiliary paster pin added lead frame package part and manufacture process |
| US8673687B1 (en) * | 2009-05-06 | 2014-03-18 | Marvell International Ltd. | Etched hybrid die package |
| CN105789068A (en) * | 2014-12-25 | 2016-07-20 | 无锡华润安盛科技有限公司 | Preparation method of QFN package device |
| CN108242433A (en) * | 2017-12-05 | 2018-07-03 | 上海交通大学 | A kind of method that hyperfine package lead is realized based on photoetching and plating |
-
2020
- 2020-11-25 CN CN202011342154.0A patent/CN112542389B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07169895A (en) * | 1993-09-20 | 1995-07-04 | Sumitomo Electric Ind Ltd | Lead frame and manufacture of the same |
| KR20030013980A (en) * | 2001-08-10 | 2003-02-15 | 삼성테크윈 주식회사 | Chip scale package and lead frame for the same and the fabrication method thereof |
| CN1735963A (en) * | 2003-01-15 | 2006-02-15 | 先进互联技术有限公司 | Semiconductor packaging with partially patterned lead frames and its making methods |
| US8673687B1 (en) * | 2009-05-06 | 2014-03-18 | Marvell International Ltd. | Etched hybrid die package |
| CN103094239A (en) * | 2012-12-14 | 2013-05-08 | 华天科技（西安）有限公司 | Auxiliary paster pin added lead frame package part and manufacture process |
| CN103050451A (en) * | 2012-12-17 | 2013-04-17 | 华天科技（西安）有限公司 | Double-row pin quad flat no lead packaging piece and insulating treatment method thereof |
| CN105789068A (en) * | 2014-12-25 | 2016-07-20 | 无锡华润安盛科技有限公司 | Preparation method of QFN package device |
| CN108242433A (en) * | 2017-12-05 | 2018-07-03 | 上海交通大学 | A kind of method that hyperfine package lead is realized based on photoetching and plating |
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| CN112542389A (en) | 2021-03-23 |
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Effective date of registration: 20240129 Address after: 221300 north of Liaohe Road and west of Huashan Road, Pizhou Economic Development Zone, Xuzhou City, Jiangsu Province Applicant after: Jiangsu SHANGDA Semiconductor Co.,Ltd. Country or region after: China Address before: 518100 floors 1-4, 2-3, building a, Huangpu Runhe Industrial Park, South Ring Road, Huangpu Community, Shajing street, Bao'an District, Shenzhen City, Guangdong Province Applicant before: LEADER-TECH ELECTRONICS (SHENZHEN) Inc. Country or region before: China |
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