CN112542147A - Liquid crystal panel driving voltage polarity inversion method and circuit, panel and display device - Google Patents
Liquid crystal panel driving voltage polarity inversion method and circuit, panel and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The application provides a liquid crystal panel driving voltage polarity inversion method, a circuit, a panel and a display device, wherein grid lines of the liquid crystal panel are divided into X continuous grid line groups, and X is an integer not less than 2; for one gate line group, sequentially opening a gate line row to which a first data voltage signal is applied corresponding to pixel units, loading the first data voltage signal to the pixel units on the opened gate line row, then sequentially opening the gate line row to which a second data voltage signal is applied corresponding to the pixel units, and loading the second data voltage signal to the pixel units on the opened gate line row, wherein the polarities of the first data voltage signal and the second data voltage signal are opposite; and performing the same driving voltage polarity inversion operation as the previous gate line group on each of the rest gate line groups until the driving voltage polarity inversion operation on X gate line groups is completed in one frame.
Description
Technical Field
The application relates to the technical field of display, in particular to a method and a circuit for reversing the polarity of a driving voltage of a liquid crystal panel, the panel and a display device.
Background
The existing liquid crystal display panel driving architecture mostly adopts a 1line architecture, a 2line architecture or a 1+2line architecture, wherein the 1line architecture can reduce the flicker problem of the display panel, and the 2line architecture or the 1+2line architecture can improve the vertical stripe and oblique line problem of the display panel caused by a viewing angle compensation algorithm, and has unique advantages in different application occasions, however, no matter the 1line architecture, the 2line architecture or the 1+2line architecture, in the driving process of the display panel, the pixel units on the scanning lines can be sequentially opened, the polarity of each line or each two lines of the data voltage signals output on the driver IC can be inverted, the polarity inversion of the data voltage signals on the display panel frequently causes the temperature rise of the driver IC, and the power consumption is increased.
Disclosure of Invention
The application aims to solve the problems of driver IC temperature rise and power consumption increase of the existing liquid crystal display panel caused by frequent polarity inversion of data voltage signals, and provides a method for inverting the driving voltage polarity of the liquid crystal display panel.
According to the liquid crystal panel driving voltage polarity inversion method, grid lines of a liquid crystal panel are divided into X continuous grid line groups, wherein X is an integer not less than 2;
for one gate line group, sequentially opening a gate line row to which a first data voltage signal is applied corresponding to pixel units, loading the first data voltage signal to the pixel units on the opened gate line row, then sequentially opening the gate line row to which a second data voltage signal is applied corresponding to the pixel units, and loading the second data voltage signal to the pixel units on the opened gate line row, wherein the polarities of the first data voltage signal and the second data voltage signal are opposite;
and performing the same driving voltage polarity inversion operation as the previous gate line group on each of the rest gate line groups until the driving voltage polarity inversion operation on X gate line groups is completed in one frame.
In one possible implementation manner of the present application, the number of the gate line rows of each gate line group is the same, the polarity inversion operation of the driving voltage of each gate line group is completed within a time of 1/X frame, for each gate line group, first, the gate line row to which the first data voltage signal is applied to the corresponding pixel unit is sequentially opened within a time of 1/2X frames, after the first data voltage signal is applied to the pixel unit on the opened gate line row, then, within a time of 1/2X frames, the gate line row to which the second data voltage signal is applied to the corresponding pixel unit is sequentially opened, and the second data voltage signal is applied to the pixel unit on the opened gate line row.
In one possible implementation manner of the present application, the driving voltage polarity inversion operation is performed on the X consecutive gate line groups sequentially from top to bottom.
In one possible implementation manner of the present application, the voltage polarity of the first data voltage signal is positive and the voltage polarity of the second data voltage signal is negative, or the voltage polarity of the first data voltage signal is negative and the voltage polarity of the second data voltage signal is positive.
In one possible implementation manner of the present application, after loading a first data voltage signal to the pixel units on the opened gate line for one gate line group, only a second data voltage signal of the gate line row to which a second data voltage signal is applied is stored in the line buffer data of the Tcon IC, and after loading the second data voltage signal to the pixel units on the opened gate line, no data is stored in the line buffer data of the Tcon IC.
In one possible implementation manner of the present application, the gate line row to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the gate line row of the odd-numbered row in the gate line group; the gate line rows to which the second data voltage signals are applied to the corresponding pixel units correspond to the gate line rows of the even-numbered rows in the gate line group.
In one possible implementation manner of the present application, the gate line rows to which the first data voltage signals are applied to the corresponding pixel units correspond to the gate line rows ordered as 1,2,5,6,9,10 … 1+4k,2+4k in the gate line groups; the gate line row of the corresponding pixel unit to which the second data voltage signal is applied corresponds to the gate line row of the gate line group which is ordered to be 3,4,7,8,11,12 … 3+4k,4+4 k; and k is a natural number.
In one possible implementation manner of the present application, the gate line rows to which the first data voltage signals are applied to the corresponding pixel units correspond to the gate line rows ordered as 1,4,5,8,9 … 4+4k,5+4k in the gate line groups; the gate line row of the corresponding pixel unit to which the second data voltage signal is applied corresponds to the gate line row of the gate line groups which are ordered to be 2,3,6,7 … 2+4k,3+4 k; and k is a natural number.
Another object of the present invention is to provide a liquid crystal panel driving voltage polarity inversion circuit, which employs the above liquid crystal panel driving voltage polarity inversion method for driving an array substrate in a liquid crystal panel.
Further, the array substrate includes: the liquid crystal display panel comprises a substrate, and a grid line and a data line which are formed on the substrate, wherein the grid line and the data line define a pixel unit;
the circuit comprises: a gate line driving circuit connected to the gate lines and a data driving circuit connected to the data lines;
the grid line driving circuit is used for sequentially opening a grid line row which is applied with a first data voltage signal to a corresponding pixel unit or a grid line row which is applied with a second data voltage signal to a corresponding pixel unit in a certain grid line group within 1/2X frame time;
the data driving circuit is used for loading a first data voltage signal to the pixel units on the opened grid line or loading a second data voltage signal to the pixel units on the opened grid line.
Another object of the present invention is to provide a liquid crystal panel using the liquid crystal panel driving voltage polarity inversion circuit.
It is still another object of the present application to provide a display device including the liquid crystal panel.
The liquid crystal panel driving voltage polarity inversion method provided by the application divides the grid lines of the liquid crystal panel into X continuous grid line groups, first applying a first data voltage signal to corresponding pixel units in a gate line group and then applying a second data voltage signal to the rest pixel units, that is, the pixel units in the same grid line group only need to perform one driving voltage polarity inversion operation, compared with the operation that the polarity of each line or each two lines of data voltage signals is inverted in the driving process of the existing display panel, the frequency of voltage polarity inversion is reduced, the rising temperature of a driver IC is reduced, the purpose of saving electricity is achieved, meanwhile, the grid lines of the liquid crystal panel are divided into X grid line groups, and the polarity inversion operation is respectively carried out on each grid line group, and the line buffer data of the Tcon IC can only store data voltage signals which are not loaded in the grid line group, so that the aim of saving Tcon IC resources is fulfilled.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method for inverting polarity of a driving voltage of a liquid crystal panel according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating an embodiment of the present invention that divides a gate line of a liquid crystal panel into 3 consecutive gate line groups from top to bottom;
fig. 3(a) to 3(f) are schematic polarity diagrams of the 1 st 1/6 th to 6 th 1/6 th frames of the display panel when the liquid crystal panel driving voltage polarity inversion method provided by the embodiment of the present application is adopted.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The embodiment of the application provides a method for reversing the polarity of a driving voltage of a liquid crystal panel, and a specific flow chart is shown in fig. 1, wherein grid lines of the liquid crystal panel are averagely divided into X continuous grid line groups from top to bottom, wherein X is an integer not less than 2; within a time of 1/X frame, for a gate line group, firstly, sequentially opening a gate line row to which a first data voltage signal is applied corresponding to pixel units within a time of 1/2X frames, loading the first data voltage signal to the pixel units on the opened gate line row, and then sequentially opening a gate line row to which a second data voltage signal is applied corresponding to the pixel units within a time of 1/2X frames, loading the second data voltage signal to the pixel units on the opened gate line row, wherein the polarities of the first data voltage signal and the second data voltage signal are opposite, the voltage polarity of the first data voltage signal is positive and the voltage polarity of the second data voltage signal is negative, or the voltage polarity of the first data voltage signal is negative and the voltage polarity of the second data voltage signal is positive; and in the time of each 1/X frame, carrying out the same driving voltage polarity inversion operation as the previous gate line group on each residual gate line group until finishing the driving voltage polarity inversion operation on the X gate line groups in one frame.
According to the liquid crystal panel driving voltage polarity inversion method, the pixel units in the same grid line group only need to carry out one-time driving voltage polarity inversion operation, and compared with the operation that the polarity of each row or each two rows of data voltage signals is inverted in the driving process of the existing display panel, the frequency of voltage polarity inversion is reduced, the rising temperature of a driver IC is reduced, and the purpose of saving electricity is achieved.
Specifically, when the polarity inversion operation of the driving voltage is performed on the X consecutive gate line groups, the polarity inversion operation of the driving voltage may be performed on each gate line group sequentially from top to bottom, and the specific flow is as shown in fig. 1. The driving voltage polarity inversion operation may also be sequentially performed on each gate line group according to a preset sequence. Alternatively, in other embodiments of the present application, the gate lines of the liquid crystal panel may be divided into X continuous gate line groups from top to bottom, and the driving voltage polarity inversion operation may be performed on each gate line group separately.
When a first data voltage signal is loaded to the pixel units on the opened gate line group for a certain gate line group, only the second data voltage signal of the gate line row, to which the second data voltage signal is applied, of the corresponding pixel units in the gate line group is stored in the line buffer data of the Tcon IC, and after the second data voltage signal is loaded to the pixel units on the opened gate line row, no data is stored in the line buffer data of the Tcon IC. The storage rule of the line buffer data of the Tcon IC solves the problem that in the driving process of a display panel, if the polarity inversion of a data voltage signal on the display panel is reduced, the data voltage signal which is not loaded in the whole display panel needs to be stored in the line buffer data of the Tcon IC, so that more Tcon IC resources are consumed, and the effect of relatively saving the Tcon IC resources is achieved. It should be noted that, in some specific implementations, the line buffer data of the Tcon IC may also store data voltage signals that are not loaded in the entire display panel as needed.
In the embodiment of the present application, specifically, the data driving frequency of the liquid crystal panel is set to be frame _ rate, the resolution is M × N, if the grid lines of the liquid crystal panel are equally divided into X continuous grid line groups from top to bottom, and X is an integer not less than 2, N/2X linebuffer data of the Tcon IC are provided, and the gate driving frequency is set to be 2X frame _ rate.
When the driving architecture of the liquid crystal panel adopts a 1line architecture, in a time of a 1 st 1/2X frame, gate line rows of rows 1, 3, 5, and 7 … … (namely, odd rows) in a first gate line group are sequentially turned on, a first data voltage signal is applied to pixel units on the turned-on gate line row, at this time, a second data voltage signal of gate line rows of rows 2, 4, 6, and 8 … … (namely, even rows) in the first gate line group is stored in linebuffer, in a time of a 2 nd 1/2X frame, gate line rows of rows 2, 4, 6, and 8 … … (namely, even rows) in the first gate line group are sequentially turned on, a second data voltage signal is applied to pixel units on the turned-on gate line rows, at this time, no data is stored in linebuffer.
In the time of the 3 rd 1/2X frame, the gate line rows in the 1 st, 3 rd, 5 th, and 7 th 7 … … th rows (i.e., odd rows) in the second gate line group are sequentially turned on, the first data voltage signal is applied to the pixel units on the turned-on gate line row, at this time, the second data voltage signal of the gate line rows in the 2 nd, 4 th, 6 th, and 8 … … th rows (i.e., even rows) in the second gate line group is stored in linebuffer, and in the time of the 4 th 1/2X frame, the gate line rows in the 2 nd, 4 th, 6 th, and 8 … … th rows (i.e., even rows) in the second gate line group are sequentially turned on, the second data voltage signal is applied to the pixel units on the turned-on gate line rows, at this time, no data is stored in linebuffer.
… … repeating the above steps until gate lines in rows 1, 3, 5, and 7 … … (i.e., odd rows) in the X-th gate line group are sequentially turned on within a time of (2X-1) 1/2X frame, loading a first data voltage signal to the pixel units on the turned-on gate line row, at this time, storing a second data voltage signal of the gate line rows in rows 2, 4, 6, and 8 … … (i.e., even rows) in the X-th gate line group in linebuffer, sequentially turning on the gate line rows in rows 2, 4, 6, and 8 … … (i.e., even rows) in the X-th gate line group within a time of 2X 1/2X frame, loading a second data voltage signal to the pixel units on the turned-on row, at this time, no data is stored in the linebuffer; thereby completing the polarity inversion operation of the driving voltages for the X gate line groups within one frame.
When the driving architecture of the liquid crystal panel adopts a 2-line architecture, gate lines of rows 1,2,5,6,9,10 … … (i.e., rows 1+4k,2+4k, k is a natural number) in the first gate line group are sequentially turned on within a time of 1/2X frame, a first data voltage signal is applied to the pixel units on the turned-on gate line row, at this time, a second data voltage signal of rows 3,4,7,8,11,12 … … (i.e., rows 3+4k,4+4k, k is a natural number) in the first gate line group is stored in linebuffer, gate line rows of rows 3,4,7,8,11,12 … … (i.e., rows 3+4k,4+4k, k is a natural number) in the first gate line group are sequentially turned on within a time of 2 1/2X frame, and a second data voltage signal is applied to the pixel units on the gate line rows of the turned-on gate lines, at this time, no data is stored in linebuffer.
Sequentially opening the gate line rows of rows 1,2,5,6,9 and 10 … … (i.e. rows 1+4k and 2+4k, where k is a natural number) in the second gate line group within the time of the 3 rd 1/2X frame, loading the first data voltage signal to the pixel units on the opened gate line row, and storing the second data voltage signal of the gate line rows 3,4,7,8,11 and 12 … … (i.e. rows 3+4k and 4+4k, where k is a natural number) in the second gate line group in linebuffer at this time, in the time of the 4 th 1/2X frame, the gate line rows in rows 3,4,7,8,11, and 12 … … (i.e., rows 3+4k,4+4k, where k is a natural number) in the second gate line group are sequentially turned on, and the second data voltage signal is applied to the pixel cells on the turned-on gate line row, where linebuffer has no data stored therein.
… … are analogized in turn until gate lines of rows 1,2,5,6,9,10 … … (i.e. rows 1+4k,2+4k, k is a natural number) in the X-th gate line group are sequentially turned on within the time of (2X-1) 1/2X frame, a first data voltage signal is applied to the pixel cells on the gate line row that is turned on, at this time, the linebuffer stores a second data voltage signal of the gate line row of rows 3,4,7,8,11,12 … … (i.e. rows 3+4k,4+4k, k is a natural number) in the X-th gate line group, the gate line rows of rows 3,4,7,8,11,12 … … (i.e. rows 3+4k,4+4k, k is a natural number) in the X-th gate line group are sequentially turned on within the time of 2X 1/2X frame, and a second data voltage signal is applied to the pixel cells on the gate line row that is turned on, at this time, no data is stored in linebuffer; thereby completing the polarity inversion operation of the driving voltages for the X gate line groups within one frame.
When the driving architecture of the liquid crystal panel adopts a 1+2line architecture, gate lines of rows 1,4,5,8 and 9 … … (i.e., rows 4+4k and 5+4k, where k is a natural number) in a first gate line group are sequentially opened within a time of 1/2X frame, a first data voltage signal is loaded to pixel units on the opened gate line row, and a second data voltage signal of a gate line row of rows 2,3,6 and 7 … … (i.e., rows 2+4k and 3+4k, where k is a natural number) in the first gate line group is stored in linebuffer at this time, in the time of the 2 nd 1/2X frame, the gate line rows in the 2 nd, 3 rd, 6 th, and 7 … … th rows (i.e., the 2+4k,3+4k th rows, where k is a natural number) in the first gate line group are sequentially opened, and the second data voltage signal is applied to the pixel units on the opened gate line rows, where linebuffer has no data stored therein.
In the time of the 3 rd 1/2X frame, the gate line rows in the 1 st, 4 th, 5 th, 8 th, 9 … … th rows (i.e., the 4 th +4k,5 th +4k rows, where k is a natural number) in the second gate line group are sequentially turned on, the first data voltage signal is applied to the pixel units on the opened gate line rows, at this time, the linebuffer stores the second data voltage signal of the 2 nd, 3 th, 6 th, 7 … … th rows (i.e., the 2 nd +4k,3 th +4k rows, where k is a natural number) in the second gate line group, and at this time, in the time of the 4 th 1/2X frame, the gate line rows in the 2 nd, 3 th, 6 th, 7 … … th rows (i.e., the 2 nd +4k,3 th +4k rows, where k is a natural number) in the second gate line group are sequentially turned on, and the pixel units on the opened gate line rows are loaded with the second data voltage signal, at this time, no data is.
… …, repeating the above steps until the gate lines in rows 1,4,5,8,9 … … (i.e. rows 4+4k,5+4k, where k is a natural number) in the X-th gate line group are sequentially turned on within the time of the (2X-1) 1/2X frame, loading the first data voltage signal to the pixel units on the turned-on gate line row, where the linebuffer stores the second data voltage signals of the 2 nd, 3 rd, 6 th, and 7 … … (i.e. rows 2+4k,3+4k, where k is a natural number) gate line rows, sequentially opening the gate line rows in rows 2,3,6 and 7 … … (namely rows 2+4k and 3+4k, wherein k is a natural number) in the X-th gate line group within the time of the 2X 1/2X frame, and loading a second data voltage signal to the pixel units on the opened gate line rows, wherein linebuffer does not store data at the moment; thereby completing the polarity inversion operation of the driving voltages for the X gate line groups within one frame.
Taking the lcd panel with data driving frequency of 60HZ and resolution of 3840 × 2160 as an example, the gate lines of the lcd panel are equally divided into 3 continuous gate line groups from top to bottom, as shown in fig. 2. Then 2160/6-360 lines of linebuffer data for Tcon IC and gate driving frequency 6-60-360 HZ. The panel driving architecture adopts a 1-line architecture, and by adopting the liquid crystal panel driving voltage polarity inversion method of the embodiment of the present application, polarity diagrams of 1/6 th frames to 1/6 th frames are shown in fig. 3(a) to 3 (f).
As shown in fig. 3(a), during the time of the 1 st 1/6 frame, sequentially opening the gate line rows of the 1 st, 3 rd, 5 th, 7 … … 717 th and 719 th rows in the first gate line group (i.e. the gate line rows of the rows 1 to 720), and applying a first data voltage signal to the pixel units on the opened gate line row, wherein the voltage polarity of the first data voltage signal is positive; at this time, the linebuffer stores the second data voltage signals of the gate line rows in the 2 nd, 4 th, 6 th, 8 … … 718, 720 th rows in the first gate line group, and 360 lines in total, and the voltage polarity of the second data voltage signal is negative, as shown in fig. 3(b), in the time of the 2 nd 1/6 frame, the gate line rows in the 2 nd, 4 th, 6 th, 8 … … 718, 720 th rows in the first gate line group are sequentially turned on, and the second data voltage signal is loaded to the pixel units on the turned-on gate line row, and at this time, no data is stored in the linebuffer.
As shown in fig. 3(c), during the 3 rd 1/6 th frame, sequentially turning on the gate lines in the 1 st, 3 rd, 5 th, 7 … … 717, 719 th rows in the second gate line group (i.e. the gate line rows in the 721 to 1440 th rows), loading the first data voltage signal to the pixel units on the turned-on gate line row, at this time, the linebuffer stores the second data voltage signals of the gate line rows in the 2 nd, 4 th, 6 th, 8 … … 718, 720 th rows in the second gate line group, and totally 360 lines, as shown in fig. 3(d), during the 4 th 1/6 th frame, sequentially turning on the gate line rows in the 2 nd, 4 th, 6 th, 8 … … 718, 720 th rows in the second gate line group, loading the second data voltage signal to the pixel units on the opened gate line rows, at this time, no data is stored in the linebuffer.
As shown in fig. 3(e), during the time of the 5 th 1/6 frame, sequentially turning on the gate lines of the 1 st, 3 rd, 5 th, 7 … … 717, 719 st rows in the third gate line group (i.e., the gate line rows of the 1441 to 2160 rows), loading the first data voltage signal to the pixel units on the turned-on gate line row, at this time, storing the second data voltage signals of the gate line rows of the 2 nd, 4 th, 6 th, 8 … … 718, 720 nd rows in the third gate line group in linebuffer, as shown in fig. 3(f), during the time of the 6 th 1/6 frame, sequentially turning on the gate line rows of the 2 nd, 4 th, 6 th, 8 … … 718, 720 nd rows in the 3 rd gate line group, loading the second data voltage signal to the pixel units on the gate line rows in linebuffer, at this time, no data is stored in linebuffer; thereby completing the polarity inversion operation of the driving voltages for the 3 gate line groups within one frame.
The embodiment of the application further provides a liquid crystal panel driving voltage polarity inversion circuit, which adopts the liquid crystal panel driving voltage polarity inversion method described above, and is used for driving an array substrate in a liquid crystal panel.
Specifically, the array substrate includes: the liquid crystal display panel comprises a substrate, and a grid line and a data line which are formed on the substrate and define a pixel unit.
The circuit includes: a gate line driving circuit connected to the gate lines and a data driving circuit connected to the data lines.
The gate line driving circuit is used for sequentially opening a gate line row to which a first data voltage signal is applied to a corresponding pixel unit or a gate line row to which a second data voltage signal is applied to a corresponding pixel unit in a certain gate line group within 1/2 times of a frame.
The data driving circuit is used for loading a first data voltage signal to the pixel units on the opened grid line row or loading a second data voltage signal to the pixel units on the opened grid line row.
The embodiment of the present application further provides a liquid crystal panel using the liquid crystal panel driving voltage polarity inversion circuit, and for specific limitations of the liquid crystal panel, reference may be made to the above limitations of the liquid crystal panel driving voltage polarity inversion method and the liquid crystal panel driving voltage polarity inversion circuit, which are not described herein again.
Finally, the embodiments of the present application provide a display device including the above-mentioned liquid crystal panel, and for the specific limitations of the display device, reference may be made to the limitations of the display panel above, and details are not repeated herein.
The liquid crystal panel driving voltage polarity inversion method and circuit, the panel and the display device provided by the present application are described in detail above, and the principle and the implementation manner of the present invention are explained in this document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (12)
1. A liquid crystal panel driving voltage polarity inversion method is characterized in that grid lines of a liquid crystal panel are divided into X continuous grid line groups, wherein X is an integer not less than 2;
for one gate line group, sequentially opening a gate line row to which a first data voltage signal is applied corresponding to pixel units, loading the first data voltage signal to the pixel units on the opened gate line row, then sequentially opening the gate line row to which a second data voltage signal is applied corresponding to the pixel units, and loading the second data voltage signal to the pixel units on the opened gate line row, wherein the polarities of the first data voltage signal and the second data voltage signal are opposite;
and performing the same driving voltage polarity inversion operation as the previous gate line group on each of the rest gate line groups until the driving voltage polarity inversion operation on X gate line groups is completed in one frame.
2. The liquid crystal panel driving voltage polarity inversion method of claim 1, wherein the number of the gate line rows of each of the gate line groups is the same, the driving voltage polarity inversion operation of each of the gate line groups is completed within a time of 1/X frame, and for each of the gate line groups, the gate line row to which the first data voltage signal is applied to the corresponding pixel unit is first sequentially turned on within a time of 1/2X frames, the gate line row to which the second data voltage signal is applied to the corresponding pixel unit is sequentially turned on within a time of 1/2X frames, and the second data voltage signal is applied to the pixel unit on the turned-on gate line row.
3. The method of claim 1, wherein the X consecutive gate line groups are sequentially driven from top to bottom by polarity inversion of driving voltage.
4. The method of claim 1, wherein the voltage polarity of the first data voltage signal is positive and the voltage polarity of the second data voltage signal is negative, or the voltage polarity of the first data voltage signal is negative and the voltage polarity of the second data voltage signal is positive.
5. The method of claim 1, wherein for a group of the gate lines, after applying a first data voltage signal to the pixel cells on the opened row of the gate lines, only a second data voltage signal of a corresponding row of the gate lines is stored in a row buffer data of a Tcon IC, and after applying a second data voltage signal to the pixel cells on the opened row of the gate lines, no data is stored in the row buffer data of the Tcon IC.
6. The liquid crystal panel driving voltage polarity inversion method of claim 2, wherein the row of the gate lines to which the first data voltage signal is applied to the corresponding pixel unit corresponds to a row of the gate lines of odd-numbered rows of the group of the gate lines; the gate line rows to which the second data voltage signals are applied to the corresponding pixel units correspond to the gate line rows of the even-numbered rows in the gate line group.
7. The liquid crystal panel driving voltage polarity inversion method of claim 2, wherein the row of the gate lines to which the first data voltage signal is applied to the corresponding pixel cell corresponds to the row of the gate lines ordered as 1,2,5,6,9,10 … 1+4k,2+4k in the group of the gate lines; the gate line row of the corresponding pixel unit to which the second data voltage signal is applied corresponds to the gate line row of the gate line group which is ordered to be 3,4,7,8,11,12 … 3+4k,4+4 k; and k is a natural number.
8. The liquid crystal panel driving voltage polarity inversion method of claim 2, wherein the row of the gate lines to which the first data voltage signal is applied to the corresponding pixel cell corresponds to the row of the gate lines ordered as 1,4,5,8,9 … 4+4k,5+4k in the group of the gate lines; the gate line row of the corresponding pixel unit to which the second data voltage signal is applied corresponds to the gate line row of the gate line groups which are ordered to be 2,3,6,7 … 2+4k,3+4 k; and k is a natural number.
9. A liquid crystal panel driving voltage polarity reversing circuit is characterized in that the circuit adopts the liquid crystal panel driving voltage polarity reversing method of any one of claims 1 to 8 and is used for driving an array substrate in a liquid crystal panel.
10. The liquid crystal panel driving voltage polarity reversing circuit according to claim 9, wherein the array substrate includes: the liquid crystal display panel comprises a substrate, and a grid line and a data line which are formed on the substrate, wherein the grid line and the data line define a pixel unit;
the circuit comprises: a gate line driving circuit connected to the gate lines and a data driving circuit connected to the data lines;
the grid line driving circuit is used for sequentially opening a grid line row which is applied with a first data voltage signal to a corresponding pixel unit or a grid line row which is applied with a second data voltage signal to a corresponding pixel unit in a certain grid line group within 1/2X frame time;
the data driving circuit is used for loading a first data voltage signal to the pixel units on the opened grid line or loading a second data voltage signal to the pixel units on the opened grid line.
11. A liquid crystal panel characterized by comprising the liquid crystal panel driving voltage polarity reversing circuit according to claim 9 or 10.
12. A display device characterized by comprising the liquid crystal panel according to claim 11.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011399510.2A CN112542147A (en) | 2020-12-02 | 2020-12-02 | Liquid crystal panel driving voltage polarity inversion method and circuit, panel and display device |
| PCT/CN2020/137968 WO2022116302A1 (en) | 2020-12-02 | 2020-12-21 | Driving voltage polarity inversion method and circuit for liquid crystal panel, and liquid crystal panel |
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| CN202011399510.2A CN112542147A (en) | 2020-12-02 | 2020-12-02 | Liquid crystal panel driving voltage polarity inversion method and circuit, panel and display device |
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| CN101681606A (en) * | 2007-06-12 | 2010-03-24 | 夏普株式会社 | Liquid crystal display device, method for driving liquid crystal display device, and television receiver |
| US20100123702A1 (en) * | 2008-11-17 | 2010-05-20 | Samsung Electronics Co., Ltd. | Liquid crystal display and method of driving the same |
| CN103262148A (en) * | 2011-04-08 | 2013-08-21 | 夏普株式会社 | Scanning signal line drive circuit and display device equipped with same |
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| CN107731192A (en) * | 2017-11-16 | 2018-02-23 | 深圳市华星光电技术有限公司 | The drive system of liquid crystal display and the driving method of liquid crystal display |
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2020
- 2020-12-02 CN CN202011399510.2A patent/CN112542147A/en active Pending
- 2020-12-21 WO PCT/CN2020/137968 patent/WO2022116302A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101681606A (en) * | 2007-06-12 | 2010-03-24 | 夏普株式会社 | Liquid crystal display device, method for driving liquid crystal display device, and television receiver |
| US20100123702A1 (en) * | 2008-11-17 | 2010-05-20 | Samsung Electronics Co., Ltd. | Liquid crystal display and method of driving the same |
| CN103262148A (en) * | 2011-04-08 | 2013-08-21 | 夏普株式会社 | Scanning signal line drive circuit and display device equipped with same |
| CN103456277A (en) * | 2013-08-30 | 2013-12-18 | 合肥京东方光电科技有限公司 | Polarity-reversal driving method and polarity-reversal driving circuit |
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| WO2022116302A1 (en) | 2022-06-09 |
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