CN112532190A - S-band hybrid integrated circuit - Google Patents

S-band hybrid integrated circuit Download PDF

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Publication number
CN112532190A
CN112532190A CN202011559574.4A CN202011559574A CN112532190A CN 112532190 A CN112532190 A CN 112532190A CN 202011559574 A CN202011559574 A CN 202011559574A CN 112532190 A CN112532190 A CN 112532190A
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China
Prior art keywords
stage
capacitor
gan chip
circuit
bias
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CN202011559574.4A
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Chinese (zh)
Inventor
杨杰
陈强
王嘉伟
南帅
张卫平
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Jiangsu Broadwave Electric Technology Co ltd
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Jiangsu Broadwave Electric Technology Co ltd
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Priority to CN202011559574.4A priority Critical patent/CN112532190A/en
Publication of CN112532190A publication Critical patent/CN112532190A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention relates to the technical field of circuits, in particular to an S-band hybrid integrated circuit which comprises a packaging tube shell, wherein a two-stage amplification circuit is arranged in the packaging tube shell, a grid power supply end, a signal input end pin, a signal output end pin and a drain power supply end are arranged on the packaging tube shell, the two-stage amplification circuit comprises a front-stage amplification circuit and a rear-stage amplification circuit, the front-stage amplification circuit comprises a front-stage 4-watt GaN chip and an input two-stage matching circuit, and the rear-stage amplification circuit comprises a rear-stage 24-watt GaN chip and an input and output two-stage matching circuit. The device is matched with 50 ohms, the use is convenient, the two-stage GaN chip matching is completed by utilizing a limited space, and the debugging is convenient by using a chip capacitor and a gold wire; the internal integrated bias circuit enables the device to be more conveniently mounted, the filter capacitor and the blocking capacitor enable the device to be more stable in performance, and finally the S-band small dense type high-gain and high-efficiency hybrid integrated amplifier circuit is achieved.

Description

S-band hybrid integrated circuit
Technical Field
The invention relates to an integrated circuit, in particular to an S-band hybrid integrated circuit, and belongs to the technical field of circuits.
Background
The GaN microwave power device has the characteristics of high power density, high efficiency, higher working frequency and the like, has greater advantages in military and civil markets compared with products of other processes, and is widely applied.
Disclosure of Invention
The invention aims to provide an S-band hybrid integrated circuit, and the device is matched with 50 ohms and is convenient to use; the device has small overall dimension, two-stage GaN chip matching is completed by using a limited space, and the chip capacitor and the gold wire are used for facilitating debugging; the bias circuit of the two-stage feed circuit is integrated inside, so that the device is more convenient to mount, and the integration is beneficial to improving the efficiency; the filter capacitor and the blocking capacitor enable the performance of the device to be more stable, and finally the S-band tiny dense type high-gain and high-efficiency hybrid integrated amplifier circuit is achieved.
In order to achieve the purpose, the invention adopts the main technical scheme that:
an S-band hybrid integrated circuit comprises a packaging tube shell, wherein a two-stage amplifying circuit is arranged inside the packaging tube shell, a grid power supply end, a signal input end pin, a signal output end pin and a drain power supply end which are connected with the two-stage amplifying circuit are arranged on the packaging tube shell, the grid power supply end is electrically connected with the two-stage amplifying circuit through a microstrip line, and the signal output end pin is electrically connected with the two-stage amplifying circuit through the microstrip line;
the two-stage amplification circuit comprises a preceding stage amplification circuit and a subsequent stage amplification circuit, the preceding stage amplification circuit comprises a preceding stage 4-watt GaN chip and an input two-stage matching circuit, the input two-stage matching circuit comprises a series inductor and a first matching capacitor, and the series inductor is connected with the first matching capacitor in series;
the post-stage amplifying circuit comprises a post-stage 24-watt GaN chip and an input and output two-stage matching circuit, the input and output two-stage matching circuit comprises a series inductor, a winding patch inductor, a second matching capacitor and a third matching capacitor, and the series inductor, the winding patch inductor, the second matching capacitor and the third matching capacitor are connected in series;
by the technical scheme, the device is matched with 50 ohms, and is convenient to use; the device has small overall dimension, two-stage GaN chip matching is completed by using a limited space, and the chip capacitor and the gold wire are used for facilitating debugging; the bias circuit of the two-stage feed circuit is integrated inside, so that the device is more convenient to mount, and the integration is beneficial to improving the efficiency; the filter capacitor and the blocking capacitor enable the performance of the device to be more stable, and finally the S-band tiny dense type high-gain and high-efficiency hybrid integrated amplifier circuit is achieved.
Preferably, a bias circuit is arranged inside the package tube shell, the bias circuit comprises a bias circuit input end, a third bias capacitor, a fourth bias capacitor, a fifth bias capacitor and a bias circuit output end, and the bias circuit input end is connected with the signal input end pin.
Preferably, the bias circuit further comprises a first quarter wave line, a second quarter wave line, a third quarter wave line and a fourth quarter wave line.
Preferably, the bias circuit is connected with a first bias capacitor and a second bias capacitor in parallel, and the input end and the output end of the front-stage 4-watt GaN chip and the rear-stage 24-watt GaN chip are both connected with a blocking capacitor.
Preferably, the front-stage 4-watt GaN chip and the rear-stage 24-watt GaN chip are both L-shaped matching circuits.
Preferably, the preceding stage 4 watt GaN chip is provided with a preceding stage 4 watt GaN chip grid electrode and a preceding stage 4 watt GaN chip drain electrode, the later stage 24 watt GaN chip is provided with a later stage 24 watt GaN chip grid electrode and a later stage 24 watt GaN chip drain electrode, and the preceding stage 4 watt GaN chip grid electrode, the preceding stage 4 watt GaN chip drain electrode, the later stage 24 watt GaN chip grid electrode and the later stage 24 watt GaN chip drain electrode are all connected with a filter capacitor.
Preferably, an attenuator is connected between the front-stage 4-watt GaN chip and the rear-stage 24-watt GaN chip.
Preferably, the signal is input from a signal input end pin, is transmitted into an input end of a bias circuit, sequentially passes through an L-shaped matching circuit consisting of a first matching capacitor and a winding chip inductor, enters a front-stage 4-watt GaN chip grid electrode in a front-stage 4-watt GaN chip, is amplified, then passes through a front-stage 4-watt GaN chip drain electrode, passes through a third bias capacitor, is output from a fourth bias capacitor, is connected to an attenuator, then passes through a attenuator, sequentially passes through a rear-stage 24-watt GaN chip consisting of a second matching capacitor and a winding chip inductor, is amplified, then passes through the rear-stage 24-watt GaN chip drain electrode sequentially passes through the winding chip inductor and the rear-stage 24-watt GaN chip consisting of the third matching capacitor, and finally passes through a fifth bias capacitor, and is finally output from an output end of the bias circuit.
Preferably, the grid power supply is connected with the grid power supply end and then connected into the filter capacitor to be divided into two paths, one path of power supply sequentially passes through the second bias capacitor and the third quarter-wavelength line to reach the grid electrode of the front-stage 4-watt GaN chip, the other path of power supply sequentially passes through the first bias capacitor and the fourth quarter-wavelength line to reach the grid electrode of the rear-stage 24-watt GaN chip, the drain power supply is connected with the drain power supply end and then connected into the filter capacitor to be divided into two paths, one path of power supply sequentially passes through the second bias capacitor and the first quarter-wavelength line to reach the drain electrode of the front-stage 4-watt GaN chip, and the other path of power supply sequentially passes through the second bias capacitor and the second quarter-wavelength.
The invention has at least the following beneficial effects:
the device is matched with 50 ohms, so that the device is convenient to use; the device has small overall dimension, two-stage GaN chip matching is completed by using a limited space, and the chip capacitor and the gold wire are used for facilitating debugging; the bias circuit of the two-stage feed circuit is integrated inside, so that the device is more convenient to mount, and the integration is beneficial to improving the efficiency; the filter capacitor and the blocking capacitor enable the performance of the device to be more stable, and finally the S-band tiny dense type high-gain and high-efficiency hybrid integrated amplifier circuit is achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of the circuit structure of the present invention;
FIG. 2 is a schematic diagram of a front-end 4W GaN chip of the invention;
FIG. 3 is a schematic view of a rear-level 24W GaN chip of the invention;
FIG. 4 is a schematic diagram of an attenuator circuit of the present invention;
FIG. 5 is a schematic diagram of a bias circuit according to the present invention.
In the figure, 1-package, 2-gate power supply, 3-signal input terminal, 4-signal output terminal, 5-drain power supply, 61-first bias capacitor, 62-blocking capacitor, 7-second bias capacitor, 8-filter capacitor, 9-first matching capacitor, 10-front stage 4W GaN chip, 101-front stage 4W GaN chip grid, 102-front stage 4W GaN chip drain, 11-attenuator, 12-second matching capacitor, 13-back stage 24W GaN chip, 131-back stage 24W GaN chip grid, 132-back stage 24W GaN chip drain, 14-winding chip inductor, 15-third matching capacitor, 16-bias circuit, 161-bias circuit input terminal, 162-bias circuit output terminal, 163-first quarter wave line, 166-second quarter wave line, 168-third bias capacitance, 169-fourth bias capacitance, 1611-fifth bias capacitance, 1612-third quarter wave line, 1613-fourth quarter wave line.
Detailed Description
Embodiments of the present application will be described in detail with reference to the drawings and examples, so that how to implement technical means to solve technical problems and achieve technical effects of the present application can be fully understood and implemented.
As shown in fig. 1 to 5, the S-band hybrid integrated circuit provided in this embodiment includes a package tube 1, a two-stage amplifying circuit is disposed inside the package tube 1, a gate power supply terminal 2, a signal input terminal pin 3, a signal output terminal pin 4, and a drain power supply terminal 5 are disposed on the package tube 1, the gate power supply terminal 2 is electrically connected to the two-stage amplifying circuit through a microstrip line, and the signal output terminal pin 4 is electrically connected to the two-stage amplifying circuit through a microstrip line;
the two-stage amplifying circuit comprises a preceding stage amplifying circuit and a subsequent stage amplifying circuit, and can sequentially amplify input signals, the preceding stage amplifying circuit comprises a preceding stage 4-watt GaN chip 10 and an input two-stage matching circuit, the input two-stage matching circuit comprises a series inductor and a first matching capacitor 9, and the series inductor is connected with the first matching capacitor 9 in series;
the rear-stage amplifying circuit comprises a rear-stage 24-watt GaN chip 13 and an input and output two-stage matching circuit, the input and output two-stage matching circuit comprises a series inductor, a winding chip inductor 14, a second matching capacitor 12 and a third matching capacitor 15, and the series inductor, the winding chip inductor 14, the second matching capacitor 12 and the third matching capacitor 15 are connected in series.
The device is matched with 50 ohms, so that the device is convenient to use; the device has small overall dimension, two-stage GaN chip matching is completed by using a limited space, and the chip capacitor and the gold wire are used for facilitating debugging; the bias circuit of the two-stage feed circuit is integrated inside, so that the device is more convenient to mount, and the integration is beneficial to improving the efficiency; the filter capacitor and the blocking capacitor enable the performance of the device to be more stable, and finally the S-band tiny dense type high-gain and high-efficiency hybrid integrated amplifier circuit is achieved.
In this embodiment, as shown in fig. 1 and 5, a bias circuit 16 is disposed inside the package case 1, the bias circuit 16 includes a bias circuit input terminal 161, a third bias capacitor 168, a fourth bias capacitor 169, a fifth bias capacitor 1611, and a bias circuit output terminal 162, and the bias circuit input terminal 161 is connected to the signal input terminal pin 3.
In the present embodiment, as shown in fig. 1 and 5, the bias circuit 16 further includes a first quarter-wave line 163, a second quarter-wave line 166, a third quarter-wave line 1612, and a fourth quarter-wave line 1613.
In this embodiment, as shown in fig. 1, the bias circuit 16 is connected in parallel with a first bias capacitor 61 and a second bias capacitor 7, and functions as a direct current resistance alternating current signal, and the input end and the output end of the front-stage 4-watt GaN chip 10 and the rear-stage 24-watt GaN chip 13 are both connected with a dc blocking capacitor 62, so as to prevent the direct current signal from passing through.
In the present embodiment, as shown in fig. 1, the front-stage 4-watt GaN chip 10 and the rear-stage 24-watt GaN chip 13 are both L-type matching circuits.
In the present embodiment, as shown in fig. 1 to 4, the front-stage 4 w GaN chip 10 is provided with a front-stage 4 w GaN chip gate 101 and a front-stage 4 w GaN chip drain 102, the rear-stage 24 w GaN chip 13 is provided with a rear-stage 24 w GaN chip gate 131 and a rear-stage 24 w GaN chip drain 132, and the front-stage 4 w GaN chip gate 101, the front-stage 4 w GaN chip drain 102, the rear-stage 24 w GaN chip gate 131 and the rear-stage 24 w GaN chip drain 132 are all connected with a filter capacitor 8 for filtering power supply noise.
In this embodiment, as shown in fig. 1, an attenuator 11 is connected between the front-stage 4-watt GaN chip 10 and the rear-stage 24-watt GaN chip 13, and the attenuator 11 makes the circuit more stable and improves the input standing wave of the 24-watt GaN chip.
As shown in fig. 1 to 5, the principle of the S-band hybrid integrated circuit provided in this embodiment is as follows:
1. connection of signal transmission path: a signal is input from a signal input end pin 3, is transmitted into a bias circuit input end 161, sequentially passes through an L-shaped matching circuit consisting of a first matching capacitor 9 and a winding chip inductor 14, enters a front-stage 4-watt GaN chip grid 101 in a front-stage 4-watt GaN chip 10, is amplified, then passes through a front-stage 4-watt GaN chip drain 102, passes through a third bias capacitor 168, is output from a fourth bias capacitor 169, is connected into an attenuator 11, then passes through the attenuator 11, sequentially passes through a rear-stage 24-watt GaN chip 13 consisting of a second matching capacitor 12 and a winding chip inductor 14, is amplified, then sequentially passes through the rear-stage 24-watt GaN chip drain 132 consisting of the winding chip inductor 14 and a third matching capacitor 15, and finally passes through a fifth bias capacitor 1611, and is finally output from a bias circuit output end 162;
2. connection of power supply lines: the grid power supply is connected with the grid power supply end 2, then connected into the filter capacitor 8, and divided into two paths, one path reaches the front-stage 4-watt GaN chip grid 101 through the second bias capacitor 7 and the third quarter-wave line 1612 in sequence, the other path reaches the rear-stage 24-watt GaN chip grid 131 through the first bias capacitor 61 and the fourth quarter-wave line 1613 in sequence, the drain power supply is connected with the drain power supply end 5, then connected into the filter capacitor 8, and divided into two paths, one path reaches the front-stage 4-watt GaN chip drain 102 through the second bias capacitor 7 and the first quarter-wave line 163 in sequence, and the other path reaches the rear-stage 24-watt GaN chip drain 132 through the second bias capacitor 7 and the second quarter-wave line 166 in sequence.
As used in the specification and in the claims, certain terms are used to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. "substantially" means within an acceptable error range, and a person skilled in the art can solve the technical problem within a certain error range to achieve the technical effect basically.
It is noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a good or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such good or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or system in which the element is included.
The foregoing description shows and describes several preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. An S-band hybrid integrated circuit comprises a packaging tube shell (1), and is characterized in that a two-stage amplification circuit is arranged inside the packaging tube shell (1), a grid power supply end (2), a signal input end pin (3), a signal output end pin (4) and a drain power supply end (5) which are connected with the two-stage amplification circuit are arranged on the packaging tube shell (1), the grid power supply end (2) is electrically connected with the two-stage amplification circuit through a microstrip line, and the signal output end pin (4) is electrically connected with the two-stage amplification circuit through the microstrip line;
the two-stage amplification circuit comprises a preceding stage amplification circuit and a subsequent stage amplification circuit, the preceding stage amplification circuit comprises a preceding stage 4-watt GaN chip (10) and an input two-stage matching circuit, the input two-stage matching circuit comprises a series inductor and a first matching capacitor (9), and the series inductor is connected with the first matching capacitor (9) in series;
the post-stage amplifying circuit comprises a post-stage 24-watt GaN chip (13) and an input and output two-stage matching circuit, the input and output two-stage matching circuit comprises a series inductor, a winding patch inductor (14), a second matching capacitor (12) and a third matching capacitor (15), and the series inductor, the winding patch inductor (14), the second matching capacitor (12) and the third matching capacitor (15) are connected in series.
2. An S-band hybrid integrated circuit as claimed in claim 1, wherein: the packaging structure is characterized in that a bias circuit (16) is arranged inside the packaging tube shell (1), the bias circuit (16) comprises a bias circuit input end (161), a third bias capacitor (168), a fourth bias capacitor (169), a fifth bias capacitor (1611) and a bias circuit output end (162), and the bias circuit input end (161) is connected with the signal input end pin (3).
3. An S-band hybrid integrated circuit as claimed in claim 2, wherein: the bias circuit (16) further includes a first quarter wave line (163), a second quarter wave line (166), a third quarter wave line (1612), and a fourth quarter wave line (1613).
4. An S-band hybrid integrated circuit as claimed in claim 2, wherein: the bias circuit (16) is connected with a first bias capacitor (61) and a second bias capacitor (7) in parallel, and the input end and the output end of the front-stage 4-watt GaN chip (10) and the rear-stage 24-watt GaN chip (13) are both connected with a blocking capacitor (62).
5. An S-band hybrid integrated circuit as claimed in claim 1, wherein: the front-stage 4-watt GaN chip (10) and the rear-stage 24-watt GaN chip (13) are both L-shaped matching circuits.
6. An S-band hybrid integrated circuit as claimed in claim 1, wherein: preceding level 4 watts GaN chip grid (101) and preceding level 4 watts GaN chip drain electrode (102) are provided with on preceding level 4 watts GaN chip (10), be provided with back level 24 watts GaN chip grid (131) and back level 24 watts GaN chip drain electrode (132) on back level 24 watts GaN chip (13), preceding level 4 watts GaN chip grid (101), preceding level 4 watts GaN chip drain electrode (102), back level 24 watts GaN chip grid (131) and back level 24 watts GaN chip drain electrode (132) all are connected with filter capacitor (8).
7. An S-band hybrid integrated circuit as claimed in claim 1, wherein: an attenuator (11) is connected between the front-stage 4-watt GaN chip (10) and the rear-stage 24-watt GaN chip (13).
8. The method of controlling an S-band hybrid integrated circuit according to any one of claims 1 to 7, wherein: the signal is input from a signal input terminal pin (3), transmitted into a bias circuit input terminal (161), then sequentially passes through an L-shaped matching circuit consisting of a first matching capacitor (9) and a winding chip inductor (14), enters a front-stage 4-watt GaN chip grid electrode (101) in a front-stage 4-watt GaN chip (10), is amplified, then passes through a front-stage 4-watt GaN chip drain electrode (102), passes through a third bias capacitor (168), is output from a fourth bias capacitor (169), is connected into an attenuator (11), then passes through the attenuator (11), sequentially passes through a rear-stage 24-watt GaN chip (13) consisting of a second matching capacitor (12) and a winding chip inductor (14), is amplified, then sequentially passes through a rear-stage 24-watt GaN chip (13) consisting of a winding chip inductor (14) and a third matching capacitor (15), and finally passes through a fifth bias capacitor (1611), the signal is finally output from the bias circuit output (162).
9. The method of controlling an S-band hybrid integrated circuit according to any one of claims 1 to 7, wherein: the grid power supply is connected with the grid power supply end (2), and then is connected into the filter capacitor (8), the grid power supply is divided into two paths, one path of the grid power supply reaches a front-stage 4-watt GaN chip grid (101) through the second bias capacitor (7) and the third quarter-wave line (1612), the other path of the grid power supply reaches a rear-stage 24-watt GaN chip grid (131) through the first bias capacitor (61) and the fourth quarter-wave line (1613), the drain power supply is connected with the drain power supply end (5), and then is connected into the filter capacitor (8), the grid power supply is divided into two paths, one path of the grid power supply reaches the front-stage 4-watt GaN chip drain (102) through the second bias capacitor (7) and the first quarter-wave line (163), and the other path of the grid power supply reaches the rear-stage 24-watt GaN chip drain (132) through the.
CN202011559574.4A 2020-12-25 2020-12-25 S-band hybrid integrated circuit Pending CN112532190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011559574.4A CN112532190A (en) 2020-12-25 2020-12-25 S-band hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011559574.4A CN112532190A (en) 2020-12-25 2020-12-25 S-band hybrid integrated circuit

Publications (1)

Publication Number Publication Date
CN112532190A true CN112532190A (en) 2021-03-19

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