CN112531008A - Manufacturing method of Schottky diode and Schottky diode - Google Patents
Manufacturing method of Schottky diode and Schottky diode Download PDFInfo
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- CN112531008A CN112531008A CN201910886064.9A CN201910886064A CN112531008A CN 112531008 A CN112531008 A CN 112531008A CN 201910886064 A CN201910886064 A CN 201910886064A CN 112531008 A CN112531008 A CN 112531008A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 239000000956 alloy Substances 0.000 claims abstract description 33
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 33
- 238000002161 passivation Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 15
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 15
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 15
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 14
- 239000011574 phosphorus Substances 0.000 claims abstract description 14
- -1 phosphorus ions Chemical class 0.000 claims abstract description 13
- 238000002513 implantation Methods 0.000 claims abstract description 10
- 229910052796 boron Inorganic materials 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- 150000001875 compounds Chemical class 0.000 description 2
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66143—Schottky diodes
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Abstract
The invention discloses a manufacturing method of a Schottky diode and the Schottky diode, wherein the manufacturing method comprises the following steps: forming an STI region on the P substrate; carrying out deep N-type implantation on the P substrate by using phosphorus ions to form DNW; performing boron ion implantation on one side of the STI region in DNW to form a P-layer guard ring, wherein the P-layer guard ring consists of a plurality of P-doped regions which are mutually separated; performing phosphorus ion implantation on the other side of the STI region in DNW to form an N + layer; depositing a metal layer or an alloy layer on the N + layer and the P-layer guard ring; forming SiO on the metal layer or the alloy layer2A passivation layer; in the SiO2A contact hole is formed in the passivation layer; and leading out an electrode from the contact hole. The technical scheme of the invention can realize that the total area of the Schottky diode is not increasedAnd on the premise of keeping the breakdown voltage, the forward conducting current is increased.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a manufacturing method of a Schottky diode and the Schottky diode.
Background
A schottky diode is a metal half-contact type semiconductor device. Compared with a PN junction diode, the diode has the advantages that: the forward conduction threshold voltage and the forward voltage are reduced, and the conductive device is a majority carrier conductive device, and the reverse recovery charge is less, so the switching speed is high, the loss is less, and the conductive device is suitable for high-frequency application.
The existing Schottky diode P-doped region manufacturing method comprises the following steps: p-type ion implantation is carried out in DNW (deep N trap) by using an annular mask plate by using an ion implantation method to form an annular P-doped region. The anode of the Schottky diode manufactured by the method is formed by combining the annular P-layer doped region and metal, and the cathode is formed by the N-type heavily doped region. At the forward conducting voltage, the contact area of both electrodes is not large enough, and the forward conducting current is not high. The increase in on current is usually achieved by increasing the die area, but the increase in area leads to an increase in manufacturing cost. Therefore, how to increase the forward conduction current without increasing the total area of the schottky diode and maintaining the breakdown voltage in the prior art is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention provides a manufacturing method of a Schottky diode and the Schottky diode, aiming at solving the technical problem that forward conducting current is increased on the premise of not increasing the total area of the Schottky diode and keeping breakdown voltage in the prior art.
The invention solves the technical problems through the following technical scheme:
a method of fabricating a schottky diode, the method comprising:
forming an STI region on the P substrate;
carrying out deep N-type implantation on the P substrate by using phosphorus ions to form DNW;
performing boron ion implantation on one side of the STI region in the DNW to form a P-layer guard ring, wherein the P-layer guard ring consists of a plurality of P-doped regions in rectangular shapes, and the P-doped regions are mutually separated;
performing phosphorus ion implantation on the other side of the STI region in the DNW to form an N + layer;
depositing a metal layer or an alloy layer on the N + layer and the P-layer guard ring;
forming on the metal layer or the alloy layerTo SiO2A passivation layer;
in the SiO2A contact hole is formed in the passivation layer;
and leading out an electrode from the contact hole.
Preferably, the electrodes include an anode and a cathode, and space charge regions of adjacent P-doped regions are pinched off when a reverse voltage is applied between the anode and the cathode.
Preferably, the area of the P-doped region is 1um2The above.
Preferably, SiO is formed on the metal layer or the alloy layer2The passivation layer includes:
forming SiO on the metal layer or the alloy layer by chemical vapor deposition2And a passivation layer.
Preferably, the metal layer is a titanium metal layer, and the alloy layer is a titanium nitride alloy layer;
in the SiO2The step of forming the contact hole on the passivation layer comprises the following steps:
in the SiO2And the passivation layer is provided with a contact hole with an inner wall being a titanium or titanium nitride adhesion layer.
Preferably, the step of forming the STI region on the P-substrate includes:
setting a mask layer on the P substrate, and etching a groove according to a preset pattern of the mask layer;
filling dry oxygen generated SiO into the groove2；
Filling the SiO with instrument pairs2The trench of (a) is polished to form the STI region.
A schottky diode, comprising:
an STI region located on the P substrate;
a DNW including the STI region located in the P-substrate;
the P-layer guard ring is positioned on one side of the STI region in the DNW and consists of a plurality of P-doped regions in rectangular shapes, and the P-doped regions are mutually separated;
an N + layer on the other side of the STI region in the DNW;
a metal layer or alloy layer located over the P-layer guard ring and the N + layer;
SiO located above the metal layer or the alloy layer2A passivation layer;
is located on the SiO2A contact hole in the passivation layer, and an electrode leading from the contact.
Preferably, the electrodes include an anode and a cathode, and space charge regions of adjacent P-doped regions are pinched off when a reverse voltage is applied between the anode and the cathode.
Preferably, the area of the P-doped region is 1um2The above.
Preferably, the SiO2A passivation layer is formed on the metal layer or the alloy layer by chemical vapor deposition.
Preferably, the metal layer is a titanium metal layer, and the alloy layer is a titanium nitride alloy layer;
the inner wall of the contact hole includes an adhesion layer of titanium or titanium nitride.
On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.
The positive progress effects of the invention are as follows: the manufacturing method of the Schottky diode and the Schottky diode provided by the invention can increase forward conducting current on the premise of not increasing the total area of the Schottky diode and keeping breakdown voltage by spacing the P-layer protection ring into a plurality of rectangular blocks of the P-doped region without increasing the tube core area of the Schottky diode.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a schottky diode according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a schottky diode according to embodiment 2 of the present invention.
Fig. 3 is a schematic diagram illustrating a distribution of a plurality of P-doped regions in a schottky diode according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a method for manufacturing a schottky diode, as shown in fig. 1, the method includes the following steps:
step S1: forming an STI region on the P substrate;
the P substrate can be specifically P-type substrate silicon, the STI region is a shallow trench isolation region, when the shallow trench isolation region is manufactured, firstly a mask layer is required to be arranged on the P-type substrate silicon, a trench is etched according to a preset pattern of the mask layer, and then the trench is filled with SiO generated by dry oxygen2(silicon dioxide) and then filling the SiO with instrument pairs2The trench of (a) is polished to form the STI region.
Step S2: carrying out deep N-type implantation on the P substrate by using phosphorus ions to form DNW (deep N well);
specifically, when implanting phosphorus ions, the implantation energy may be 65 kev. After ion implantation, ion diffusion is needed, the adopted diffusion temperature can be 1000 ℃, and the temperature is N2The reaction is carried out for 6min under the environment.
Step S3: performing boron ion implantation on one side of the STI region in the DNW to form a P-layer guard ring, wherein the P-layer guard ring consists of a plurality of P-doped regions in rectangular shapes, and the P-doped regions are mutually separated;
in this embodiment, the electrode includes an anode and a cathode, and when a reverse voltage is applied between the anode and the cathode, the space charge regions of the adjacent P-doped regions are pinched off, that is, when a reverse voltage is applied between the two electrodes, the space charge regions of the P-doped regions expand, and the space charge regions of the two adjacent P-doped regions have a cross region due to the expansion, so that the reverse breakdown voltage can be ensured to be constant.
Further, the area of the P-doped region is 1um2The above.
Preferably, the first and second electrodes are formed of a metal,the implantation energy that can be used when implanting boron ions is 70 Kev. After ion implantation, diffusion is also required, and the diffusion temperature is preferably 1100 ℃ in N2The reaction is carried out for 30min under the environment.
Step S4: performing phosphorus ion implantation on the other side of the STI region in the DNW to form an N + layer;
specifically, when the phosphorus ions are implanted in step S4, the implantation energy may be 65 kev. After ion implantation, ion diffusion is needed, the adopted diffusion temperature is 1000 ℃, and the temperature is N2The reaction is carried out for 20min under the environment.
Step S5: depositing a metal layer or an alloy layer on the N + layer and the P-layer guard ring;
preferably, the metal layer may be a titanium metal layer, and the alloy layer may be a titanium nitride alloy layer.
Step S6: forming SiO on the metal layer or the alloy layer2A passivation layer;
specifically, the SiO may be formed using chemical vapor deposition2And a passivation layer. The chemical vapor deposition is a chemical technology, and the technology is mainly a method for generating a film by performing chemical reaction on the surface of a substrate by using one or more gas-phase compounds or simple substances containing film elements.
Step S7: in the SiO2A contact hole is formed in the passivation layer;
in particular, it is possible to use in the SiO2And the passivation layer is provided with a contact hole with an inner wall being a titanium or titanium nitride adhesion layer.
Step S8: and leading out an electrode from the contact hole.
According to the manufacturing method of the Schottky diode provided by the embodiment, when the Schottky diode is manufactured, the area of a tube core of the Schottky diode is not increased, but the P-layer protection rings are spaced into the form of the plurality of rectangular blocks of the P-doped region, so that forward conducting current is increased on the premise that the total area of the Schottky diode is not increased and breakdown voltage is kept.
Example 2
The present embodiment provides a schottky diode, as shown in fig. 2 to 3, including:
an STI region 4 located on the P substrate;
DNW5 located in the P-substrate including the STI region 4;
a P-layer guard ring located at one side of the STI region 4 in the DNW5, wherein the P-layer guard ring is composed of a plurality of P-doped regions 2 with rectangular shapes, and the P-doped regions 2 are mutually separated;
an N + layer 6 on the other side of the STI region 4 in the DNW 5;
a metal or alloy layer located over the P-layer guard ring and the N + layer 6;
SiO located above the metal layer or the alloy layer2A passivation layer;
is located on the SiO2Contact holes in the passivation layer, and electrodes leading out of said contact holes 8.
Specifically, the P substrate may be a P-type substrate silicon, and the STI region 4 is a shallow trench isolation region.
The DNW5 may be formed by implanting phosphorus ions, and specifically, the implantation energy may be 65kev when the phosphorus ions are implanted. After ion implantation, ion diffusion is needed, the adopted diffusion temperature is 1000 ℃, and the temperature is N2This was carried out for 6min under ambient conditions to obtain DNW5 in this example.
The P-layer guard ring may be formed by implanting boron ions, and specifically, the implantation energy that may be used when implanting boron ions is 70 Kev. After ion implantation, diffusion is also required, and the diffusion temperature is preferably 1100 ℃ in N2The process is performed for 30min under the environment to form the P-layer guard ring in this embodiment.
In this embodiment, the electrode includes an anode 3 and a cathode 1, when a reverse voltage is applied between the anode 3 and the cathode 1, the space charge regions of the adjacent P-doped regions 2 are pinched off, that is, when a reverse voltage is applied between the two electrodes, the space charge regions of the P-doped regions 2 expand, and the space charge regions of the adjacent two P-doped regions 2 have an intersecting region due to the expansion, so that the reverse breakdown voltage can be ensured to be constant.
The area of the P-doped region 2 is 1um2The above.
The schottky diode further comprises an active region 7, the active region 7 being generally defined by the STI regions 4, in particular the substrate between adjacent STI regions 4 may be referred to as active region 7.
The schottky diode further comprises an anode metal wiring area 9 and a cathode metal wiring area 10, wherein the anode metal wiring area 9 is used for communicating the contact hole 8 belonging to the anode area with the anode 3, and the cathode metal wiring area 10 is used for communicating the contact hole 8 belonging to the cathode area with the cathode 1.
The N + layer 6 on the other side of the STI region 4 in the DNW5 may be formed by implanting phosphorus ions. Specifically, when implanting phosphorus ions, the implantation energy may be 65 kev. After ion implantation, ion diffusion is needed, the adopted diffusion temperature is 1000 ℃, and the temperature is N2This is done for 20min in ambient to form the N + layer 6 in this example.
Further, the SiO2A passivation layer may be formed on the metal layer or the alloy layer by chemical vapor deposition. The chemical vapor deposition is a chemical technology, and the technology is mainly a method for generating a film by performing chemical reaction on the surface of a substrate by using one or more gas-phase compounds or simple substances containing film elements.
In this embodiment, the metal layer may be a titanium metal layer, and the alloy layer may be a titanium nitride alloy layer, based on which the inner wall of the contact hole may include a titanium or titanium nitride adhesion layer.
The P-layer guard rings in the schottky diode provided by this embodiment are spaced into a plurality of rectangular blocks of P-doped regions, so that forward conduction current is increased on the premise that the total area of the schottky diode is not increased and breakdown voltage is maintained.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (11)
1. A manufacturing method of a Schottky diode is characterized by comprising the following steps:
forming an STI region on the P substrate;
carrying out deep N-type implantation on the P substrate by using phosphorus ions to form DNW;
performing boron ion implantation on one side of the STI region in the DNW to form a P-layer guard ring, wherein the P-layer guard ring consists of a plurality of P-doped regions in rectangular shapes, and the P-doped regions are mutually separated;
performing phosphorus ion implantation on the other side of the STI region in the DNW to form an N + layer;
depositing a metal layer or an alloy layer on the N + layer and the P-layer guard ring;
forming SiO on the metal layer or the alloy layer2A passivation layer;
in the SiO2A contact hole is formed in the passivation layer;
and leading out an electrode from the contact hole.
2. The method of claim 1, wherein said electrodes comprise an anode and a cathode, and wherein space charge regions of adjacent P-doped regions are pinched off when a reverse voltage is applied between said anode and said cathode.
3. The method of claim 1, wherein the P-doped region has an area of 1um2The above.
4. The method of claim 1, wherein SiO is formed on the metal layer or the alloy layer2The passivation layer includes:
at the placeForming SiO on the metal layer or the alloy layer by chemical vapor deposition2And a passivation layer.
5. The method of claim 1, wherein the Schottky diode is formed by a plasma etching process,
the metal layer is a titanium metal layer, and the alloy layer is a titanium nitride alloy layer;
in the SiO2The step of forming the contact hole on the passivation layer comprises the following steps:
in the SiO2And the passivation layer is provided with a contact hole with an inner wall being a titanium or titanium nitride adhesion layer.
6. The method of any of claims 1-5, wherein the step of forming the STI region on the P-substrate comprises:
setting a mask layer on the P substrate, and etching a groove according to a preset pattern of the mask layer;
filling dry oxygen generated SiO into the groove2；
Filling the SiO with instrument pairs2The trench of (a) is polished to form the STI region.
7. A schottky diode, comprising:
an STI region located on the P substrate;
a DNW including the STI region located in the P-substrate;
the P-layer guard ring is positioned on one side of the STI region in the DNW and consists of a plurality of P-doped regions in rectangular shapes, and the P-doped regions are mutually separated;
an N + layer on the other side of the STI region in the DNW;
a metal layer or alloy layer located over the P-layer guard ring and the N + layer;
SiO located above the metal layer or the alloy layer2A passivation layer;
is located on the SiO2Contact holes in the passivation layer toAnd an electrode leading from the contact.
8. The schottky diode of claim 7 wherein said electrodes comprise an anode and a cathode, and wherein space charge regions of adjacent P-doped regions are pinched off when a reverse voltage is applied between said anode and said cathode.
9. The schottky diode of claim 7 wherein the P-doped region has an area of 1um2The above.
10. The schottky diode of claim 7 wherein said SiO is2A passivation layer is formed on the metal layer or the alloy layer by chemical vapor deposition.
11. The schottky diode of any of claims 7-10 wherein the metal layer is a titanium metal layer and the alloy layer is a titanium nitride alloy layer;
the inner wall of the contact hole includes an adhesion layer of titanium or titanium nitride.
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| CN201910886064.9A CN112531008A (en) | 2019-09-19 | 2019-09-19 | Manufacturing method of Schottky diode and Schottky diode |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070278581A1 (en) * | 2006-06-06 | 2007-12-06 | Texas Instruments Incorporated | Semiconductor dual guardring arrangement |
| CN102315281A (en) * | 2010-09-07 | 2012-01-11 | 成都芯源系统有限公司 | Schottky diode and manufacturing method thereof |
| US20160093748A1 (en) * | 2012-10-04 | 2016-03-31 | Cree, Inc. | Passivation for semiconductor devices |
| US20190140071A1 (en) * | 2017-11-04 | 2019-05-09 | Globalfoundries Singapore Pte. Ltd. | High voltage schottky diode and manufacturing method thereof |
-
2019
- 2019-09-19 CN CN201910886064.9A patent/CN112531008A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070278581A1 (en) * | 2006-06-06 | 2007-12-06 | Texas Instruments Incorporated | Semiconductor dual guardring arrangement |
| CN102315281A (en) * | 2010-09-07 | 2012-01-11 | 成都芯源系统有限公司 | Schottky diode and manufacturing method thereof |
| US20160093748A1 (en) * | 2012-10-04 | 2016-03-31 | Cree, Inc. | Passivation for semiconductor devices |
| US20190140071A1 (en) * | 2017-11-04 | 2019-05-09 | Globalfoundries Singapore Pte. Ltd. | High voltage schottky diode and manufacturing method thereof |
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