CN112530798A - Semiconductor structure and manufacturing and thinning method thereof - Google Patents
Semiconductor structure and manufacturing and thinning method thereof Download PDFInfo
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- CN112530798A CN112530798A CN202011409672.XA CN202011409672A CN112530798A CN 112530798 A CN112530798 A CN 112530798A CN 202011409672 A CN202011409672 A CN 202011409672A CN 112530798 A CN112530798 A CN 112530798A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 85
- 238000005530 etching Methods 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000002346 layers by function Substances 0.000 claims abstract description 49
- 239000000872 buffer Substances 0.000 claims abstract description 36
- 239000007788 liquid Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 27
- 239000000243 solution Substances 0.000 claims description 28
- 238000000227 grinding Methods 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 12
- 229910052755 nonmetal Inorganic materials 0.000 claims description 12
- 239000011224 oxide ceramic Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 6
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 claims description 4
- 238000003756 stirring Methods 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 claims description 3
- 229910001506 inorganic fluoride Inorganic materials 0.000 claims description 3
- 229910001853 inorganic hydroxide Inorganic materials 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000002861 polymer material Substances 0.000 claims description 3
- 239000012266 salt solution Substances 0.000 claims description 3
- 150000004760 silicates Chemical class 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000008569 process Effects 0.000 description 12
- 238000003486 chemical etching Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000007983 Tris buffer Substances 0.000 description 2
- 229960001484 edetic acid Drugs 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- BTBUEUYNUDRHOZ-UHFFFAOYSA-N Borate Chemical compound [O-]B([O-])[O-] BTBUEUYNUDRHOZ-UHFFFAOYSA-N 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000006174 pH buffer Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 229910001404 rare earth metal oxide Inorganic materials 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Abstract
The application provides a semiconductor structure and manufacturing and thinning methods thereof, and relates to the technical field of semiconductor material processing. The semiconductor structure comprises a substrate, a buffer layer, a thinning functional layer and a device layer, wherein the substrate, the buffer layer, the thinning functional layer and the device layer are connected layer by layer; and the etching rate of the substrate and the target etching liquid is more than or equal to 2 times of the etching rate of the thinned functional layer and the target etching liquid. The semiconductor structure and the manufacturing and thinning methods thereof have the advantages of being high in thinning efficiency and good in quality.
Description
Technical Field
The application relates to the technical field of semiconductor material processing, in particular to a semiconductor structure and manufacturing and thinning methods thereof.
Background
In recent years, with the development of network technology, electronic devices and instruments are required to have multiple functions, high reliability, small size and portability, and the requirements for the overall dimensions of devices are increasingly smaller. The miniaturization requirement of the overall dimension of the device, the improvement of the packaging structure form, the development and progress of reducing the thermal resistance, improving the heat dissipation capability of the chip and the like. The chip used for packaging is required to be thinner and thinner, and the quality is required to be higher and higher. Ultra-thin chips are required in many emerging semiconductor fabrication fields. In these fields, the trend toward ultra-thinning of chips is evident.
Most of the existing chip thinning methods are mechanical grinding, namely thinning is carried out by using a thinning machine or a polishing machine, the thinning thickness is greatly restricted by equipment, and in a device layer on a chip, a transistor circuit and a connecting wire are complex, so that stress is uneven, and the quality of the obtained chip is poor after mechanical grinding. Meanwhile, the efficiency is low by adopting a mechanical grinding mode.
Disclosure of Invention
The application aims to provide a semiconductor structure and manufacturing and thinning methods thereof, and aims to solve the problems of poor quality and low efficiency in chip thinning in the prior art.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides a semiconductor structure, where the semiconductor structure includes a substrate, a buffer layer, a thinning functional layer, and a device layer, where the substrate, the buffer layer, the thinning functional layer, and the device layer are connected layer by layer;
and the etching rate of the substrate and the target etching liquid is more than or equal to 2 times of the etching rate of the thinned functional layer and the target etching liquid.
Furthermore, the material for manufacturing the thinning functional layer comprises silicon, gallium nitride, silicon carbide, silicate, metal oxide ceramic, non-metal oxide ceramic, metal nitride ceramic and non-metal nitride ceramic.
Further, the material for preparing the target etching solution comprises organic hydroxide, inorganic hydroxide, organic fluoride, inorganic fluoride and pH buffer salt solution.
Further, the thickness of the thinned functional layer is less than or equal to 5 μm.
Further, the substrate is made of a material including silicon, gallium nitride, silicon carbide, silicate, metal oxide ceramic, non-metal oxide ceramic, metal nitride ceramic, and non-metal nitride ceramic.
Furthermore, the material for manufacturing the buffer layer comprises an organic polymer material, polycrystalline silicon, silicate and oxide, and the thickness of the buffer layer is 100 nm-1000 μm.
In a second aspect, embodiments of the present application further provide a method for fabricating a semiconductor structure, where the method is used to fabricate the semiconductor structure as described above, and the method includes:
providing a substrate;
and sequentially manufacturing a buffer layer, a thinning functional layer and a device layer on the substrate, wherein the etching rate of the substrate and the target etching liquid is more than or equal to 2 times that of the thinning functional layer and the target etching liquid.
In a third aspect, an embodiment of the present application further provides a semiconductor structure thinning method, for thinning the above semiconductor structure, where the method includes:
and placing the semiconductor structure in target etching liquid until the substrate and the buffer layer are completely etched by the target etching liquid.
Further, before the step of placing the semiconductor structure in the target etching solution, the method further comprises:
placing the semiconductor structure in an electrochemical etching solution, and applying voltage on a substrate and a device layer of the semiconductor structure;
and grinding the substrate to remove the substrate.
Further, the step of grinding the substrate comprises:
and grinding the substrate by any one of stirring, jet flow, vortex, oscillation and ultrasonic wave.
Compared with the prior art, the method has the following beneficial effects:
the application provides a semiconductor structure and a manufacturing and thinning method thereof, wherein the semiconductor structure comprises a substrate, a buffer layer, a thinning functional layer and a device layer, wherein the substrate, the buffer layer, the thinning functional layer and the device layer are connected layer by layer; and the etching rate of the substrate and the target etching liquid is more than or equal to 2 times of the etching rate of the thinned functional layer and the target etching liquid. Because the difference between the etching rate of the substrate and the etching rate of the thinning functional layer is large, when the semiconductor structure is placed in target etching liquid for chemical etching, after the substrate and the buffer layer are completely etched, the device layer cannot be influenced at the moment due to the blocking of the thinning functional layer, and therefore the effect that the substrate and the buffer layer can be etched and the device layer cannot be influenced can be achieved. Meanwhile, the thinning function layer can be made very thin in the manufacturing process, so that the effect of thinning the semiconductor structure can be achieved. Moreover, the efficiency is higher than that of the traditional mechanical grinding because of adopting chemical etching; meanwhile, a chemical etching mode is adopted, so that the influence of uneven stress is avoided, and the quality of the manufactured thinned semiconductor structure is better.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic view of a semiconductor structure according to an embodiment of the present disclosure.
Fig. 2 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.
Fig. 3 is a schematic flowchart of a semiconductor structure thinning method according to an embodiment of the present disclosure.
In the figure: 100-a semiconductor structure; 110-a substrate; 120-a buffer layer; 130-thinning the functional layer; 140-device layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
First embodiment
As described in the background art, most of the existing chip thinning methods are mechanical grinding, i.e., thinning is performed by using a thinning machine or a polishing machine, the thinned thickness is greatly restricted by equipment, and in a device layer on a chip, a transistor circuit and a connecting wire are complex, so that stress is uneven, and therefore, after mechanical grinding, the obtained chip has poor quality. Meanwhile, the efficiency is low by adopting a mechanical grinding mode.
In view of the above, in order to solve the above problems, the present application provides a semiconductor structure, in which a thinned functional layer is provided, and an etching rate of a substrate and a target etching solution is greater than or equal to 2 times of an etching rate of the thinned functional layer and the target etching solution. When the semiconductor structure is placed in the target etching liquid, after the substrate and the buffer layer are etched, the remaining thinning functional layer can play a certain role in blocking, and then after chemical etching, the thinning effect can be achieved, and devices on the semiconductor structure cannot be damaged.
The following is an exemplary illustration of the semiconductor mechanism provided in the present application:
referring to fig. 1, the semiconductor structure 100 includes a substrate 110, a buffer layer 120, a thinned functional layer 130, and a device layer 140, wherein the substrate 110, the buffer layer 120, the thinned functional layer 130, and the device layer 140 are connected in a layer-by-layer manner. And the etching rate of the substrate 110 and the target etching solution is greater than or equal to 2 times of the etching rate of the thinned functional layer 130 and the target etching solution.
The substrate 110 provided herein may be made of, but is not limited to, doped or undoped silicon, gallium nitride, silicon carbide, silicate, metal oxide ceramic, non-metal oxide ceramic, metal nitride ceramic, or non-metal nitride ceramic.
The material of the buffer layer 120 includes organic polymer materials, polysilicon, silicates, oxides, and other materials that are easily bonded or bonded. Alternatively, the buffer layer 120 may have a thickness of 100nm to 1000 μm.
The material of the thinned functional layer 130 includes, but is not limited to, doped or undoped silicon, gallium nitride, silicon carbide, silicate, metal oxide ceramic, non-metal oxide ceramic, metal nitride ceramic, and non-metal nitride ceramic, and the present application does not limit the material of the above-mentioned layered structure. The thinned functional layer 130 has good bonding or bonding performance with the buffer layer 120, and has a large chemical etching activity difference with the substrate 110, so that the etching rate of the substrate 110 and the target etching liquid is greater than or equal to 2 times of the etching rate of the thinned functional layer 130 and the target etching liquid.
Meanwhile, in actual manufacturing, the thinned functional layer 130 may be further configured as one or more layers according to actual application requirements, and the components are any one or more combinations of the above.
The device layer 140 refers to an array of integrated circuit structures of various scales, and the host material includes, but is not limited to, elemental semiconductor materials such as germanium or silicon, and semiconductor materials of compounds of group iii and group v. Such as a nitride transistor device included in device layer 140.
The material for preparing the target etching solution comprises organic hydroxide, inorganic hydroxide, organic fluoride and inorganic fluoride, and the working composition table is shown in table one:
watch 1
The material of the target etching liquid can be one or more material combinations in the table I. Of course, the target etching solution provided in the present application may also be etching solution of other materials, such as pH buffered salt solution including EDTA (ethylene diamine tetraacetic acid), Tris (Tris), phosphate, borate, acetate, etc., which is not limited in this application.
Through the above arrangement, when the semiconductor structure 100 is placed in the target etching solution, the target etching solution etches the substrate 110 and the buffer layer 120, and when the semiconductor structure is etched to the thinning functional layer 130, the reactivity of the thinning functional layer 130 and the etching solution is greatly different, so that the semiconductor structure 100 is etched to play a role in blocking, and the device layer 140 is not damaged. It is understood that after the semiconductor structure 100 is fabricated, the surface and the side of the device layer 140 are encapsulated by the insulating layer, so as to prevent the surface and the side of the device layer 140 from being etched during the etching process.
After the substrate 110 and the buffer layer 120 are chemically etched away, the semiconductor structure 100 only has the thinned functional layer 130 and the device layer 140, and the thinned functional layer 130 can be physically made thinner during the manufacturing process. It can achieve the effect of thinning. In general, the thickness of the thinned functional layer 130 may be only 5 μm or less.
Second embodiment
Referring to fig. 2, an embodiment of the present invention further provides a method for fabricating a semiconductor structure, which is capable of fabricating the semiconductor structure according to the first embodiment, and the method includes:
s201, providing a substrate.
S202, sequentially manufacturing a buffer layer, a thinning functional layer and a device layer on the substrate, wherein the etching rate of the substrate and the target etching liquid is greater than or equal to 2 times of the etching rate of the thinning functional layer and the target etching liquid.
The material of the thinned functional layer and the material of the substrate may be any one of the materials described in the first embodiment, which is not limited in this application.
In addition, the manufacturing process of the thinned functional layer is not limited at all in the application, and the thinned functional layer can be manufactured by an epitaxial process or a direct bonding process, so that the thinned functional layer can be manufactured to be less than 5 microns thick.
Third embodiment
Referring to fig. 3, an embodiment of the present application further provides a method for thinning a semiconductor structure, which can be used to thin the semiconductor structure according to the first embodiment. As an optional implementation, the method includes:
s302, the semiconductor structure is placed in the target etching liquid until the substrate and the buffer layer are completely etched by the target etching liquid.
That is, in the present application, the semiconductor structure is thinned by chemical etching, and the material of the target etching solution has been described in detail in the first embodiment, and is not described herein again.
It can be understood that, in the process of manufacturing the semiconductor structure, the front surface and the side surface of the device layer are encapsulated, so that the etching of the device material by the target etching solution can be isolated. When the semiconductor structure is placed in the target etching solution, the target etching solution can etch away the bottom and the buffer layer.
In practical applications, if only chemical etching is used, the etching rate is still relatively slow. In view of this, as another possible implementation manner, the semiconductor structure thinning method provided by the present application may further use an electrochemical etching manner to accelerate the etching rate. That is, before the step of S302, the method further includes:
s301-1, placing the semiconductor structure in an electrochemical etching solution, and applying voltage to a substrate and a device layer of the semiconductor structure.
S301-2, grinding the substrate to remove the substrate.
That is, in the present application, the semiconductor structure is first placed in an electrochemical etching solution, and then a voltage is applied across the substrate and the device layer. Optionally, the anode is connected with the substrate, and the cathode is connected with the device layer, so that the substrate is changed into a sponge structure in the electrochemical etching process due to the fact that the buffer layer is not conductive, and the substrate is fragile and easy to remove. The substrate is taken as a silicon material for explanation, and the electrochemical etching liquid takes hydrofluoric acid as an example, when the electrochemical etching is performed, the silicon substrate is converted into silicon dioxide, the substrate is converted into a sponge structure, and the middle of the substrate comprises a plurality of bubble structures.
On the basis of the above, the substrate can be easily removed by a mechanical grinding process, and of course, the substrate can be removed by other methods. And (3) flowing into the selective etching solution, grinding the substrate by using metal/rare earth oxide, metal nitride, special ceramic, diamond, silicon carbide and other particles which are compatible with the selective etching solution as mechanical grinding materials by adopting processes of stirring, jet flow, vortex, oscillation, ultrasonic wave and the like in the grinding process, and further removing the substrate. And because the substrate is removed by adopting the processes of stirring, jet flow, vortex, oscillation, ultrasonic wave and the like, the influence of uneven stress can not be received, so that the quality of the thinned semiconductor structure is better, and the thinning efficiency is greatly improved.
After the substrate is removed, the semiconductor structure is placed in a target etching solution, and then the buffer layer can be etched by the target etching solution, so that thinning is realized.
By the aid of the semiconductor structure thinning method, the semiconductor structure cannot be thinned quickly, and the thinned semiconductor structure is better in quality.
In summary, the present application provides a semiconductor structure and a method for manufacturing and thinning the same, the semiconductor structure includes a substrate, a buffer layer, a thinning functional layer and a device layer, the substrate, the buffer layer, the thinning functional layer and the device layer are connected layer by layer; and the etching rate of the substrate and the target etching liquid is more than or equal to 2 times of the etching rate of the thinned functional layer and the target etching liquid. Because the difference between the etching rate of the substrate and the etching rate of the thinning functional layer is large, when the semiconductor structure is placed in target etching liquid for chemical etching, after the substrate and the buffer layer are completely etched, the device layer cannot be influenced at the moment due to the blocking of the thinning functional layer, and therefore the effect that the substrate and the buffer layer can be etched and the device layer cannot be influenced can be achieved. Meanwhile, the thinning function layer can be made very thin in the manufacturing process, so that the effect of thinning the semiconductor structure can be achieved. Moreover, the efficiency is higher than that of the traditional mechanical grinding because of adopting chemical etching; meanwhile, a chemical etching mode is adopted, so that the influence of uneven stress is avoided, and the quality of the manufactured thinned semiconductor structure is better.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. The semiconductor structure is characterized by comprising a substrate, a buffer layer, a thinning functional layer and a device layer, wherein the substrate, the buffer layer, the thinning functional layer and the device layer are connected layer by layer;
and the etching rate of the substrate and the target etching liquid is more than or equal to 2 times of the etching rate of the thinned functional layer and the target etching liquid.
2. The semiconductor structure of claim 1, wherein the material from which the thinned functional layer is made comprises silicon, gallium nitride, silicon carbide, silicates, metal oxide ceramics, non-metal oxide ceramics, metal nitride ceramics, and non-metal nitride ceramics.
3. The semiconductor structure of claim 1, wherein the target etchant is made of a material comprising an organic hydroxide, an inorganic hydroxide, an organic fluoride, an inorganic fluoride, and a pH buffered salt solution.
4. The semiconductor structure of claim 1, wherein the thinned functional layer has a thickness of less than or equal to 5 μ ι η.
5. The semiconductor structure of claim 1, wherein the substrate is made of a material comprising silicon, gallium nitride, silicon carbide, silicates, metal oxide ceramics, non-metal oxide ceramics, metal nitride ceramics, and non-metal nitride ceramics.
6. The semiconductor structure of claim 1, wherein the buffer layer is made of a material comprising an organic polymer material, polysilicon, a silicate, and an oxide, and the buffer layer has a thickness of 100nm to 1000 μm.
7. A method of fabricating a semiconductor structure, the method being for fabricating a semiconductor structure according to any one of claims 1 to 6, the method comprising:
providing a substrate;
and sequentially manufacturing a buffer layer, a thinning functional layer and a device layer on the substrate, wherein the etching rate of the substrate and the target etching liquid is more than or equal to 2 times that of the thinning functional layer and the target etching liquid.
8. A method for thinning a semiconductor structure, for thinning a semiconductor structure according to any one of claims 1 to 6, the method comprising:
and placing the semiconductor structure in target etching liquid until the substrate and the buffer layer are completely etched by the target etching liquid.
9. The method for thinning a semiconductor structure of claim 8, wherein prior to the step of placing the semiconductor structure in a target etchant, the method further comprises:
placing the semiconductor structure in an electrochemical etching solution, and applying voltage on a substrate and a device layer of the semiconductor structure;
and grinding the substrate to remove the substrate.
10. The method of thinning a semiconductor structure of claim 9, wherein the step of grinding the substrate comprises:
and grinding the substrate by any one of stirring, jet flow, vortex, oscillation and ultrasonic wave.
Priority Applications (1)
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