CN110223976A - A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure - Google Patents
A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure Download PDFInfo
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- CN110223976A CN110223976A CN201910442487.1A CN201910442487A CN110223976A CN 110223976 A CN110223976 A CN 110223976A CN 201910442487 A CN201910442487 A CN 201910442487A CN 110223976 A CN110223976 A CN 110223976A
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- single crystal
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- electricity single
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
Abstract
The invention discloses a kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure, comprising: ferro-electricity single crystal film layer is bonded to the interlayer dielectric layer of one layer of large scale IC wafers metal interconnecting layer the top as on the top surface of lower layer as upper layer；Overcome the problems, such as during current large scale IC wafers and ferro-electricity single crystal thin-film integration due to ferro-electricity single crystal film crushing when the factors such as the distortion of large scale IC wafers, membrane stress, wafer surface flatness cause to be bonded.In the case where not changing the IC wafers flow technological process of production as far as possible, by special process structure, realize that ferro-electricity single crystal thin-film integration, structure are simple, it is convenient and practical, it can be widely applied to the exploitation of novel semi-conductor electronic device.
Description
Technical field
The present invention relates to microelectronics technology more particularly to a kind of large scale IC wafers and ferro-electricity single crystal film
Integrated morphology.
Background technique
After decades of development, the core application integrated circuit feature size of microelectric technique is miniature with Moore's Law
Physics limit is approached, semiconductors manufacture is just becoming more and more difficult.Microelectric technique fast development how is kept to become industry each
Fang Nuli is solved the problems, such as.Currently, the micro-nano electronic device characterized by new process, new material, new construction, which is just becoming to surmount, rubs
The microelectric technique new development direction of your law.The especially appearance of three-dimensional integration technology, IC wafers by being bonded
Technique becomes bonded wafer, realizes electric signal connection by penetrating more interlayer metals interconnection of three-dimensional structure of wafer.
Ferroelectric single crystal material is due to characteristics such as ferroelectricity, piezoelectricity, photoelectricity, being widely used to SAW device, thin
The various core electron components such as membrane body acoustic resonator, photoelectric sensor.But device it is integrated, micromation trend
Under, the ferro-electricity single crystal film of high-quality and had become in conjunction with si-substrate integrated circuit industry development there is an urgent need to.But such as
What realizes large scale integrated electronic wafer and ferro-electricity single crystal thin-film integration structure to prepare as further semiconductor device
It is the technical problem of those skilled in the art's urgent need to resolve.
Summary of the invention
In view of presently, there are above-mentioned deficiency, the present invention provides a kind of large scale IC wafers and ferro-electricity single crystal film
Integrated morphology, the integrated morphology can be used as the base substrate of further semiconductor device preparation working process.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure, the integrated morphology includes: ferroelectricity list
Polycrystalline thin film layer is bonded to the interlayer dielectric layer conduct of one layer of large scale IC wafers metal interconnecting layer the top as upper layer
On the top surface of lower layer.
According to one aspect of the present invention, the size of the large scale IC wafers is 6 inches and dimensions above.
According to one aspect of the present invention, the inter-level dielectric layer material is advanced low-k materials.
According to one aspect of the present invention, the inter-level dielectric layer material is silica.
According to one aspect of the present invention, the integrated morphology further include: realize the through hole electrode of each layer electric signal connection.
According to one aspect of the present invention, the ferro-electricity single crystal thin film layer thickness is between 20 nanometers to 1 micron.
The advantages of present invention is implemented: large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration knot
Structure, comprising: ferro-electricity single crystal film layer is bonded to one layer of large scale IC wafers metal interconnecting layer the top as upper layer
Interlayer dielectric layer is as on the top surface of lower layer；During overcoming current large scale IC wafers and ferro-electricity single crystal thin-film integration
Since ferro-electricity single crystal is thin when the factors such as the distortion of large scale IC wafers, membrane stress, wafer surface flatness cause to be bonded
Film Crushing Problem.In the case where not changing the IC wafers flow technological process of production as far as possible, pass through special process
Structure realizes that ferro-electricity single crystal thin-film integration, structure are simple, convenient and practical, can be widely applied to novel semi-conductor electronic device and opens
Hair.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration structural schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure, the integrated morphology packet
Include: lower layer 101 made of being stacked as metal interconnecting layer and interlayer dielectric layer, be bonded in lower layer by ferro-electricity single crystal film layer structure
At upper layer 201.
In practical applications, the ferro-electricity single crystal is the iron such as lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, strontium bismuth tantalate
Electric material.
In practical applications, the size of the large scale IC wafers is 6 inches and dimensions above.Such as 6 inches,
8 inches, 12 inches and the size greater than 12 inches.
In practical applications, the inter-level dielectric layer material is advanced low-k materials.
In practical applications, the inter-level dielectric layer material is silica.
In practical applications, the integrated morphology further include: realize the through hole electrode of each layer electric signal connection.
In practical applications, the ferro-electricity single crystal thin film layer thickness is between 20 nanometers to 1 micron.
1) IC wafers are manufactured in the Silicon Wafer greater than 6 inches using custom integrated circuit manufacturing process.Work as technique
After process step goes to the last layer interlayer dielectric layer for completing metal interconnecting layer, stop conventional flowsheet.
2) the last layer interlayer dielectric layer makes surface planarisation, table by being greater than 6 inches of chemical-mechanical polisher polishings
Surface roughness is 15 nanometers；Then surface residual particle, and desiccation are removed using 8 inches of integrated circuit cleaning equipments, thus
To greater than 6 inches of IC wafers.
3) in ultrahigh vacuum bonder, the 6 inches of ferro-electricity single crystal stacks of thin films that are greater than of 800 nanometer thickness are placed in greater than 6
On inch IC wafers, then by both bonding operation processing step completions bonding, integrated to realize and be greater than 6 inches
Circuit wafer be greater than 6 inches of ferro-electricity single crystal thin-film integration structures.
The advantages of present invention is implemented: large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration knot
Structure, comprising: ferro-electricity single crystal film layer is bonded to one layer of large scale IC wafers metal interconnecting layer the top as upper layer
Interlayer dielectric layer is as on the top surface of lower layer；During overcoming current large scale IC wafers and ferro-electricity single crystal thin-film integration
Since ferro-electricity single crystal is thin when the factors such as the distortion of large scale IC wafers, membrane stress, wafer surface flatness cause to be bonded
Film Crushing Problem.In the case where not changing the IC wafers flow technological process of production as far as possible, pass through special process
Structure realizes that ferro-electricity single crystal thin-film integration, structure are simple, convenient and practical, can be widely applied to novel semi-conductor electronic device and opens
Hair.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those skilled in the art is in technical scope disclosed by the invention, and any changes or substitutions that can be easily thought of, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be with the scope of protection of the claims
It is quasi-.
Claims (6)
1. a kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure, which is characterized in that the integrated morphology packet
Include: ferro-electricity single crystal film layer is bonded to the interlayer of one layer of large scale IC wafers metal interconnecting layer the top as upper layer
Dielectric layer is as on the top surface of lower layer.
2. large scale IC wafers according to claim 1 and ferro-electricity single crystal thin-film integration structure, which is characterized in that
The size of the large scale IC wafers is 6 inches and dimensions above.
3. large scale IC wafers according to claim 1 and ferro-electricity single crystal thin-film integration structure, which is characterized in that
The inter-level dielectric layer material is advanced low-k materials.
4. large scale IC wafers according to claim 3 and ferro-electricity single crystal thin-film integration structure, which is characterized in that
The inter-level dielectric layer material is silica.
5. special according to claim 1 to large scale IC wafers described in one of 4 and ferro-electricity single crystal thin-film integration structure
Sign is, the integrated morphology further include: realizes the through hole electrode of each layer electric signal connection.
6. large scale IC wafers according to claim 5 and ferro-electricity single crystal thin-film integration structure, which is characterized in that
The ferro-electricity single crystal thin film layer thickness is between 20 nanometers to 1 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910442487.1A CN110223976A (en) | 2019-05-25 | 2019-05-25 | A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910442487.1A CN110223976A (en) | 2019-05-25 | 2019-05-25 | A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114650655A (en) * | 2022-05-23 | 2022-06-21 | 之江实验室 | Interconnection and heat dissipation structure of wafer prefabricated part and PCB and manufacturing method thereof |
| CN114980504A (en) * | 2022-07-27 | 2022-08-30 | 之江实验室 | High-density power supply device for wafer-level processor |
| CN115003025A (en) * | 2022-07-18 | 2022-09-02 | 之江实验室 | Detachable interconnection structure of on-chip system and PCB and manufacturing method |
| CN115050727A (en) * | 2022-08-15 | 2022-09-13 | 之江实验室 | Wafer processor and circuit self-test and power supply management device used for same |
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| US20030155598A1 (en) * | 1999-08-26 | 2003-08-21 | International Business Machines Corporation | Flip feram cell and method to form same |
| US20060090691A1 (en) * | 2004-08-10 | 2006-05-04 | Industrial Technology Research Institute | Method for manufacturing bonded wafer with ultra-thin single crystal ferroelectric film |
| CN108417574A (en) * | 2018-03-12 | 2018-08-17 | 复旦大学 | The manufacturing method of ferroelectric memory based on SOI |
| CN109786229A (en) * | 2018-12-05 | 2019-05-21 | 中北大学 | A kind of wafer bonding method and the method for corresponding foreign substrate preparation |
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- 2019-05-25 CN CN201910442487.1A patent/CN110223976A/en active Pending
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| US20030155598A1 (en) * | 1999-08-26 | 2003-08-21 | International Business Machines Corporation | Flip feram cell and method to form same |
| US20070164337A1 (en) * | 1999-08-26 | 2007-07-19 | International Business Machines Corporation | Flip feram cell and method to form same |
| US20060090691A1 (en) * | 2004-08-10 | 2006-05-04 | Industrial Technology Research Institute | Method for manufacturing bonded wafer with ultra-thin single crystal ferroelectric film |
| CN108417574A (en) * | 2018-03-12 | 2018-08-17 | 复旦大学 | The manufacturing method of ferroelectric memory based on SOI |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114650655A (en) * | 2022-05-23 | 2022-06-21 | 之江实验室 | Interconnection and heat dissipation structure of wafer prefabricated part and PCB and manufacturing method thereof |
| CN114650655B (en) * | 2022-05-23 | 2022-08-23 | 之江实验室 | Interconnection and heat dissipation structure of wafer prefabricated part and PCB and manufacturing method thereof |
| CN115003025A (en) * | 2022-07-18 | 2022-09-02 | 之江实验室 | Detachable interconnection structure of on-chip system and PCB and manufacturing method |
| CN115003025B (en) * | 2022-07-18 | 2022-11-08 | 之江实验室 | Detachable interconnection structure of on-chip system and PCB and manufacturing method |
| CN114980504A (en) * | 2022-07-27 | 2022-08-30 | 之江实验室 | High-density power supply device for wafer-level processor |
| CN114980504B (en) * | 2022-07-27 | 2022-11-08 | 之江实验室 | High-density power supply device for wafer-level processor |
| CN115050727A (en) * | 2022-08-15 | 2022-09-13 | 之江实验室 | Wafer processor and circuit self-test and power supply management device used for same |
| CN115050727B (en) * | 2022-08-15 | 2022-11-15 | 之江实验室 | Wafer processor and circuit self-test and power supply management device used for same |
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