CN110211915A - A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique - Google Patents
A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique Download PDFInfo
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- CN110211915A CN110211915A CN201910443269.XA CN201910443269A CN110211915A CN 110211915 A CN110211915 A CN 110211915A CN 201910443269 A CN201910443269 A CN 201910443269A CN 110211915 A CN110211915 A CN 110211915A
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- wafers
- large scale
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- single crystal
- electricity single
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
- H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Abstract
The invention discloses a kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique, comprising the following steps: manufactures large scale IC wafers by custom integrated circuit manufacturing process；Stop custom integrated circuit manufacturing process after completing the last layer interlayer dielectric layer of metal interconnecting layer and obtains large scale IC wafers；Large scale IC wafers are polished by chemical-mechanical polisher, make surface planarisation；Using the large scale IC wafers after the planarization of integrated circuit cleaning equipment clean the surface；The ferro-electricity single crystal film of same size is bonded on large scale IC wafers circuit surface；Ferro-electricity single crystal film after para-linkage does semiconductor technology working process；In the case where not changing the IC wafers flow technological process of production as far as possible, by reducing processing step, i.e., realization is simple with ferro-electricity single crystal thin-film integration, structure, convenient and practical, can be widely applied to Novel electronic devices exploitation.
Description
Technical field
The present invention relates to microelectronics technology more particularly to a kind of large scale IC wafers and ferro-electricity single crystal film
Integrated technique.
Background technique
After decades of development, the core application integrated circuit feature size of microelectric technique is miniature with Moore's Law
Physics limit is approached, semiconductors manufacture is just becoming more and more difficult.Microelectric technique fast development how is kept to become industry each
Fang Nuli is solved the problems, such as.Currently, the micro-nano electronic device characterized by new process, new material, new construction, which is just becoming to surmount, rubs
The microelectric technique new development direction of your law.The especially appearance of three-dimensional integration technology, IC wafers by being bonded
Technique becomes bonded wafer, realizes electric signal connection by penetrating more interlayer metals interconnection of three-dimensional structure of wafer.
Ferroelectric single crystal material is due to characteristics such as ferroelectricity, piezoelectricity, photoelectricity, being widely used to SAW device, thin
The various core electron components such as membrane body acoustic resonator, photoelectric sensor.But device it is integrated, micromation trend
Under, the ferro-electricity single crystal film of high-quality and had become in conjunction with si-substrate integrated circuit industry development there is an urgent need to.But such as
What realizes large scale integrated electronic wafer and ferro-electricity single crystal thin-film integration is the technical problem of those skilled in the art's urgent need to resolve.
Summary of the invention
In view of presently, there are above-mentioned deficiency, the present invention provides a kind of large scale IC wafers and ferro-electricity single crystal film
Integrated technique, in the case where not changing the IC wafers flow technological process of production as far as possible, by reducing technique step
Suddenly, i.e., realization is simple with ferro-electricity single crystal thin-film integration, structure, convenient and practical.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique, the integrated technique includes following step
It is rapid:
Large scale IC wafers are manufactured by custom integrated circuit manufacturing process；
Stop custom integrated circuit manufacturing process after completing the last layer interlayer dielectric layer of metal interconnecting layer to obtain greatly
Scale integrated circuits wafer；
Large scale IC wafers are polished by chemical-mechanical polisher, make surface planarisation；
Using the large scale IC wafers after the planarization of integrated circuit cleaning equipment clean the surface；
The ferro-electricity single crystal film of same size is bonded on large scale IC wafers circuit surface；
Ferro-electricity single crystal film after para-linkage does semiconductor technology working process.
According to one aspect of the present invention, the large scale IC wafers are having a size of 6 inches and dimensions above.
According to one aspect of the present invention, the ferro-electricity single crystal film thickness is between 20 nanometers to 1 micron.
According to one aspect of the present invention, the inter-level dielectric layer material is advanced low-k materials.
According to one aspect of the present invention, the inter-level dielectric layer material is silica.
According to one aspect of the present invention, the bonding carries out in case of heating.
According to one aspect of the present invention, the temperature of the heating is no more than 500 degree.
The advantages of present invention is implemented: large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration work
Skill, comprising the following steps: large scale IC wafers are manufactured by custom integrated circuit manufacturing process；It is interconnected when completing metal
Stop custom integrated circuit manufacturing process after the last layer interlayer dielectric layer of layer and obtains large scale IC wafers (101)；
Large scale IC wafers (101) are polished by chemical-mechanical polisher, make surface planarisation；It is cleaned using integrated circuit
Large scale IC wafers after the planarization of equipment clean the surface；The ferro-electricity single crystal film 201 of same size is bonded to
On large scale IC wafers circuit surface；Ferro-electricity single crystal film 201 after para-linkage does semiconductor technology working process；Gram
It takes during current large scale IC wafers and ferro-electricity single crystal thin-film integration due to large scale IC wafers distortion, thin
Ferro-electricity single crystal film crushing problem when the factors such as membrane stress, wafer surface flatness cause to be bonded.By not changing collection as far as possible
In the case where at the circuit wafer flow technological process of production, by reduce processing step, that is, realize with ferro-electricity single crystal thin-film integration,
Structure is simple, convenient and practical, can be widely applied to Novel electronic devices exploitation.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration structural schematic diagram；
Fig. 2 is large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration process schematic representation.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As depicted in figs. 1 and 2, a kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique, it is described integrated
Technique the following steps are included:
Step S1: large scale IC wafers are manufactured by custom integrated circuit manufacturing process；
In practical applications, the size of the large scale IC wafers is 6 inches and dimensions above.Such as 6 inches,
8 inches, 12 inches and the size greater than 12 inches.
Step S2: stop custom integrated circuit manufacturing process after completing the last layer interlayer dielectric layer of metal interconnecting layer
It obtains large scale IC wafers (101)；
In practical applications, the inter-level dielectric layer material is advanced low-k materials.
In practical applications, the inter-level dielectric layer material is silica.
Step S3: large scale IC wafers (101) are polished by chemical-mechanical polisher, make surface planarisation；
Step S4: using the large scale IC wafers after the planarization of integrated circuit cleaning equipment clean the surface；
Step S5: the ferro-electricity single crystal film (201) of same size is bonded to large scale IC wafers circuit table
On face；
In practical applications, the ferro-electricity single crystal is the iron such as lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, strontium bismuth tantalate
Electric material.In practical applications, the ferro-electricity single crystal thin film layer thickness is between 20 nanometers to 1 micron.
In practical applications, the bonding can be in ultrahigh vacuum bonding, vacuum environment surface-activated bond, atmospheric environment
The bonding techniques such as room-temperature bonding, fluorine-containing plasma-activated room-temperature bonding technology.The bonding technology temperature is not higher than 500
Degree.
Step S6: the ferro-electricity single crystal film (201) after para-linkage does semiconductor technology working process.
In practical applications, the semiconductor technology includes photoetching, etching, metallization, passivation layer growth, aluminium Pad production
Etc. processing steps.
In practical applications, for 8 inches:
1) IC wafers are manufactured in 8 inches of Silicon Wafers using custom integrated circuit manufacturing process, when process flow walks
Suddenly after going to the last layer interlayer dielectric layer for completing metal interconnecting layer, stop conventional flowsheet.
2) the last layer interlayer dielectric layer makes surface planarisation, surface is thick by 8 inches of chemical-mechanical polisher polishings
Rugosity is 15 nanometers；Then surface residual particle, and desiccation are removed using 8 inches of integrated circuit cleaning equipments, to obtain 8 English
Very little IC wafers.
3) in ultrahigh vacuum bonder, 8 inches of ferro-electricity single crystal stacks of thin films of 800 nanometer thickness are placed in 8 inches and integrate
On circuit wafer, the two bonding is then completed by bonding operation processing step, as shown in Figure 2.
4) custom integrated circuit manufacturing process is used: making devices structure, production through-hole connection on ferro-electricity single crystal film
Top layer metallic layer, interlayer metal to 8 inches of IC wafers interconnect realization electric signal connection, to realize that 8 inches integrate
Circuit wafer and 8 inches of ferro-electricity single crystal thin-film techniques are integrated.
The advantages of present invention is implemented: large scale IC wafers of the present invention and ferro-electricity single crystal thin-film integration work
Skill, comprising the following steps: large scale IC wafers are manufactured by custom integrated circuit manufacturing process；It is interconnected when completing metal
Stop custom integrated circuit manufacturing process after the last layer interlayer dielectric layer of layer and obtains large scale IC wafers (101)；
Large scale IC wafers (101) are polished by chemical-mechanical polisher, make surface planarisation；It is cleaned using integrated circuit
Large scale IC wafers after the planarization of equipment clean the surface；The ferro-electricity single crystal film 201 of same size is bonded to
On large scale IC wafers circuit surface；Ferro-electricity single crystal film 201 after para-linkage does semiconductor technology working process；Gram
It takes during current large scale IC wafers and ferro-electricity single crystal thin-film integration due to large scale IC wafers distortion, thin
Ferro-electricity single crystal film crushing problem when the factors such as membrane stress, wafer surface flatness cause to be bonded.By not changing collection as far as possible
In the case where at the circuit wafer flow technological process of production, by reduce processing step, that is, realize with ferro-electricity single crystal thin-film integration,
Structure is simple, convenient and practical, can be widely applied to Novel electronic devices exploitation.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those skilled in the art is in technical scope disclosed by the invention, and any changes or substitutions that can be easily thought of, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be with the scope of protection of the claims
It is quasi-.
Claims (7)
1. a kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique, which is characterized in that the integrated technique packet
Include following steps:
Large scale IC wafers are manufactured by custom integrated circuit manufacturing process；
Stop custom integrated circuit manufacturing process after completing the last layer interlayer dielectric layer of metal interconnecting layer and obtains large scale
IC wafers (101)；
Large scale IC wafers (101) are polished by chemical-mechanical polisher, make surface planarisation；
Using the large scale IC wafers after the planarization of integrated circuit cleaning equipment clean the surface；
The ferro-electricity single crystal film (201) of same size is bonded on large scale IC wafers circuit surface；
Ferro-electricity single crystal film (201) after para-linkage does semiconductor technology working process.
2. large scale IC wafers according to claim 1 and ferro-electricity single crystal thin-film integration technique, which is characterized in that
The large scale IC wafers (101) are having a size of 6 inches and dimensions above.
3. large scale IC wafers according to claim 1 and ferro-electricity single crystal thin-film integration technique, which is characterized in that
Ferro-electricity single crystal film (201) thickness is between 20 nanometers to 1 micron.
4. large scale IC wafers according to claim 1 and ferro-electricity single crystal thin-film integration technique, which is characterized in that
The inter-level dielectric layer material is advanced low-k materials.
5. large scale IC wafers according to claim 4 and ferro-electricity single crystal thin-film integration technique, which is characterized in that
The inter-level dielectric layer material is silica.
6. large scale IC wafers according to one of claims 1 to 5 and ferro-electricity single crystal thin-film integration technique, special
Sign is that the bonding carries out in case of heating.
7. large scale IC wafers according to claim 6 and ferro-electricity single crystal thin-film integration technique, which is characterized in that
The temperature of the heating is no more than 500 degree.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910443269.XA CN110211915A (en) | 2019-05-25 | 2019-05-25 | A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique |
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| CN201910443269.XA CN110211915A (en) | 2019-05-25 | 2019-05-25 | A kind of large scale IC wafers and ferro-electricity single crystal thin-film integration technique |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060090691A1 (en) * | 2004-08-10 | 2006-05-04 | Industrial Technology Research Institute | Method for manufacturing bonded wafer with ultra-thin single crystal ferroelectric film |
| US20080258194A1 (en) * | 1999-08-26 | 2008-10-23 | International Business Machines Corporation | Flip feram cell and method to form same |
| CN108417574A (en) * | 2018-03-12 | 2018-08-17 | 复旦大学 | The manufacturing method of ferroelectric memory based on SOI |
-
2019
- 2019-05-25 CN CN201910443269.XA patent/CN110211915A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080258194A1 (en) * | 1999-08-26 | 2008-10-23 | International Business Machines Corporation | Flip feram cell and method to form same |
| US20060090691A1 (en) * | 2004-08-10 | 2006-05-04 | Industrial Technology Research Institute | Method for manufacturing bonded wafer with ultra-thin single crystal ferroelectric film |
| CN108417574A (en) * | 2018-03-12 | 2018-08-17 | 复旦大学 | The manufacturing method of ferroelectric memory based on SOI |
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Application publication date: 20190906 |