WO2005074048A1

WO2005074048A1 - Free-standing semiconductor substrate and the manufacturing method and manufacturing apparatus thereof

Info

Publication number: WO2005074048A1
Application number: PCT/KR2004/002753
Authority: WO
Inventors: Seong-Jin Kim; Soon-Jae Yu
Original assignee: Itswell Co. Ltd.
Priority date: 2004-01-31
Filing date: 2004-10-29
Publication date: 2005-08-11

Abstract

The invention provides a free-standing semiconductor wafer and its fabrication method. In the free-standing semiconductor wafer, at least one compound semiconductor layer is grown on a base substrate and then exists by itself since the base substrate is removed via backside-polishing, wet etching or dry etching from the semiconductor layer.

Description

FREE-STANDING SEMICONDUCTOR SUBSTRATE AND THE MANUFACTURING METHOD AND MANUFACTURING APPARATUS THEREOF

Technical Field The present invention relates to a semiconductor wafer and its fabrication method and apparatus. More particularly, the invention is de ised to remove a sapphire substrate, which is used as a base for the growth of nitride-based semiconductor, in order to provide a free-standing semiconductor wafer (hereinafter will be also referred to as semiconductor wafer or substrate) . By using the free-standing semiconductor wafer from which the sapphire substrate is removed, the invention can grow nitride-based semiconductor layers on the semiconductor wafer of the same lattice constant and thus can easily fabricate a vertical electrode nitride-based semiconductor device which has excellent film qualities of little crystal defect and excellent performance.

Background Art Substrates used for the growth of semiconductor are determined according to film types to be grown thereon. Any lattice constant difference between a substrate and a semiconductor layer grown thereon may bring in crystal defect thereby worsening qualities of the semiconductor film. In order to overcome such a problem, it is well known to mainly grow an AlGaP or GaP/AlP heterojunction structure on a GaP substrate, an InP film on an InP substrate, and GaAs, GaAlAs and InGaP films on InGaAs and GaAs substrates. In particular, a GaN (nitride-based-based) semiconductor is mainly grown on a sapphire substrate to obtain a high quality semiconductor films although GaN and sapphire have a dissimilar lattice constant. However, unlike GaP, InP, Si and GaAs semiconductor substrates, it is impossible to produce a conductive substrate from sapphire through doping. This causes difficulties to fabrication of vertical electrode optoelectronic devices such as Light Emitting Diodes (LEDs) , vertical electrode laser diodes and high-frequency RF devices, and thus both of first and second electrodes are to be formed (i.e., as lateral electrodes) on the same side on which epitaxial layers are grown. If both electrodes are formed on the same side like this, wire-bonding areas for the both electrodes are to be ensured on the same side and thus an LED should have at least a specific chip size. This restricts improvement in chip yield per wafer. In addition, an insulator used as a substrate can hardly discharge static electricity, if any induced from the outside, potentially causing damages owing to static electricity. This degrades device reliability and requires an incorporation of a Zener diode, thereby bringing restrictions to packaging processes. In addition, since sapphire is a poor heat conductor, heat generated in the LED is not easily radiated to the outside. This restricts high current operation necessary for high light-output power generation. In addition, an oscillation facet of excellent reflectivity is essential for fabrication of laser diodes in order to obtain laser optical gains . Since it is difficult to treat sapphire or form cleaving areas therein owing to its hardness, laser diodes of excellent performance can be hardly fabricated from sapphire. Even though the commercial merits of sapphire substrates have been known, they are not widely used in the fabrication of laser diodes owing to its high fabrication cost. In particular, highly valuable electronic devices such as Hetero Bipolar Transistor (HBT) adopting a vertical electrode can be hardly made from sapphire owing to its poor workability. Although these problems can be overcome when nitride-based semiconductor is grown on a nitride-based semiconductor wafer or substrate of fine workability, fabrication of nitride-based semiconductor wafers is not an easy task at all. There is a conventional approach to separate a sapphire substrate from nitride-based-based films via laser lift-off (LLO) in order to produce a nitride-based semiconductor wafer. However, such LLO requires a complicated process and high cost owing to expensive equipments mounted with a high power excimer laser. This approach also shows poor productivity and causes some problems in which for example semiconductor wafer surface is damaged by heat during LLO process. Disclosure of the Invention Technical Object The present invention has been made to solve the foregoing problems of the prior art and it is therefore an object of the present invention to provide a free-standing semiconductor wafer, in which a base substrate is removed from the nitride-based-based semiconductor film so that vertical electrode semiconductor devices of little crystal defect and excellent performance can be produced therefrom, and a fabrication method thereof. It is another object of the invention to provide a fabrication method of semiconductor wafers capable of more easily removing base substrates from nitride-based-based semiconductor films . It is further another object of the invention to provide a fabrication method and an apparatus of semiconductor wafers which can be more easily performed as well as improving productivity.

Technical Solution In order to realize the above objects, the present invention provides a semiconductor wafer comprising a nitride-based-based semiconductor layer grown on a base substrate, wherein the nitride-based semiconductor layer is separated from the sapphire substrate . According to an aspect of the invention, there is provided a semiconductor wafer comprising a nitride-based-based semiconductor layer grown on a sapphire (Al₂0₃) substrate, wherein at least a part of the sapphire substrate is separated from the nitride-based-based semiconductor layers. It is preferred that the sapphire substrate is separated from the nitride-based-based semiconductor layer via etching, and the sapphire substrate has a thickness of about 50 to 800 m. In this case, the sapphire substrate has a crystal growth plane selected from C, M, A and R planes, and preferably, the sapphire substrate is patterned in x or y direction. It is preferred that the semiconductor layer comprises at least one nitride-based-based semiconductor layer of In_x (Ga_yAlι__y) N, in which l≥x≥O, l≥y≥O and x+y>0. In this case, the semiconductor layer has a thickness of about 10 to bO Oμ . Preferably, the semiconductor layer is grown via at least one selected from a group consisting of Vapor Phase Epitaxy (VPE) , Hydride Vapor Phase Epitaxy (HVPE) , Metal Organic Vapor Phase Epitaxy (MOVPE) , Metal Organic Chemical Vapor Deposition (MOCVD) , Molecular Beam Epitaxy (MBE) , Low Pressure Chemical Vapor Deposition (LPCVD) , Liquid Phase Epitaxy (LPE) and combinations thereof. In this case, the semiconductor layer may be one selected from a group consisting of high resistance semiconductor, p-type semiconductor and n-type semiconductor. Preferably, the high resistance semiconductor has a doping concentration of 10E17Ω/cm³ or less, and the p- and n-type semiconductor layers have a doping concentration of 10El8/cm³ or more and a resistivity of 10E-2Ωcm or less . The semiconductor wafer may further comprise an etch stop layer grown between the sapphire substrate and the nitride-based semiconductor layer, the etch stop layer adapted to stop etching proceeding from the sapphire substrate. In this case, the etch stop layer comprises a nitride-based-based semiconductor layer.

According to another aspect of the invention, there is provided a fabrication method of semiconductor wafers, comprising steps of: (a) preparing a substrate of sapphire (A1₂0₃) ; (b) forming a semiconductor layer on the substrate; (c) forming a protective layer on the semiconductor layer; (d) lapping and polishing the substrate and etching the substrate to remove the substrate from the semiconductor layer via; and (e) removing the protective layer via etching. Preferably, the etching in the (d) step is performed with an etching solution containing at least one selected from a group consisting of HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, KOH, KHS0₄, Aluetch(4H₃P0+4CH₃COOH+HN0₃+H₂0) and mixtures thereof. More preferably, the semiconductor layer is adapted to act as an etch stop layer in wet etching. In this case, the semiconductor layer comprises at least one selected from a group consisting of an In_x (Ga_yAlι-_y) N layer (l≥x≥O, l≥y≥O and x+y>0), a silicon oxide cluster such as Si0₂ and a silicon nitride-based cluster such as SiN_x. It is preferred that the etching in the (d) step is performed with the etching solution heated to a temperature of at least 100^°C . More preferably, the etching solution is heated indirectly via optical absorption. Preferably, the etching in the (d) step may further comprise dry etching of ICP/RIE or RIE. In this case, the dry etching utilizes preferably at least one etching gas selected from a group consisting of BC1₃, Cl₂, HBr and Ar. Preferably, the lapping and polishing in the (d) step mirror polishes the sapphire substrate to have a surface roughness of 20 μm or less. The lapping and polishing in the (d) step preferably makes the sapphire substrate to a thickness of 300μm or less. Also, the lapping and polishing in the (d) step is preferably performed via at least one of mechanical polishing, Chemical Mechanical Polishing (CMP) and wet etching, wherein the wet etching uses an etching solution containing at least one selected from a group consisting of HCl, HNO₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, Aluetch (4H₃P0₄+4CH₃COOH+HNθ₃+H2θ) and mixtures thereof. In addition, the protective layer is preferably made of Si0₂ or Spin-On Glass (SOG) .

According to further another aspect of the invention, there is provided a fabrication method of semiconductor wafers, comprising steps of: (a) preparing a substrate of sapphire (A1₂0₃) ; (b) forming an etch stop layer on the substrate; (c) forming a semiconductor layer on the etch stop layer; (d) forming a protective layer on the semiconductor layer; (e) lapping and polishing the substrate and etching the substrate to remove the substrate from the semiconductor layer; and (f) removing the protective layer. The fabrication method may further comprise a step off attaching an auxiliary substrate on the protective layer after the (d) step, and wherein the auxiliary substrate is separated from the semiconductor layer by the (g) step of removing the protective layer via etching. Preferably, the auxiliary substrate comprises an insulating substrate or a semiconductor substrate. Preferably, the auxiliary substrate is attached via adhesive means made of eutectic metal. In this case, the eutectic metal preferably comprises at least one selected from a group consisting of In, Ni, Pd, Au, Ti, Pt, Rh and combinations thereof. Preferably, the etch stop layer and the semiconductor layer comprise one selected from a group consisting of an In_x (Ga_yA?Lι-_y) N layer (l≥x≥O, l≥y≥O and x+y>0) , a silicon oxide cluster and a silicon nitride-based cluster of Si0₂ or SiN_x. Also, the etching in the (e) step is preferably performed with an etching solution containing at least one selected from a group consisting of HCl, HN0₃, KOH, NaOH,^" H₂S0₄, H₃P0₄, Cr0₃, Aluetch (4H₃Pθ₄+4CH₃COOH+HN0₃+H₂θ) and mixtures thereof. In this case, the etching in the (e) step may be performed with the etching solution heated to a temperature of at least 100 ^°C. Preferably, the etching solution is heated indirectly via optical absorption. Also, the etching in the (e) step may further comprise dry etching which utilizes at least one etching gas selected from a group consisting of BC1₃, Cl₂, HBr and Ar. Preferably, the lapping and polishing in the (e) step mirror polishes the sapphire substrate to have a surface roughness of 20 IM or less. It is preferred that the lapping and polishing in the (d) step makes the sapphire substrate to a thickness of 300 ιn or less. The protective layer may be etched via HF or Buffer Oxide Etchant (BOE) . Preferably, the protective layer is made of Si0₂ or Spin-On Glass (SOG) .

According to yet another aspect of the invention, there is provided an apparatus for fabricating free-standing semiconductor wafers, comprising: a loader for loading semiconductor wafers each having a sapphire substrate and a nitride-based-based semiconductor layer grown on the sapphire substrate, wherein the sapphire substrates are lapped and polished to a substantially uniform thickness, and heating the semiconductor wafers to a predetermined temperature; a solution heater for pre-heating an etching solution for etching the sapphire substrates of the semiconductor wafers; a carrier arm having its top portion connected to a rail for enabling horizontal movement and designed vertically adjustable in length to elevate the semiconductor wafers from the wafer loader; an etch bath for etching the sapphire substrates of the semiconductor wafers carried by the carrier arm; a cleaning and drying unit for cleaning and drying the semiconductor wafers which are etched in the etch bath so that the sapphire substrates are removed therefrom; and an unloader for unloading the cleaned and dried semiconductor wafers from the carrier arm. Preferably, the sapphire substrates of the semiconductor wafers loaded on the loader have a thickness within an error range of ±10 IM. Also, the etch bath preferably uses an etching solution containing at least one selected from a group consisting of H₂S0₄, H₃PO4 and combinations thereof. More preferably, H₂S0₄ has a fraction of 5 to 95% when mixed with H₃PO₄, and the etching solution is maintained at least 100 °C . In this case, the etch bath may have hot wires for directly applying heat to the etching solution within the etch bath to maintain the temperature of the etching solution or indirect heating may be performed by radiating light to the etching solution within the etch bath to maintain the temperature of the etching solution. In addition, the etch bath preferably comprises: a cooling pipe arranged around the etch bath to adjust the temperature of the etching solution; a cover adapted to open/close the etch bath so that vapor generated from the etching solution does not leak to the outside; a drain pipe connected to the etch bath to drain vapor generated from the etching solution; a liquidizing pipe arranged around the drain pipe to cool and liquidize vapor drained through the drain pipe; and a controller for automatically controlling the cooling pipe, the drain pipe and the liquidizing pipe. Preferably, the etch bath is made of one selected from a group consisting of high temperature Te lon, SUS, glass and quartz.

Brief Description of the Drawings FIG. 1 illustrates a nitride-based-based semiconductor structure including a sapphire substrate and a nitride-based-based semiconductor layer grown on the sapphire substrate via HVPE; FIG. 2 illustrates a nitride-based-based semiconductor structure including a sapphire substrate, a first nitride-based-based semiconductor layer grown on the sapphire substrate via HVPE and a second nitride-based semiconductor layer re-grown on the first nitride-based semiconductor layer via MOCVD; FIG. 3 illustrates a nitride-based semiconductor structure including a patterned sapphire substrate, a first nitride-based semiconductor layer grown on the sapphire substrate via HVPE and a second nitride-based semiconductor layer regrown on the first nitride-based semiconductor layer via MOCVD; FIG. 4 illustrates a nitride-based semiconductor structure including a sapphire substrate, a fine cluster of Si0₂ or SiN_x formed on the sapphire substrate, a first nitride-based semiconductor layer grown via HVPE on the sapphire substrate and a second nitride-based semiconductor layer regrown on the first nitride-based semiconductor layer via MOCVD; FIG. 5 illustrates a nitride-based semiconductor structure including a sapphire substrate, a first nitride-based semiconductor layer grown on the sapphire substrate via MOCVD, a second nitride-based semiconductor layer grown on the first nitride-based semiconductor layer via HVPE and a third semiconductor layer regrown on the second nitride-based semiconductor layer via MOCVD; FIG. 6 illustrates a nitride-based semiconductor structure including a patterned sapphire substrate, a first nitride-based semiconductor layer grown on the patterned sapphire substrate via MOCVD, a second nitride-based semiconductor layer grown on the first nitride-based semiconductor layer via HVPE and a third semiconductor layer regrown on the second nitride-based semiconductor layer via MOCVD; FIG.7 illustrates a fabrication process of semiconductor wafers according to a first embodiment of the invention; FIG. 8 is a graph comparing the etching rate of sapphire and GaN by ICP/RIE dry etch. FIG. 9 is a graph comparing the etching rate of sapphire and GaN when etched with a mixed solution of H₂S0₄ and H₃PO₄. FIG. 10 is graph comparing the etching rate according to temperature variation when sapphire and GaN are wet etched by a mixed solution of H₂S0₄ and H₃PO₄. FIG. 11 is a photograph illustrating a cross section of a sapphire substrate in which grooves of different line width are formed via wet etching according to an embodiment of the invention; FIG. 12 is a graph illustrating etched depths by wet etching according to patterned line widths and aspect ratios between the patterned line widths and the etched depths; FIG. 13 is a photograph illustrating the surface of a nitride-based semiconductor layer when a sapphire substrate is removed via wet etching; FIG. 14 illustrates a fabrication process of semiconductor wafers according to a third embodiment of the invention; FIG. 15 illustrates a fabrication process of semiconductor wafers according to a fourth embodiment of the invention; FIG. 16 illustrates process steps of a free-standing nitride-based semiconductor wafer; FIG. 17 is a photograph illustrating an etched surface after a sapphire substrate is etched according to a specific pattern via wet etching; FIG. 18 illustrates an apparatus for fabricating free-standing semiconductor wafers according to the invention; FIG. 19 illustrates a wet etch bath in detail; FIG. 20 illustrates direct heating in a wet etch bath; and FIG. 21 illustrates indirect heating in a wet etch bath.

Best Mode for Carrying out the Invention Semiconductor Layer Formation FIG. 1 illustrates a nitride-based semiconductor structure including a sapphire substrate (A1₃0₃) having a thickness of 430/tm and an In_x (Ga_yAlι__y) N nitride-based semiconductor layer grown at a thickness of 200 m on the sapphire substrate via Hydride Vapor Phase Epitaxy (HVPE) . The nitride-based semiconductor layers have a composition of l≥x≥O and l≥y≥O. The nitride-based semiconductor layer 12 may be grown via Metal Organic Chemical Vapor Deposition (MOCVD) , Liquid Phase Epitaxy (LPE) , Molecular Beam Epitaxy (MBE) and Metal Organic Vapor Phase Epitaxy (MOVPE) . The grown nitride-based semiconductor layer is preferably thick so that it can be readily treated in following procedures in which nitride-based semiconductor layers are regrown and a device is fabricated. In addition, if the sapphire substrate 11 is extremely thin, the sapphire substrate 11 on which nitride-based semiconductor is grown may be bent under the stress caused by the lattice difference between sapphire and nitride-based semiconductor or the sapphire substrate 11 may break while nitride-based semiconductor is grown thereon. So, the sapphire substrate 11 preferably has a thickness of about 10 to 500ΛH. Although HVPE (Hydride Vapor Phase Epitaxy) produces poorer nitride-based semiconductor compared to those grown via Metal Organic Chemical Vapor Deposition (MOCVD) , it can grow semiconductor layers at a high rate of lOO m/hr, which is adequate for mass production and can save manufacturing cost. So, HVPE can preferably grow a thick nitride-based semiconductor layer which is to act as a free-standing semiconductor wafer or substrate when a sapphire substrate is removed therefrom. Therefore, nitride-based semiconductor is grown via HVPE at a temperature of about 900 ^°C using ammonia (NH ) , trimethyl Gallium and trimethyl aluminum. The nitride-based semiconductor can be grown into single or multiple layers according to device types to be fabricated. In addition, at least one of Si, Mg, Sn and Zn is doped into the nitride-based semiconductor to impart conductivity thereto. Si dopant can produce an n-nitride-based semiconductor layer 12, and Mg dopant can produce a p-nitride-based semiconductor layer 12. Herein, Si is doped to grow the n-nitride-based semiconductor layer 12 to a thickness of about 200[M in view of easiness in the growth of nitride-based semiconductor. FIG. 2 illustrates a nitride-based semiconductor structure including a sapphire substrate 11 having a thickness of 500 tm, a first In_x (Ga_yAli__y) N nitride-based semiconductor layer 12 grown at a thickness of 200M on the sapphire substrate 11 via HPVE and a second In_x (Ga_yAlι__y) N nitride-based semiconductor layer 13 regrown on the first semiconductor layer 12 via MOCVD. The nitride-based semiconductor layers have a composition of l≥x≥O and l≥y≥O. As described above, the nitride-based semiconductor can be grown via HVPE in single or multiple layers according to device types to be fabricated. In addition, at least one of Si, Mg, Sn and Zn may be doped to produce n- or p-type nitride-based semiconductor layer having conductivity. Doping density is varied according to device types to be fabricated, and its range may be from 10E15/C1³ to 10E21/cu. In addition the nitride-based semiconductor can be regrown on the first layer, which is previously grown via HVPE, in single or multiple layers according to device types to be fabricated. For the purpose of fabricating an LED, an n-type nitride-based semiconductor layer of 2 to 5 m thickness, an n-cladding layer of 0.5 m thickness, an active layer of 0.5 m thickness, a p-cladding layer of O . δμ . and a p-type nitride-based semiconductor layer of 0.2 m thickness are grown. An active layer adopts a multi quantum well structure of In_x (Ga_yAli-_y) N/In_x (Ga_yAlι__y) N even though it may be varied more or less according to the wavelength of light. The composition of In_x (Ga_yAlι-_y) N is so determined that a quantum well layer has an energy band gap smaller than that of a barrier layer. In this case, the quantum well structure may be grown in the form of Ino.₁Gao.₉N/GaN or Ino.₁Gao.₉N/Alo.₁Gao.₉N. FIG. 3 illustrates a nitride-based semiconductor structure including a patterned sapphire substrate 11, a first nitride-based semiconductor layer of In_x (Ga_yAlι__y) N grown on the patterned sapphire substrate 11 via HVPE and a second nitride-based semiconductor layer of In_x (Ga_yAlι-_y) N re-grown on the first nitride-based semiconductor layer via MOCVD. The nitride-based semiconductor layers have a composition of x≥O, y≥O. The nitride-based semiconductor layers have a structure similar to that shown in FIG. 2 except that the patterned sapphire substrate 11 is used to grow the nitride-based semiconductor layers. Such a patterned sapphire substrate can minimize the strain between the sapphire substrate and a nitride-based semiconductor layer grown thereof advantageously minimizing crystal defect. While nitride-based semiconductor grown on a semiconductor wafer without patterns has a crystal defect density of about lOElO/cu, the crystal defect density of nitride-based semiconductor grown on the patterned substrate can be reduced to 10E8/αrf. FIG. 4 illustrates a nitride-based semiconductor structure including a sapphire substrate having a thickness of 10A, small size clusters grown on the sapphire substrate and In_x (Ga_yAl__y) N nitride-based semiconductor layers formed on the small size (fine) cluster. The cluster is formed from any of Siθ₂ and SiN_x groups or their combination, the first nitride-based semiconductor layer is grown at a thickness of lOO m on the fine cluster via HVPE, and the second nitride-based semiconductor layer is regrown at a thickness of 5/m on the first nitride-based semiconductor layer via MOCVD. Other detailed features are similar to the before-described structures except that a SiN or SiO fine cluster is formed before the growth of nitride-based semiconductor layers via HVPE. The SiN_x or Si0₂ fine cluster is adapted to minimize the strain between the sapphire substrate and the overlying nitride-based semiconductor layer, and thus can be used as a wet etch stop layer when the sapphire substrate is to be removed via wet etching as will be described later. When the SiN_x or Si0₂ fine cluster is formed covering the sapphire substrate, its wafer coverage is necessarily remained at 90% or less. If the SiN_x or Si0₂ fine cluster completely covers the sapphire substrate without exposing any partial area thereof, nitride-based cannot be grown on the sapphire substrate. FIG. 5 illustrates a nitride-based semiconductor structure including a sapphire substrate, a first nitride-based semiconductor layer of In_x (GayAlx-y) N grown at a thickness of 2pm on the sapphire substrate via MOCVD, a second semiconductor layer of In_x (Ga_yAlι__y) N grown at a thickness of 200 m on the first nitride-based semiconductor layer via HVPE and a third nitride-based semiconductor layer of In_x (Ga_yAli-_y) N grown at a thickness of 5an on the second nitride-based semiconductor layer via MOCVD. The nitride-based semiconductor layers have a compositions of x≥O and y≥O. The first nitride-based semiconductor layer is grown on the sapphire substrate via MOCVD since a nitride-based semiconductor layer grown on the sapphire substrate via HVPE cannot remove or reduce threading crystal dislocations even though it is formed thick. For the purpose of coping with this problem, the first nitride-based semiconductor layer is grown on the sapphire substrate via MOCVD to minimize crystal defects so as to reduce threading crystal dislocations that occur in the growth of nitride-based semiconductor via HVPE. Also in this structure, as described above, the nitride-based semiconductor layer formed via HVPE can be grown in single or multiple layers according to device types to be fabricated. In addition, at least one dopant of Si, Mg, Sn and Zn can be doped into the nitride-based semiconductor layers giving conductivity thereto. In this way, n-type or p-type doped nitride-based semiconductor layers can be formed. FIG. 6 illustrates a nitride-based semiconductor structure including a patterned sapphire substrate, a first nitride-based semiconductor layer of undoped In_x (Ga_yAlι__y) N grown at a thickness of 2 m on the patterned sapphire substrate via MOCVD, a second nitride-based semiconductor layer of In_x (Ga_yAlι__y) N grown at a thickness of 100/ on the first nitride-based semiconductor layer via HVPE and a third semiconductor layer of In_x (Ga_yAlι-_y) N grown on the second nitride-based semiconductor layer via MOCVD. Also in this structure, the nitride-based semiconductor layers have a compositions of x≥O and y≥O. The first nitride-based semiconductor layer is grown on the patterned sapphire substrate via MOCVD since a nitride-based semiconductor layer grown on the sapphire substrate via HVPE cannot remove or reduce threading crystal dislocations even though it is formed thick. In addition, when the first nitride-based semiconductor layer is grown on the patterned sapphire substrate, the patterned sapphire substrate minimizes the strain between the sapphire substrate and the first nitride-based semiconductor layer thereby minimizing crystal defects, so that the first nitride-based semiconductor layer can have better quality. Its detailed features and fabrication method are similar to those in FIG. 4 except that the first nitride-based semiconductor layer is grown on the patterned sapphire substrate. When grown in this method, the first nitride-based semiconductor layer grown via HVPE shows fine quality and thus threading crystal dislocations are reduced. This method is adopted to reduce crystal defects in the second nitride-based semiconductor layer grown via HVPE and thus to improve the quality of the third nitride-based semiconductor layer regrown via MOCVD, which is a final layer of a resultant device, thereby improving the performance of the resultant device. In addition, the third nitride-based semiconductor layer is adapted to act as an etch stop layer when the sapphire substrate is removed via wet etching as will be described later.

First Embodiment FIG. 7 illustrates intermediate steps in a fabrication method of a semiconductor wafer according to a first embodiment of the invention, in which a sapphire substrate is removed via etching. In the method as shown in FIG. 7, a nitride-based semiconductor structure as shown in FIG.4 is grown on a sapphire substrate 11 having a thickness of 450 m, and then the sapphire substrate 11 is removed so as to fabricate a free-standing semiconductor wafer. In FIG. 7, a first nitride-based semiconductor layer 12 of In_x(Ga_yAli-_y)N is grown at a thickness of 200jMn on the sapphire substrate via HVPE, a second nitride-based semiconductor layer of In_x (Ga_yAlι-_y) N 13 is grown at a thickness of 5 m on the first nitride-based semiconductor layer 12 via MOCVD, and then a hard mask or protection layer of Si0₂ is deposited at a thickness of Iμm on the second nitride-based semiconductor layer 13 to protect the nitride-based semiconductor layers 12 and 13 from damage. The nitride-based semiconductor layers 12 and 13 formed on the sapphire substrate 11 may be of single or multiple layers grown via MOCVD, LPE, MBE, HVPE or MOVPE. Also, the second nitride-based semiconductor layer 13 may be of single or multiple semiconductor layers regrown via MOCVD on a nitride-based semiconductor layer grown via MOCVD, LPE, MBE or VPE. The layer structure is not particularly influential in this process for the free-standing semiconductor wafer. In view of following processes for a nitride-based semiconductor structure and a device, it is advantageous to make the nitride-based semiconductor layers 12 and 13 have a large thickness. However, the thickness is limited owing to the strain between the sapphire base substrate and the nitride-based semiconductor layers. Therefore, the total thickness of semiconductor layers 12 and 13 is determined preferably in a range from 10 to 500 tm. Then, a hard mask or protection layer 15 of for example Spin-On Glass (SOG) or Si0₂ is deposited at a thickness of ljMii on the semiconductor layers to protect the surface thereof, the sapphire substrate 11 is lapped and polished up to a thickness of 30 to 50 IM, and the lapped side is mirror polished into a smooth surface having a roughness of 20 [M or less. The sapphire substrate 11 may be lapped via Chemical Mechanical Polishing (CMP) , ICP/RIE or RIE dry etching or mechanical lapping with alumina (A1₂0₃) powder. Alternatively, the lapping may be performed via wet etching using an etching solution containing HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, H₂0, KOH, KHS0₄, Aluetch(4H₃P0₄+4CH₃COOH+HN0₃+H₂0) or combinations thereof. The ICP/RIE or RIE dry etching uses an etching gas selected from BC1₃, Cl₂, HBr, Ar and combinations thereof. In this case, it is more desirable for the sapphire substrate 11 to have a smaller thickness. However, since extremely small thickness may cause bending to the sapphire substrate 11 or worsen its workability, the sapphire substrate 11 preferably has a thickness of about 10 to 300/tm . It is also preferred that the mirror-polished sapphire substrate 11 has a surface roughness of 20 m or less. Otherwise, the surface roughness of the sapphire substrate 11 may be transferred to the nitride-based semiconductor layers thereby damaging a resultant nitride-based semiconductor structure. The wet etching of the sapphire substrate 11 is carried out as follows: The etch rate of the sapphire substrate 11 by a mixed etching solution of H₂S0₄ and H₃PO₄ of 320 ^°C is measured, and then the sapphire substrate 11 is immersed into the etching solution for a specific time period estimated to etch a sapphire substrate having a thickness added for 5j«m to the thickness of the sapphire substrate 11. By the etching solution used herein, nitride-based semiconductor shows an etch rate that is 1/10 or less compared to that of the sapphire substrate 11. That is, the nitride-based semiconductor layers 12 and 13 have an etch selectivity of 10 or more with respect to the sapphire substrate 11. Therefore, although the etching is performed for a time period that is sufficient to completely etch the sapphire substrate 11, there is no risk of damaging the nitride-based semiconductor layers 12 and 13 since they are etched slowly enough. In addition, the temperature of the etching solution is preferably maintained at a temperature of 100°C or more in order to shorten process time. Heating for maintaining the etching solution at 100°C or more can be performed directly or indirectly. In the direct heating, the etching solution is placed on a heater or directly contacted by the heater. In the indirect heating, optical absorption is adopted to heat the etching solution. The sapphire substrate 11 can be etched via ICP/RIE. ICP and RIE power may be raised as high as possible to etch the sapphire substrate 11 at a higher rate, whereas attention should be given since high temperature may damage an epitaxial layer. FIG. 8 is a graph comparing the etch rate of sapphire with that of GaN by ICP/RIE dry etch. As shown in FIG. 8, the etch rates of sapphire and GaN semiconductor increase in proportion to ICP and RIE power, but the etch selectivity of sapphire with respect to GaN semiconductor (A1₂0₃ etch rate/GaN etch rate) decreases. Regarding this result, when the sapphire substrate 11 is etched via dry etch of ICP/RIE, the etching is rarely stopped at the nitride-based semiconductor layer 12 of GaN semiconductor. So, an approach such as optical analysis and residual gas analysis has to be applied in order to stop etching at the nitride-based semiconductor layer 12. Even though such an analysis technique is used, etching is successfully stopped at a very low ratio. However, wet etching can utilize the nitride-based semiconductor layer 12 as an etch stop layer thereby achieving process margin that is essential to mass production. FIG. 9 is a graph comparing the etch rate of sapphire with that of GaN when etched with a mixed solution of H₂S0 and H₃P0₄. As seen in FIG. 9, the etch selectivity of sapphire with respect to nitride-based semiconductor by the mixed solution of H₂S0₄ and H₃P0₄ can be 20 or more at a specific temperature. This result reports that the nitride-based semiconductor layer 12 can be effectively used as an etch stop layer for the sapphire substrate 11. A high etch selectivity of 20 or more was obtained at a high temperature of 100 ^°C or more. In particular, since the etch rate of sapphire reaches or exceeds l m/min at a specific temperature, it is apparent that the fabrication method proposed by this invention is more advantageous than any conventional methods in view of production cost, productivity and process stabilization. An important factor for applying this method of the invention to mass production is to ensure process conditions that can increase the etch selectivity between the sapphire substrate 11 and the nitride-based semiconductor layer 12. It is particularly effective to use the nitride-based semiconductor layer 12 as an etch stop layer. Therefore, the nitride-based semiconductor layer 12 can be made of In_x (GayAli-y) N (l≥x≥O, l≥y≥O, x+y>0) , in which the composition of Al can be preferably raised. In addition, Mg-doped p-GaN may be effectively used. In the meantime, as shown in FIG. 4, the protective layer 15 of Si0₂ or SiN_x may be locally formed to make an etch stop layer prior to the formation of the nitride-based semiconductor layer 12 on the sapphire substrate 11. In particular, Si0₂ has a high etch selectivity with respect to sapphire. FIG. 11 is a photograph illustrating a cross section of a sapphire substrate in which grooves of different line width are formed via wet etching according to an embodiment of the invention. As seen in FIG. 11, the etched depth of a sapphire substrate is varied according to opened width, and becomes deeper in proportion to opened line width. As seen in FIG. 12, a pattern having an opened line width 57jMH is etched up to 24 m depth and thus has an aspect ratio 0.4, whereas a pattern having an opened line width lO m is etched only up to 1.5 m and thus has an aspect ratio 0.1. That is, the sapphire substrate has an orientation with respect to wet etching, and its etched depth depends on patterned width. Most available sapphire base substrates are of C plane or (0001) plane, and when wet etched, its etched surface generally forms an inclination of about 54 or 25 degree according to M, R or A plane as shown in FIG. 11. This phenomenon is observed because of the different etch rate of etched facets such as C plane (0001) , M plane (10-10) , R plane (-1012) andAplane (11-20) . The dependences of sapphire etch rate with respect to surface orientation are in the order of C, M, R and A planes, that is, C plane > M plane > R plane > A plane. This result indicates that the etching depth is determined by opened width and thus can be controlled freely adjusting opened width. For example, narrowing opened line width can stop etching at a depth of 1/zm or less . When observed with a microscope, the etched surface showed a very clean morphology and there were no large thickness variation. FIG. 13 is a photograph illustrating the surface of the nitride-based semiconductor layer 12 when the sapphire substrate is removed via wet etching. As shown in FIG. 13 even after the sapphire substrate 11 was removed, substantially no breaks or damages were found from the nitride-based semiconductor layer 12, which had a very clean surface state. Finally, as shown in FIG. 7, the protective layer is immersed into Buffer Oxide Etchant (BOE) and etched thereby so as to produce a f ee-standing semiconductor wafer. The produced free-standing semiconductor wafer is shown in a plan view in the bottom part of FIG. 7. When a whole device structure is grown on a sapphire substrate and then the sapphire substrate is removed, a nitride-based semiconductor layer is not necessarily grown thereon. On the other hand, when the semiconductor wafer is used as a base substrate for crystal growth, the nitride-based semiconductor layer 13 is regrown on the semiconductor wafer to fabricate a vertical electrode LED, a vertical electrode laser diode, an HBT and so on. The nitride-based semiconductor layer 13 may be of single or multiple layers grown via MOCVD, LPE, MBE, VPE or combinations thereof. Preferably, the nitride-based semiconductor layer 13 is grown via MOCVD in view of the film quality and productivity of nitride-based semiconductor. Nitride-based semiconductor is regrown on the semiconductor wafer via MOCVD since homostructure can grow a fine quality semiconductor layer without crystal growth defect as well as facilitates device fabrication such as cleaving line formation and dicing.

Fabrication of Semiconductor Wafer FIG. 16 illustrates process steps of a free-standing nitride-based semiconductor wafer. FIG. 16(a) shows a nitride-based semiconductor layer 12 of In_x (Ga_yAlι-_y) N having a thickness of 300 μm grown on a sapphire substrate 11 having a thickness of 430 m via HVPE. FIG. 16 also illustrates a fabrication process which removes the sapphire substrate 11 to produce a nitride-based semiconductor wafer. In_x (Ga_yAlι__y) N nitride-based semiconductor has a composition of l≥x≥O, l≥y≥O and x+y>0. As shown in FIG. 16, a protection layer 15 for example of Si0₂ is formed on the nitride-based semiconductor layer 12 to protect the nitride-based semiconductor layer 12 from damage in wet etching. The protection layer 15 is deposited at a thickness of about lμm via Plasma Enhanced Chemical Vapor Deposition (PECVD) . The Si0₂ protective layer 15 is rarely influenced by etching solution and thus can prevent the nitride-based semiconductor layer 12 from contacting etching solution. The nitride-based semiconductor layer 12 grown on the sapphire substrate 11 may be of single or multiple layers grown via MOCVD, LPE, MBE, HVPE or combinations thereof. In addition, nitride-based semiconductor layer 12 may be of single or multiple layers regrown via MOCVD on a nitride-based semiconductor layer that is grown via MOCVD, LPE, MBE or VPE. The layer structure is not particularly influential in this process for the free-standing semiconductor wafer. In view of following processes for a nitride-based semiconductor structure and a device, it is advantageous to make the nitride-based semiconductor layer 12 have a large thickness. However, the thickness is limited owing to the strain between the sapphire base substrate and the nitride-based semiconductor layer. Therefore, the thickness of semiconductor layer 12 is determined preferably in a range from

The protection layer for the nitride-based semiconductor layer may adopt a single layer of Spin-On Glass (SOG) or Si0₂. Alternatively, multiple layers made of combinations thereof can be formed as a protection layer. After the protective layer 15 deposited to a thickness of 1 μm, the sapphire substrate 11 is lapped and polished up to a thickness of 100 to 300jMm, and the lapped side is mirror polished into a smooth surface having a roughness of 20 m or less (FIG. 16(b) ) . In this case, it is more desirable for the sapphire substrate 11 to have a smaller thickness. However, since extremely small thickness may cause bending to the sapphire substrate 11 or worsen its workability, the sapphire substrate 11 preferably has a thickness of about 10 to lOOjUm. It is also preferred that the mirror-polished sapphire substrate 11 has a surface roughness of 20 m or less. Otherwise, the surface roughness of the sapphire substrate 11 may be transferred to the nitride-based semiconductor layer thereby damaging a resultant nitride-based semiconductor structure. The sapphire substrate 11 may be lapped via CMP, ICP/RIE or RIE dry etching or mechanical lapping with alumina (A1₂0₃) powder. Alternatively, the lapping may be performed via wet etching using an etching solution containing HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, H₂0, KOH, KHS0₄, Aluetch(4H₃Pθ₄+4CH₃COOH+HNθ₃+H₂θ) or combinations thereof. The ICP/RIE or RIE dry etching uses an etching gas selected from BCI₃, Cl₂, HBr, Ar and combinations thereof. In case of a mixed solution of sulphuric acid (HS0₄) and phosphoric acid (H₃PO4) , it is preferred that sulphuric acid has a fraction of 5 to 95% and the mixed solution is heated to a temperature of 100 ^°C or more. In this case, The ICP/RIE or RIE dry etching uses an etching gas selected from BC1₃, Cl₂, HBr, Ar and combinations thereof. Then, the sapphire substrate 11 is wet etched as follows: (Refer to FIG. 16(c) and FIG. 18.) Upon being lapped, precise thickness measurement is performed to collect wafers 133 having a thickness error of ±IOJMΪI or less. The collected wafers 133 are mounted on a wafer loader 114 as shown in FIG. 18. Uniform wafers are collected and mounted on the wafer loader since it is difficult to ensure process margin or obtain uniform properties from ununiform wafers. That is, even though etched at the same time period, the ununiform sapphire substrates may be over-etched or under-etched according to their thickness uniformity. Then, some sapphire substrates may remain after etching. So, the wafer collection is performed to avoid this problem. A wafer is heated to a high temperature in the vicinity of 200 ^°C before being immersed into an etching solution. The wafer is pre-heated at a temperature ranging from about 100 to 320^°C. A large temperature difference between a wafer to be etched and an etching solution tends to break the wafer. Thus, the temperature difference is minimized for the purpose of raising productivity. Then, the heated wafer is carried to an etch bath 116. The wafer is etched ?by the etching solution at a temperature of about 325°C. The etching solution is selected from the group consisting of HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, H₂0, Aluetch(4H₃P0₄+4CH₃COOH+HNθ3+H2θ) and combinations thereof. In case that a mixed solution of sulphuric acid (H₂SO₄) and phosphoric acid (H3PO4) is used, it is preferred that sulphuric acid has a fraction of 5 to 95% and the mixed solution is heated to a temperature of 100 °C or more. Etching time is set as follows : First, the etch rate of a sapphire layer 11 by the etching solution is measured, and then the wafer 133 is immersed into the etching solution for a specific time period estimated to etch a sapphire substrate having a thickness added for 0.1 tm to the thickness of the sapphire layer 11. That is, the etching time is so set that etching is performed longer than the time period necessary for completely etching the thickness t of the sapphire substrate . FIG. 10 is a graph illustrating etch rate according to temperature variation when sapphire and GaN are wet etched by a mixed solution of H₂S0₄ and acid H₃PO₄. As seen in FIG. 10, the etch rate of sapphire increases in proportion of the temperature of the etching solution. Therefore, the temperature of the etching solution is preferably maintained at least 100 °C to reduce the etching time. Heating for maintaining the etching solution at 100 ^°C or more can be performed directly or indirectly. Direct heating is performed as shown in FIG. 20, in which hot wires 144 are placed in the etch bath 116 to directly contact the etching solution. Also, as shown in FIG. 21, indirect heating may be performed via optical absorption in which halogen lamps 145 are placed outside the etch bath to radiate light so as to heat the etching solution in the etch bath. When the sapphire layer 11 is completely removed from the nitride-based semiconductor layer according to the etching, a carrier arm 112 carries the wafer to the cleaner 117 and the drier 118 in sequence to clean and dry the wafer, and then to a wafer unloader 119, which in turn completely unloads the wafer from the carrier arm 112. By the mixed etching solution of H₂S0₄ and H₃PO₄ used herein, nitride-based semiconductor shows an etch rate that is 1/10 or less compared to that of the sapphire layer 11. That is, the nitride-based semiconductor layer 12 has an etch selectivity of 10 or more with respect to the sapphire layer 11. Therefore, although the etching is performed for a time period that is sufficient to completely etch the sapphire substrate 11, there is no risk of damaging the nitride-based semiconductor layer 12 since it is etched slowly enough. FIG. 9 is a graph comparing the etch rate of sapphire with that of GaN when etched with a mixed solution of H₂S0₄ and H₃P0₄. As seen in FIG. 9, the etch selectivity of sapphire with respect to nitride-based semiconductor by the mixed solution of H₂SO₄ and H₃PO₄ can be 20 or more at a specific temperature. This result reports that the nitride-based semiconductor layer 12 can be effectively used as an etch stop layer for the sapphire layer 11. A high etch selectivity of 20 or more was obtained at a high temperature of 100 ^°C or more as in FIG. 10. In particular, it can be observed that sapphire has an etch rate of l m/min or more at 325^°C. So, it is apparent that the fabrication method proposed by this invention is more advantageous than any conventional methods in view of production cost, productivity and process stabilization. An important factor for applying the present invention to mass production is to ensure process conditions capable of raising the etch selectivity between the sapphire layer 11 and the nitride-based semiconductor layer 12. In particular, the nitride-based semiconductor layer 12 can be effectively used as an etch stop layer.

The nitride-based semiconductor layer 12 can be made of In_x (Ga_yAlι__y) N (l≥x≥O, l≥y≥O, x+y>0), in which the composition of Al can be preferably raised. In addition, Mg-doped In_x (Ga_yAlι-_y) N semiconductor may be effectively used (l≥x≥O, l≥y≥O, x+y>0). In the meantime, Si0₂ clusters may be locally formed to make an etch stop layer prior to the formation of the nitride-based semiconductor layer 12 on the sapphire layer 11. The etch stop layer may be made of In_x (Ga_yAlχ-_y) N (l≥x≥O, l≥y≥O, x+y>0), silicon oxide clusters, silicon nitride-based clusters (e.g., of Si0₂ or SiN_x) and combinations thereof. FIG. 17 is a photograph illustrating an etched surface of a sapphire substrate when a specific pattern is formed on the sapphire substrate and the sapphire substrate is etched according to a specific pattern via wet etching using a mixed solution of sulphuric acid (H₂S0₄) and phosphoric acid (H₃PO₄) at a temperature of 320^°C. It can be observed that the flat underside area of the etched sapphire substrate is proportional to the area of the opened pattern, in which etched inclinations and the substrate surface are very clean. The sapphire substrate was etched to 22.4 m for 20 minutes, thereby showing an etch rate of 1.1 tm/min . This etch rate is a consideralole result satisfactory in view of chip mass production. The wet etching has more advantages than any other approaches in view of mass production since it is not restricted to the productivity of equipments. The sapphire substrate has an orientation with respect to wet etching, and its etched depth depends on patterned width. Most available sapphire substrates are of C plane or (0001) plane, and when wet etched, its etched surface generally forms an inclination of about 54 or 25 degree according to M, R or A plane. This phenomenon is observed because of the different etch rate of etched facets such as C plane (0001) , M plane (10-10) , R plane (-1012) and A plane (11-20) . The dependences of sapphire etch rate with respect to surface orientation are in the order of C, M, R and A planes, that is, C plane > M plane > R plane > A plane. When observed with a microscope, the etched surface showed a very clean morphology and there were no large thickness variation. FIG. 13 is a photograph illustrating the surface of a nitride-based semiconductor layer 12 when the sapphire substrate is removed via wet etching. As shown in FIG. 13 even after the sapphire substrate 11 was removed, substantially no breaks or damages were found from the nitride-based semiconductor layer 12, which had a very clean surface state. After the above process, the Si0₂ protection layer is immersed into buffer oxide etchant (HF or BOE) and etched thereby as in FIG.

16(d) to produce a complete free-standing semiconductor wafer. The produced free-standing semiconductor wafer has a planar configuration as shown in FIG. 16(e). After the free-standing semiconductor wafer is produced, a nitride-based semiconductor layer is regrown thereon via MOCVD since homostructure can grow a fine quality semiconductor layer without crystal growth defect as well as facilitates device fabrication such as cleaving line formation and dicing.

Apparatus for Fabricating Semiconductor Wafers FIG. 18 illustrates an apparatus for fabricating free-standing semiconductor wafers according to the invention. As shown in FIG. 18, the apparatus for fabricating free-standing semiconductor wafers according to the invention includes a wafer loader 114, a solution heater 115, an etch bath 116, a wafer cleaner 117, a wafer drier 118 and a wafer unloader 119. In addition, there is arranged a carrier arm 112 for automatically carrying the wafer. First the wafer loader 114 loads semiconductor wafers 133 each having a nitride-based semiconductor layers grown on a sapphire substrate. The sapphire substrates are lapped and polished from the semiconductor wafers 133, and several of the semiconductor wafers 133 having a similar thickness are loaded. That is, upon being lapped, precise thickness measurement is performed to collect the wafers 133 having a thickness error of ±IOJMΠ or less, and the collected wafers 133 are loaded on the wafer loader 114. Uniform wafers are collected and mounted on the wafer loader since it is difficult to ensure process margin or obtain uniform properties from ununiform wafers. That is, even though etched at the same time period, the ununiform sapphire substrates may be over-etched or under-etched according to their thickness uniformity. Then, some sapphire substrates may remain after etching. So, the wafer collection is performed to avoid this problem. The wafers 133 loaded on the wafer loader 114 are heated up to a temperature in the vicinity of 200 ^°C similar to the temperature of an etching solution within the etch bath. The wafers are pre-heated at a temperature ranging from about 100 to 320 ^°C. A large temperature difference between a wafer to be etched and an etching solution tends to break the wafer. Thus, the temperature difference is minimized for the purpose of raising productivity. Then, the heated wafers are carried to the etch bath 116. The carrier arm 112 is used to carry the wafers 133 to the etch bath. The carrier arm 112 is at its top connected to a rail 113, as shown in FIG. 18, to move in a horizontal direction. In addition, the carrier arm 112 is designed adjustable in vertical length so that it can elevate the wafers 133 from the wafer loader. This structure may adopt a hydraulic or pneumatic cylinder or a timing bel . Since the wafers 133 are wet etched at a high temperature condition, the carrier arm 112 is used to ensure safer working conditions to operators. The solution heater 115 is installed in front of the etch bath 116 to pre-heat an etching solution for etching sapphire substrates. Since heating the etching solution to a high temperature within the etch bath takes a long time period, the etching solution is pre-heated by the solution heater 115 so that the etching solution is maintained hot in the etch bath 116. The solution heater 115 can advantageously reduce a time period for heating the etching solution while allowing any contaminated etching solution to be directly discharged from the etch bath and replaced by clean one. FIG. 19 illustrates the wet etch bath in detail. As shown in FIG. 19, the etch bath is designed to heat an etching solution rapidly as well as automatically adjust the temperature of the etching solution. Cooling pipes 127 are arranged around the etch bath 116 to adjust the temperature of the etching solution. The cooling pipes 127 are wound on the etch bath, and controlled by a controller 124 and a control valve 130. The temperature of the etch bath 116 is automatically regulated by the controller 125. If the temperature is too high, the etch bath 116 can be cooled down by the cooling pipes 127 wound thereon and thus the temperature can be adjusted rapidly. The etching solution heated to a high temperature generates acid vapor, which may cause risk to operators. In order to prevent such risk, the etch bath is covered with a cover 120 and a drainpipe 122 is provided to drain acid vapor . Hot acid vapor may pollute environment or damage the fabricating apparatus when discharged to the outside. So, the drainpipe 122 has a liquidizing pipe 121 designed to cool hot acid vapor into liquid. Then, liquid collects in a drain box 123. The etch bath 116 is powered by an external power supply 124. Also, the controller 125 automatically controls valves of the drainpipe

122 and the liquidizing pipe 121 in addition to the cooling pipes. The etch bath 116 is made of high temperature Teflon, quartz, glass or SUS. In addition, the etch bath 116 is preferably maintained at a temperature of 100°C or more during etching. Heating for this purpose can be performed directly or indirectly. Direct heating is performed as shown in FIG. 20, in which hot wires 144 are placed in the etch bath 116 to directly contact the etching solution. Also, as shown in FIG. 21, indirect heating may be performed via optical absorption in which halogen lamps 145 are placed outside the etch bath to radiate light so as to heat the etching solution in the etch bath. In etching the wafers, the etching solution has a temperature of about 325°C, and selected from the group consisting of HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, H₂0, Aluetch (4H₃P0₄+4CH₃COOH+HN03+H2θ) and combinations thereof. Etching time is set as follows : First, the etch rate of a sapphire substrate 11 by the etching solution is measured, and then the wafers 133 are immersed into the etching solution for a specific time period estimated to etch a sapphire substrate having a thickness added for 0. ljum to the thickness of the sapphire layer or substrate 11. That is, the etching time is so set that etching is performed longer than, the time period necessary for completely etching the thickness t of the sapphire substrate. When the sapphire substrates are completely removed in the etch bath 116, again referring to FIG. 18, the wafers are immersed and cleaned by the cleaner 117, and then dried by the drier 118. In the cleaning step, the wafers are immersed into distilled water and. cleaned thereby, and the cleaned wafers are carried to the rotary drier 118 to be dried thereby. Then, the substrate unloader 119 unloads the wafers 133 from the carrier arm 112.

Second Embodiment The second embodiment of the invention is adapted to utilize a nitride-based semiconductor layer grown on a sapphire substrate as is used in the first embodiment of the invention, and to remove the sapphire substrate through mechanical lapping or polishing only so as to fabricate semiconductor wafers. That is, when nitride-based semiconductor layers 12 and 13 are grown on the sapphire substrate,. the sapphire substrate can be removed via mechanical lapping or polishing only. This requires that the nitride-based semiconductor layer 12 grown via HVPE to be used as a base layer of a free-standing semiconductor wafer have a thickness of 100im or more. Regarding that lapping has a thickness tolerance value of ±3 m, there is a process margin. Although a process is complicated and difficult if the sapphire substrate is removed via lapping only, the nitride-based semiconductor layer 13 on the sapphire substrate 11 is wax bonded to a lapping holder and then the sapphire substrate 11 is mechanically lapped or polished with AI₂O₃ powder so as to produce a free-standing nitride-based semiconductor wafer.

Third Embodiment FIG. 14 illustrates intermediate steps in a fabrication method of a semiconductor wafer according to the third embodiment of the invention, in which a sapphire substrate is removed via etching to produce a semiconductor wafer. The fabrication method is similar to that of the first embodiment but an auxiliary substrate is attached before the sapphire substrate is removed via etching. As the auxiliary substrate is attached, it is possible to perform backside-polishing on the sapphire substrate thereby saving etching time for the sapphire substrate. In addition, this can advantageously solve a bending problem that the substrate can be bent when it becomes thin by backside-polishing. Detailed description will follow with reference to the drawings . As shown in FIG. 14, an In_x (Ga_yAlι__y) N nitride-based semiconductor layer 12 is grown at a thickness of 100 tm on a sapphire substrate 11 via HVPE, and an In_x (Ga_yAlι__y) N nitride-based semiconductor layer 13 is regrown at a thickness of 5 on the In_x (Ga_yAlι__y) N nitride-based semiconductor layer 12 via MOCVD. In this case, the In_x (Ga_yAlι-_y) N nitride-based semiconductor layer 12 formed on the sapphire substrate 11 may be of single or multiple layers grown via MOCVD, LPE, MBE or VPE. The In_x (Ga_yAlι__y) N nitride-based semiconductor layer 13 may be of single or multiple layers regrown on the In_x (Ga_yAlι__y) N nitride-based semiconductor layer 12 grown via MOCVD, LPE, MBE or VPE. The layer structure is not particularly influential in this process for the free-standing semiconductor wafer. In view of following processes for a nitride-based semiconductor structure and a device, it is advantageous to make the nitride-based semiconductor layers have a large thickness. However, the thickness is limited owing to the stress between the sapphire base substrate and the nitride-based semiconductor layers. Therefore, the total thickness of semiconductor layers 12 and 13 is determined preferably in a range from 10 to 500/ . Next, a hard mask or protective layer 15 of for example Spin-On Glass (SOG) or Si0₂ is deposited at a thickness of lμm on the semiconductor layers to protect the surface thereof in following wet or dry etching. Then, an auxiliary substrate 18 is attached thereon. Available examples of the auxiliary substrate 18 may include an insulating substrate of for example sapphire, a semiconductor substrate of for example Si, GaAs, GaP, InP and InAs and a conductive oxide substrate of for example Indium Tin Oxide (ITO) , ZrB and ZnO. The auxiliary substrate 18 is preferably attached with an adhesive such as wax and eutectic metal. In the attachment process, eutectic metal 16, 17 is deposited onto the protective layer of Si0₂ or SOG overlying the nitride-based semiconductor layers 12 and 13, and eutectic metal is deposited onto the auxiliary substrate 18. Eutectic metal contains Ti, Au, Sn, In, Pd, Pt, Rh, Ni or combinations thereof, and is heat-pressed. In particular, an alloy containing Au and/or Pt is preferable since Au and Pt have strong resistance against acid. In this case, heat pressing is performed at a temperature ranging from about 300 to 500^°C under a pressure of about 1 to 3MP for 3 to 60 minutes. Then, the sapphire substrate 11 is lapped and polished up to a thickness of 30 to 50/tm . The sapphire substrate 11 may be lapped via CMP, ICP/RIE or RIE dry etching or mechanical lapping with alumina (A1₂0₃) powder. Alternatively, the lapping may be performed via wet etching using an etching solution containing HCl, HNO₃, KOH, NaOH, H₂SO₄, H₃PO₄, Cr0₃, H₂0, KOH, KHSO₄, Aluetch (4H₃Pθ₄+4CH₃COOH+HNθ₃+H₂0) or combinations thereof. The ICP/RIE or RIE dry etching uses an etching gas selected from BCI₃, Cl₂, HBr, Ar and combinations thereof. In this case, it is more desirable for the sapphire substrate 11 to have a smaller thickness, and preferably a thickness of about 10 to 50/tm . It is also preferred that the mirror-polished sapphire substrate 11 has a surface roughness of 20 m or less. Otherwise, the surface roughness of the sapphire substrate 11 may be transferred to the nitride-based semiconductor layer 12 thereby damaging a resultant nitride-based semiconductor structure. When the sapphire substrate 11 is removed via wet etching, the wafer is immersed into BOE to etch the oxide protective layer 15 so as to separate the auxiliary substrate is detached from the nitride-based semiconductor layer 13. In this way, a free-standing semiconductor wafer is produced. In this case, a partial area of the sapphire substrate can be removed via dry etching such as ICP/RIE or via a combination of wet etching and dry etching. Dry etching itself does not stop etching at the nitride-based semiconductor layer but wet etching can stop etching at the nitride-based semiconductor layer. Except for this, the sapphire substrate 11 is wet etched as previously described in the preferred embodiment.

Fourth Embodiment FIG. 15 illustrates intermediate steps in a fabrication method of a semiconductor wafer according to the fourth embodiment of the invention, in which a sapphire substrate 11 is partially removed via etching. This fabrication method is generally similar to the previously described one of the preferred embodiment except that an oxide layer 19 of Si0₂ is deposited at a thickness of Iμm on the sapphire substrate 11 and etched via photolithography so that the sapphire substrate 11 is etched in part via oxide layer patterning. In this method, the sapphire substrate is etched in part to ensure a semiconductor contact area. By the etched partial area, a semiconductor layer can be easily broken or handled. Occasionally, the etched partial area can be utilized as scribing lines by which the wafer is to be broken into pieces according to devices. The patterned configuration and size of the oxide layer is not limited specifically but can be modified variously according to its application. Rather, the oxide layer may be patterned into a configuration opposite to that as shown in FIG. 15. Detailed description will follow with reference to the drawings . As shown in FIG. 15, an In_x (Ga_yAlι__y) N nitride-based semiconductor layer 12 is grown at a thickness of iO O tm on a sapphire substrate 11 via HVPE and an In_x (Ga_yAlι__y) N nitride-based semiconductor layer 13 is regrown at a thickness of 5 m on the nitride-based semiconductor layer 12 via MOCVD. As described above, the nitride-based semiconductor layer 12 formed on the sapphire substrate 11 may be of single or multiple layers grown via MOCVD, LPE, MBE or VPE, and the nitride-based semiconductor layer 13 may be of single or multiple layers regrown via MOCVD on the nitride-based semiconductor layer 12. The layer structure is not particularly influential in this process for the free-standing semiconductor wafer. In view of following processes for a nitride-based semiconductor structure and a device, it is advantageous to make the nitride-based semiconductor layers have a large thickness. However, the thickness is limited owing to the stress between the sapphire base substrate and the nitride-based semiconductor layers. Therefore, the total thickness of semiconductor layers 12 and 13 is determined preferably in a range from 10 to 500 m. Then, the sapphire substrate is lapped and polished up to a small thickness of 30 to 50 m. The sapphire substrate 11 may be lapped via CMP, ICP/RIE or RIE dry etching or mechanical lapping with alumina powder. Alternatively, the lapping may be performed via wet etching at a high temperature using an etching solution containing HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, H₂0, KOH, KHS0₄, Aluetch(4H₃Pθ₄+4CH₃COOH+HNθ₃+H₂θ) or combinations thereof. The ICP/RIE or RIE dry etching uses an etching gas selected from BC1 , Cl₂, HBr, Ar and combinations thereof. In this case, it is more desirable for the sapphire substrate 11 to have a smaller thickness, and preferably a thickness of about 10 to 50 m. It is also preferred that the mirror-polished sapphire substrate 11 has a surface roughness of 20 m or less. Otherwise, the surface roughness of the sapphire substrate 11 may be transferred to the nitride-based semiconductor layer 12 thereby damaging a resultant nitride-based semiconductor structure. Next, an Si0₂ oxide layer is deposited at a thickness of ljtffll on the sapphire substrate, and patterned via photolithography etching the Si0₂ layer via BOE or RIE. Then, sapphire substrate 11 is etched by using the Si0₂ layer as an etch mask. When the sapphire substrate 11 is removed via wet etching, the wafer is immersed into BOE to etch the oxide protective layer 15 so as to produce a free-standing semiconductor wafer. Other wet etching processes of the sapphire substrate 11 will be performed as previously described in the preferred embodiment.

Industrial Applicability As described above, the present invention can remove the sapphire substrate from the nitride-based semiconductor structure grown thereon in easier ways than conventional approaches thereby fabricating vertical electrode LEDs at a low cost. This invention can improve the reliability and brightness of LEDs but reduce their size to improve the productivity and performance of the LEDs, and thus can provide key approaches enabling fabrication of high brightness and performance nitride-based semiconductor LEDs. In addition, the invention enables the fabrication of other electronic devices such as HBT, which have been considered impossible to produce, thereby enabling the production of high frequency and high power electronic devices. In this way, the invention can contribute to incessant development in the art. While the present invention has been described in connection with the embodiments illustrated in the drawings, it will be apparent to those skilled in the art that modifications, variations and equivalents can be made from the embodiments. Therefore, the protective scope of the invention shall be defined only by the appended claims .

Claims

1. A semiconductor wafer comprising a nitride-based semiconductor layer grown on a sapphire (A1₂0₃) substrate, wherein at least a part of the sapphire substrate is separated from the nitride-based semiconductor layer.

2. The semiconductor wafer according to claim 1, wherein the sapphire substrate is separated from the nitride-based semiconductor layer via etching.

3. The semiconductor wafer according to claim 1, wherein the sapphire substrate has a thickness of about 50 to 800/ .

4. The semiconductor wafer according to claim 1, wherein the sapphire substrate has a crystal growth plane selected from C, M, A and R planes.

5. The semiconductor wafer according to claim 1, wherein the sapphire substrate is patterned in x or y direction.

6. The semiconductor wafer according to claim 1, wherein the semiconductor layer comprises at least one nitride-based semiconductor layer of In_x (Ga_yAlι__y) N, wherein l≥x≥O, l≥y≥O and x+y>0

7. The semiconductor wafer according to claim 6, wherein the semiconductor layer has a thickness of about 10 to 500/tm.

8. The semiconductor wafer according to claim 6, the semiconductor layer is grown via at least one selected from a group consisting of Vapor Phase Epitaxy (VPE) , Hydride Vapor Phase Epitaxy (HVPE) , Metal Organic Vapor Phase Epitaxy (MOVPE) , Metal Organic Chemical Vapor Deposition (MOCVD) , Molecular Beam Epitaxy (MBE) , Low Pressure Chemical Vapor Deposition (LPCVD) , Liquid Phase Epitaxy (LPE) and combinations thereof.

9. The semiconductor wafer according to claim 6, wherein the semiconductor layer comprises one selected from a group consisting of high resistance semiconductor, p-type semiconductor and n-type semiconductor .

10. The semiconductor wafer according to claim 9, wherein the high resistance semiconductor has a doping concentration of 10El7/cm³ or less.

11. The semiconductor wafer according to claim 9, wherein the p- type semiconductor layers and n-type semiconductor layers have a doping concentration of 10El8/cm³ or more and a resistivity of 10E-2 Ωc or less.

12. The semiconductor wafer according to claim 2, further comprising an etch stop layer grown between the sapphire substrate and the nitride-based semiconductor layer, the etch stop layer adapted to stop etching proceeding from the sapphire substrate.

13. The semiconductor wafer according to claim 12, wherein the etch stop layer comprises a nitride-based semiconductor layer.

14. A fabrication method of semiconductor wafers, comprising steps of: (a) preparing a substrate of sapphire (A1₂0₃) ; (b) forming a semiconductor layer on the substrate; (c) forming a protective layer on the semiconductor layer; (d) lapping and polishing the substrate and etching the substrate to remove the substrate from the semiconductor layer via; and (e) removing the protective layer via etching.

15. The fabrication method according to claim 14, wherein the etching in the (d) step is performed with an etching solution containing at least one selected from a group consisting of HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃PO₄, Cr0₃, KOH, KHSO₄, Aluetch(4H₃P0₄+4CH₃COOH+HNθ₃+H₂θ) and mixtures thereof.

16. The fabrication method according to claim 15, wherein the semiconductor layer is adapted to act as an etch stop layer in wet etching.

17. The fabrication method according to claim 16, wherein the semiconductor layer comprises at least one selected from a group consisting of an In_x (Ga_yAlι-_y) N layer (l≥x≥O, l≥y≥O and x+y>0), a silicon oxide cluster such as Si0₂ and a silicon nitride-based cluster such as SiN_x.

18. The fabrication method according to claim 15, wherein the etching in the (d) step is performed with the etching solution heated to a temperature of at least 100^°C.

19. The fabrication method according to claim 18, wherein the etching solution is heated indirectly via optical absorption.

20. The fabrication method according to claim 15, wherein the etching in the (d) step further comprises dry etching of ICP/RIE or RIE.

21. The fabrication method according to claim 20, wherein the dry etching utilizes at least one etching gas selected from a group consisting of BC1₃, Cl₂, HBr and Ar.

22. The fabrication method according to claim 14, wherein the lapping and polishing in the (d) step mirror polishes the sapphire substrate to have a surface roughness of 20μm or less.

23. The fabrication method according to claim 14, wherein the lapping and polishing in the (d) step makes the sapphire substrate to a thickness of 300jttm or less.

24. The fabrication method according to claim 14, wherein the lapping and polishing in the (d) step is performed via at least one of mechanical polishing, Chemical Mechanical Polishing (CMP) and wet etching, wherein the wet etching uses an etching solution containing at least one selected from a group consisting of HCl, HN0₃, KOH, NaOH, H₂S0₄, H₃PO₄, Cr0₃, Aluetch(4H₃PO₄+4CH₃C0OH+HNO₃+H₂O) and mixtures thereof.

25. The fabrication method according to claim 14, wherein the protective layer is made of Si0₂ or Spin-On Glass (SOG) .

26. A fabrication method of semiconductor wafers, comprising steps of: (a) preparing a substrate of sapphire (A1₂0₃) ; (b) forming an etch stop layer on the substrate; (c) forming a semiconductor layer on the etch stop layer; (d) forming a protective layer on the semiconductor layer; (e) lapping and polishing the substrate and etching the substrate to remove the substrate from the semiconductor layer; and (f) removing the protective layer.

27. The fabrication method according to claim 26, further comprising a step of attaching an auxiliary substrate on the protective layer after the (d) step, and wherein the auxiliary substrate is separated from the semiconductor layer by the (f) step of removing the protective layer via etching.

28. The fabrication method according to claim 27, wherein the auxiliary substrate comprises an insulating substrate.

29. The fabrication method according to claim 27, wherein the semiconductor substrate comprises a semiconductor substrate.

30. The fabrication method according to claim 27, wherein the auxiliary substrate is attached via adhesive means made of eutectic metal .

31. The fabrication method according to claim 30, wherein the eutectic metal comprises at least one selected from a group consisting of In, Ni, Pd, Au, Ti, Pt, Rh and combinations thereof.

32. The fabrication method according to claim 26, wherein the etch stop layer and the semiconductor layer comprise one selected from a group consisting of an In_x (Ga_yAlι-_y) N layer (l≥x≥O, l≥y≥O and x+y>0) , a silicon oxide cluster and a silicon nitride-based cluster of Si0₂ or SiN_x.

33. The fabrication method according to claim 26, wherein the etching in the (e) step is performed with an etching solution containing at least one selected from a group consisting of HCl, HNO₃, KOH, NaOH, H₂S0₄, H₃P0₄, Cr0₃, Aluetch (4H₃PO₄+4CH₃COOH+HNO₃+H₂O) and mixtures thereof.

34. The fabrication method according to claim 33, wherein the etching in the (e) step is performed with the etching solution heated to a temperature of at least 100^°C.

35. The fabrication method according to claim 34, wherein the etching solution is heated indirectly via optical absorption.

36. The fabrication method according to claim 33, wherein the etching in the (e) step further comprises dry etching which utilizes at least one etching gas selected from a group consisting of BC1₃, Cl₂, HBr and Ar.

37. The fabrication method according to claim 26, wherein the lapping and polishing in the (e) step mirror polishes the sapphire substrate to have a surface roughness of 20ffll or less.

38. The fabrication method according to claim 26, wherein the lapping and polishing in the (d) step makes the sapphire substrate to a thickness of 300 tm or less.

39. The fabrication method according to claim 26, wherein the protective layer is etched via HF or Buffer Oxide Etchant (BOE) .

40. The fabrication method according to claim 26, wherein the protective layer is made of Si0₂ or Spin-On Glass (SOG) .

41. A semiconductor wafer produced according to a fabrication method as described in any of preceding claims 14 to 25.

42. A semiconductor wafer produced according to a fabrication method as described in any of preceding claims 26 to 40.

43. An apparatus for fabricating free-standing semiconductor wafers, comprising: a loader for loading semiconductor wafers each having a sapphire substrate and a nitride-based semiconductor layer grown on the sapphire substrate, wherein the sapphire substrates are lapped and polished to a substantially uniform thickness, and heating the semiconductor wafers to a predetermined temperature; a solution heater for pre-heating an etching solution for etching the sapphire substrates of the semiconductor wafers; a carrier arm having its top portion connected to a rail for enabling horizontal movement, and designed vertically adjustable in length to elevate the semiconductor wafers from the wafer loader; an etch bath for etching the sapphire substrates of the semiconductor wafers carried by the carrier arm; a cleaning and drying unit for cleaning and drying the semiconductor wafers which are etched in the etch bath so that the sapphire substrates are removed therefrom; and an unloader for unloading the cleaned and dried semiconductor wafers from the carrier arm.

44. The apparatus according to claim 43, wherein the sapphire substrates of the semiconductor wafers loaded on the loader have a thickness within an error range of ±lOμm.

45. The apparatus according to claim 43, wherein the etch bath uses an etching solution containing at least one selected from a group consisting of H₂S0₄, H₃PO₄ and combinations thereof.

46. The apparatus according to claim 45, wherein H₂S0₄ has a fraction of 5 to 95% when mixed with H₃PO₄.

47. The apparatus according to claim 45, wherein the etching solution is maintained at least 100^°C.

48. The apparatus according to claim 47, wherein the etch bath has hot wires for directly applying heat to the etching solution within the etch bath to maintain the temperature of the etching solution.

49. The apparatus according to claim 47, wherein indirect heating is performed by radiating light to the etching solution within the etch bath to maintain the temperature of the etching solution.

50. The apparatus according to claim 43, wherein the etch bath comprises : a cooling pipe arranged around the etch bath to adjust the temperature of the etching solution; a cover adapted to open/close the etch bath so that vapor generated from the etching solution does not leak to the outside; a drain pipe connected to the etch bath to drain vapor generated from the etching solution; a liquidizing pipe arranged around the drain pipe to cool and liquidize vapor drained through the drain pipe; and a controller for automatically controlling the cooling pipe, the drain pipe and the liquidizing pipe.

51. The apparatus according to claim 50, wherein the etch bath is made of one selected from a group consisting of high temperature Teflon, SUS, glass and quartz.

52. A free-standing semiconductor wafer produced from a fabrication apparatus as described in any of the preceding claims 43 to 51.