CN112527576A - Method, equipment, medium and device for testing PCIe link signal at high temperature - Google Patents
Method, equipment, medium and device for testing PCIe link signal at high temperature Download PDFInfo
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- CN112527576A CN112527576A CN202011353081.5A CN202011353081A CN112527576A CN 112527576 A CN112527576 A CN 112527576A CN 202011353081 A CN202011353081 A CN 202011353081A CN 112527576 A CN112527576 A CN 112527576A
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- 238000010438 heat treatment Methods 0.000 claims abstract description 89
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- 238000004458 analytical method Methods 0.000 claims description 20
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- 238000004590 computer program Methods 0.000 claims description 10
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
The invention discloses a method for testing PCIe link signals at high temperature, which comprises the steps of detecting the temperature of a mainboard to be tested, and testing an eye diagram of a PCIe link in the mainboard to be tested at the initial temperature; setting a heating range and a temperature threshold; the mainboard to be measured is gradually heated through the heating module, and when the temperature of the mainboard to be measured exceeds a temperature threshold value, the heating module stops heating and gives an alarm; in the step-by-step heating process, testing the eye pattern of the PCIe link in the mainboard to be tested each time heating is carried out, and obtaining the eye patterns of the PCIe link at a plurality of temperatures; calculating the temperature range of the PCIe link according to the eye pattern of the PCIe link at the initial temperature and the eye patterns of the PCIe link at a plurality of temperatures; by the mode, the method can test pertinence when a certain link is tested, and can more accurately position a problem position when the link has a problem.
Description
Technical Field
The present invention relates to the field of test technologies, and in particular, to a method, device, medium, and apparatus for testing PCIe link signals at high temperature.
Background
The test for PCIe signals is currently divided into Tx and Rx parts. The test rate for PCIe _ Tx signals ranges from GEN1, GEN2 < -3.5dB, GEN2 < -6dB up to GEN3, GEN 4. Waveforms at different rates are analyzed by an Intel Sigtest tool, and an eye diagram is drawn to judge the signal quality. The Rx end mainly tests GEN3 and GEN4 parts, and the signal quality of the Rx end can be judged by matching an Intel tool with XDP to perform margin test. However, both tests are based on a normal temperature environment, and a high-temperature test method for the PCIe link is not available for a while.
At present, signal integrity tests aiming at PCIe links are performed in a normal temperature environment, although the signal quality can be verified to a certain extent, the signal quality under a severer high-temperature environment cannot be verified, a server often needs to operate under a long-time high-strength condition, PCIe signals are very important high-speed signals, and therefore the signal link quality can be preferably tested under a severer environment.
Disclosure of Invention
The invention mainly solves the technical problem of providing a method, equipment, medium and device for testing PCIe link signals at high temperature, which can preset different temperatures, carry out infrared high temperature and local heating, test pertinently when testing a certain link, and more accurately position the problem position when the link has problems, and an active noise reduction module in the device can eliminate huge noise generated by the test and provide better working environment for people.
In order to solve the technical problems, the invention adopts a technical scheme that: a method for high-temperature testing of PCIe link signals is provided, comprising:
detecting the temperature of the mainboard to be tested, and testing an eye pattern of a PCIe link in the mainboard to be tested at the initial temperature;
setting a heating range A and a temperature threshold value;
gradually heating the mainboard to be measured within the heating range A, and stopping heating and alarming when the temperature of the mainboard to be measured exceeds a temperature threshold;
in the step-by-step temperature rise process, when the temperature B is raised each time, the test equipment is loaded through the heat insulation device, the eye pattern of the PCIe link in the mainboard to be tested is tested, and the eye patterns of the PCIe link at a plurality of temperatures are obtained;
and calculating the temperature range of the PCIe link according to the eye pattern of the PCIe link at the initial temperature and the eye patterns of the PCIe link at a plurality of temperatures.
Further, the mainboard to be tested is locally heated or wholly heated in the step-by-step heating process.
Further, the eye diagram of the PCIe link includes an eye width and an eye height;
the eye height corresponds to amplitude information of PCIe link signals;
the eye width corresponds to jitter information of PCIe link signals.
The calculating the temperature range of the PCIe link comprises the following steps:
recording the eye pattern of the PCIe link at the initial temperature and the eye patterns of the PCIe links at a plurality of temperatures into a calculation analysis tool;
importing a computational analysis template into a computational analysis tool;
the calculation analysis tool separates out the eye height and the eye width in the eye pattern of the PCIe link;
when one item of the eye width and the eye height in the eye pattern of the PCIe link exceeds the range of the eye height and the eye width in the calculation analysis template, the corresponding temperature of the eye pattern of the PCIe link is the vertex of the temperature range of the PCIe link.
An apparatus for hot testing a PCIe link signal, comprising:
a memory for storing a computer program;
a processor for implementing the steps of a method of high temperature testing of PCIe link signals as described in any one of the above when executing said computer program.
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a method of hot testing PCIe link signals as recited in any one of the above.
An apparatus for hot testing PCIe link signals, comprising: the device comprises a temperature monitoring module, a temperature control module, a heating module, a testing module, a storage module and an analysis module;
the temperature control module sets a heating range, a temperature threshold value and a heating temperature;
the heating module heats the mainboard to be measured step by step according to the heating temperature;
the temperature monitoring module monitors the temperature of each part of the mainboard to be measured, and controls the heating module to stop heating and give an alarm when detecting that the temperature of the mainboard to be measured exceeds the temperature threshold set by the temperature control module;
the test module is provided with a heat insulation device; the test module tests an eye pattern of the PCIe link in an initial state when the heating module does not perform heating and eye patterns of the PCIe link at a plurality of temperatures in the gradual heating process of the heating module;
the storage module stores an eye pattern of the PCIe link in an initial state and eye patterns of the PCIe link under a plurality of temperatures;
the analysis module analyzes the eye pattern of the PCIe link in the storage module through an analysis tool and calculates the temperature range of the PCIe link.
Furthermore, a plurality of heating points and heating coordinates corresponding to the heating points are arranged on the heating module; the heating module carries out local heating through the heating coordinate.
Further, the heating module heats through infrared.
And the active noise reduction module is used for receiving and identifying the noise generated in the test, sending a reverse sound source equal to the noise and offsetting the noise generated in the test.
The invention has the beneficial effects that: according to the invention, through testing the PCIe signal in a high-temperature environment, the stability and the signal integrity of the server can be more accurately verified, the PCIe signal quality at different temperatures can be found, whether a link meets requirements or not can be judged according to the use requirement, the cost can be greatly reduced through local temperature control, and the problem can be more accurately positioned.
Drawings
FIG. 1 is a flowchart of a preferred embodiment of a method for hot testing PCIe link signals in accordance with the present invention;
FIG. 2 is a schematic diagram of an apparatus for high-temperature testing of PCIe link signals according to the present invention;
FIG. 3 is a schematic circuit diagram of an active noise reduction module in an apparatus for testing PCIe link signals at a high temperature according to the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
The embodiment of the invention comprises the following steps:
referring to fig. 1, a method for high-temperature testing of PCIe link signals includes:
the temperature monitoring module detects the temperature of the mainboard to be tested, and eye diagrams of PCIe links at the initial temperature in the mainboard to be tested are respectively tested through the TX sending end testing module and the RX receiving end testing module; information such as amplitude, jitter and the like of the signal can be reflected through the height and width of the eye pattern, and the margin of the signal can be judged through the size of the eye in a specified spec range;
setting a heating range A and a temperature threshold value for the temperature control module, heating through the infrared heating module, heating B each time, loading the transmitting terminal test module and the receiving terminal test module through the heat insulation device for testing, and obtaining eye diagrams for testing PCIe links at different temperatures; when the temperature monitoring module detects that the temperature of the mainboard to be measured exceeds a temperature threshold value, the temperature monitoring module controls the infrared heating module to stop heating and give an alarm;
the heat insulation device is provided with the sending end test module and the receiving end test module, so that the situation that test equipment HOST and XDP cannot work in a high-temperature environment can be effectively avoided, and the HOST and XDP can be effectively used for testing an eye pattern of a PCIe link in the high-temperature environment;
the infrared heating module can be internally provided with a heating coordinate and heating points corresponding to the heating coordinate, local heating can be carried out according to the heating coordinate, integral heating can be carried out by heating all the heating points, and the coordinate position can be tested independently while the integral temperature of the mainboard to be tested is tested;
and recording the eye pattern of the PCIe link at the initial temperature and the eye patterns at different temperatures into a calculation analysis tool, and importing the calculation analysis template into the calculation analysis tool.
The eye pattern is a graph to completely represent bit information of a serial signal, so that the eye pattern becomes the most important tool for measuring signal quality, and the eye pattern measurement is sometimes called as a signal quality test. In addition, the result of the eye measurement is either a pass or a fail, which is determined according to what is usually relative to the template.
Because the eye diagram test is most concerned about the relationship between the eye height and the eye width; wherein the total jitter of the eye width response signal, i.e. the length of the horizontal axis of the eye diagram; the eye width is the size of the vertical axis of the eye pattern.
Reading detailed eye width and eye height information of the eye pattern at different temperatures by using an analysis tool Sigtest tool, and reading the eye width and eye height information in the Sigtest tool by using a processor;
judging the quality and the allowance of the PCIe signal through the test regulation given by the PCIe association;
for example, the eye height for PCIe _ Gen4 rate is specified to be 19 to 1200mv, and the eye width should be greater than 21.75 ps;
when the height and width of the eye do not exceed the specified range, the larger the eye is, the more ideal the eye is in the eye diagram; therefore, the eye height and the eye width tested in different eye diagrams are set as x1 and x2, the eye height and the eye width specified by the eye diagram in the calculation analysis template are y1 and y2, the quality of the eye diagram at the corresponding temperature is judged through (x-y)/y, the quality of the eye diagram is better when the value of (x-y)/y is closer to 0, the maximum temperature which can be borne by the PCIe link is judged when a certain temperature is reached and either the eye height or the eye width exceeds a specified range, and the temperature range is calculated through the maximum temperature.
A is 20 to 70 ℃ and B is 10 ℃.
The embodiment of the invention provides a device for testing PCIe link signals at high temperature,
the test apparatus includes: a memory for storing a computer program; a processor for implementing the steps of a method of high temperature testing of PCIe link signals as disclosed in the foregoing when executing a computer program.
Correspondingly, the invention also discloses a computer readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the method for testing PCIe link signals at high temperature as disclosed in the foregoing.
The computer-readable storage medium provided by the embodiment of the invention has the beneficial effects of the method for testing the PCIe link signal at high temperature disclosed in the foregoing.
Referring to fig. 2, an embodiment of the present specification further provides an apparatus for testing PCIe link signals at high temperature, including: the device comprises a temperature monitoring module, a temperature control module, a heating module, a testing module, a storage module and an analysis module;
the temperature control module sets a heating range, a temperature threshold value and a heating temperature;
the heating module heats the mainboard to be measured step by step according to the heating temperature; the heating module is provided with a plurality of heating points and heating coordinates corresponding to the heating points; the heating module carries out local heating through the heating coordinate; the heating module heats through infrared;
the temperature monitoring module monitors the temperature of each part of the mainboard to be measured, and controls the heating module to stop heating and give an alarm when detecting that the temperature of the mainboard to be measured exceeds the temperature threshold set by the temperature control module;
the test module is provided with a heat insulation device; the test module tests an eye pattern of the PCIe link in an initial state when the heating module does not perform heating and eye patterns of the PCIe link at different temperatures in the gradual heating process of the heating module;
the storage module stores an eye pattern of the PCIe link in an initial state and eye patterns of the PCIe link under a plurality of temperatures;
the analysis module analyzes the PCIe signal eye diagram in the storage module through an analysis tool, calculates the maximum temperature born by the PCIe link and judges the temperature range born by the link.
The active noise reduction receives and identifies noise, and emits a reverse sound source equal to the noise to offset the noise generated during testing.
Referring to fig. 3, the audio frequency to be detected of the active noise reduction module circuit is loosely coupled with the LC series resonance circuit through the mutual inductance M, and the variable capacitance C is changed to enable the circuit to generate series resonance, so that the current of the circuit reaches the maximum. At this time, the current enters a post circuit, the capacitor C1 plays a role in filtering, the R1 is a current limiting resistor, and the LED1 is lighted, so that the device can normally work. The current flows through the LED2 and then passes through the triode, the branch circuit plays a circuit protection role, if the current is too large, the circuit is broken, the LED2 is extinguished, the current is too large, and the buzzer sends out sound sources with corresponding different frequencies according to the current so as to offset the noise.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A method of pyrometry testing PCIe link signals, comprising:
detecting the temperature of the mainboard to be tested, and testing an eye pattern of a PCIe link in the mainboard to be tested at the initial temperature;
setting a heating range A and a temperature threshold value;
gradually heating the mainboard to be measured within the heating range A, and stopping heating and alarming when the temperature of the mainboard to be measured exceeds a temperature threshold;
in the step-by-step temperature rise process, when the temperature B is raised each time, the test equipment is loaded through the heat insulation device, the eye pattern of the PCIe link in the mainboard to be tested is tested, and the eye patterns of the PCIe link at a plurality of temperatures are obtained;
and calculating the temperature range of the PCIe link according to the eye pattern of the PCIe link at the initial temperature and the eye patterns of the PCIe link at a plurality of temperatures.
2. The method of claim 1, wherein the method comprises: and carrying out local heating or integral heating on the mainboard to be tested in the step-by-step heating process.
3. The method of claim 1, wherein the method comprises: the eye diagram of the PCIe link comprises an eye width and an eye height;
the eye height corresponds to amplitude information of PCIe link signals;
the eye width corresponds to jitter information of PCIe link signals.
4. The method of claim 3, wherein the method comprises: the calculating the temperature range of the PCIe link comprises the following steps:
recording the eye pattern of the PCIe link at the initial temperature and the eye patterns of the PCIe links at a plurality of temperatures into a calculation analysis tool;
importing a computational analysis template into a computational analysis tool;
the calculation analysis tool separates out the eye height and the eye width in the eye pattern of the PCIe link;
when one item of the eye width and the eye height in the eye pattern of the PCIe link exceeds the range of the eye height and the eye width in the calculation analysis template, the corresponding temperature of the eye pattern of the PCIe link is the temperature range vertex of the PCIe link.
5. An apparatus for hot testing a PCIe link signal, comprising:
a memory for storing a computer program;
a processor for implementing the steps of a method of hot testing PCIe link signals as claimed in any one of claims 1 to 4 when executing said computer program.
6. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of a method of pyrometric testing of PCIe link signals as recited in any one of claims 1 to 4.
7. An apparatus for hot testing PCIe link signals, comprising: the device comprises a temperature monitoring module, a temperature control module, a heating module, a testing module, a storage module and an analysis module;
the temperature control module sets a heating range, a temperature threshold value and a heating temperature;
the heating module heats the mainboard to be measured step by step according to the heating temperature;
the temperature monitoring module monitors the temperature of each part of the mainboard to be measured, and controls the heating module to stop heating and give an alarm when detecting that the temperature of the mainboard to be measured exceeds the temperature threshold set by the temperature control module;
the test module is provided with a heat insulation device; the testing module tests an eye pattern of a PCIe link in an initial state and eye patterns of the PCIe link at a plurality of temperatures in the gradual heating process of the heating module;
the storage module stores an eye pattern of the PCIe link in an initial state and eye patterns of the PCIe link under a plurality of temperatures;
the analysis module analyzes the eye pattern of the PCIe link in the storage module through an analysis tool and calculates the temperature range of the PCIe link.
8. The apparatus of claim 7, wherein the means for pyrometallying PCIe link signals is: the heating module is provided with a plurality of heating points and heating coordinates corresponding to the heating points; the heating module carries out local heating through the heating coordinate.
9. The apparatus of claim 8, wherein the means for pyrometallying PCIe link signals is: the heating module heats through infrared.
10. The apparatus of claim 7, wherein the means for pyrometallying PCIe link signals is: the device also comprises an active noise reduction module, wherein the active noise reduction module receives and identifies noise generated during testing, and sends a reverse sound source equal to the noise to offset the noise generated during testing.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011353081.5A CN112527576A (en) | 2020-11-27 | 2020-11-27 | Method, equipment, medium and device for testing PCIe link signal at high temperature |
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| CN202011353081.5A CN112527576A (en) | 2020-11-27 | 2020-11-27 | Method, equipment, medium and device for testing PCIe link signal at high temperature |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023184936A1 (en) * | 2022-04-01 | 2023-10-05 | 普源精电科技股份有限公司 | Abnormal waveform capturing method and apparatus, electronic device and storage medium |
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2020
- 2020-11-27 CN CN202011353081.5A patent/CN112527576A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023184936A1 (en) * | 2022-04-01 | 2023-10-05 | 普源精电科技股份有限公司 | Abnormal waveform capturing method and apparatus, electronic device and storage medium |
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