CN115658982A - DRAM aging test data analysis system - Google Patents
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Abstract
The invention discloses a DRAM aging test data analysis system, and relates to the technical field of DRAM aging tests; to facilitate the reason why the quick lock may fail; the system comprises a historical test database, a test data input module, a yield data judgment module, a Bin Map concentration analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model input module, an analysis report and an early warning module. According to the invention, through establishing a corresponding relation between the yield and the correlation of the machine, whether abnormal points such as low yield, failure concentration, bin Gap and continuous fail appear in the test process is automatically compared in the production process, so that abnormal data can be found in time, and the timeliness of data analysis is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to a DRAM aging test data analysis system.
Background
In the prior art, when a DRAM is subjected to an aging test, except for a failure of a chip itself, some small problems occur in hardware due to high stress test, which is very likely to cause a large influence on a test result, in a test process, a fool-proof is usually set through personal experience to avoid problem expansion due to the reason caused by the hardware, but a large amount of experimental verification and data collection are often required when analyzing a root cause of an abnormal occurrence, and a large number of false tests have occurred when a problem is found, and it is desired that whether the failure of the test has the centrality of equipment can be found as soon as possible, and meanwhile, through analyzing a test Log, the test failure centrality of particles is fed back to a client, so that the reason of possible failure is quickly locked, thereby being beneficial to quickly solving the problem and improving the yield of the chip;
when hardware has problems, the frequency of the problems is not very high, the influence on the yield is not very large, but when the problems are found to be abnormal, a period of time is needed, a large amount of data needs to be traced, and the feedback is not timely;
when processing the analysis data, because the data bulk is great, under the condition of not putting in order, need consume than long time to put in order, and need the analyst to know more to the experience of ageing tests worker-station, can carry out effectual judgement to the data, this process inefficiency, and require very high to personnel's training to be unfavorable for analyzing the test data, provide a DRAM ageing tests data analysis system based on this.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a DRAM aging test data analysis system.
In order to achieve the purpose, the invention adopts the following technical scheme:
a DRAM aging test data analysis system comprises a historical test database, a test data input module, a yield data judgment module, a Bin Map centralized analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model input module, an analysis report and an early warning module.
Preferably: the yield data judging module is used for judging data of the test data input module, comparing historical production yields of programs of the same type based on yield clamping control set by a system grabbing system, judging the standards of the yields, judging the yield to be Normal when no abnormality occurs, summarizing Abnormal conditions when the judging process finds the abnormality, marking Lot on the basis of Normal, absormal and New Program, and if the Lot is in a non-Normal state, marking the output corresponding to the production as an Absormal state to perform hardware analysis and Program analysis.
Preferably: the Bin Map concentration analysis module analyzes according to two aspects after the yield data judgment module analyzes and finds that the yield is abnormal;
(1) Entering a Bin Map centralized analysis module, and the system captures a test result and generates a corresponding Bin Map according to the Dut of the BIB;
(2) Whether concentrated Fail exists on Bin distribution or not is analyzed, whether continuous Fail and the condition of the concentrated Fail exist are observed, abnormal Oven and Slot are marked under the Abnormal condition, the BIB is an Abnormal skin, then a summary result is output, and the result enters a Slot correlation analysis module.
Preferred for the present invention are: the Slot correlation analysis module analyzes the Bin Map concentration problem, the Slot correlation analysis module compares whether the yield of each Slot is abnormal after finding no Bin Map concentration problem, marks the Slot, the BIB is abnormal, the Slot correlation module can capture historical test information of the abnormal Slot, compares the yield of the abnormal Slot with the yield of other slots of the same Oven according to the test information, judges whether the abnormal Slot belongs to the abnormality of the Slot, outputs a judgment result, and cancels the Slot abnormal mark if the abnormal Slot belongs to the abnormality, and enters the BIB correlation analysis module.
As a preferable aspect of the present invention: the BIB correlation analysis module receives the BIB with input abnormality and analyzes in two aspects,
(1) Capturing historical test information of the abnormal BIB, and comparing the abnormal BIB with the yield of other BIBs same as the Oven according to the test information;
(2) Capturing historical Fail Bin distribution of BIB, then overlapping Fail Bin, and checking whether fixed Dut continuous Fail exists;
and the BIB analysis module outputs a judgment result according to the two aspects, and cancels the BIB abrormal mark and enters the Oven correlation analysis module after the two aspects are not abnormal.
As a preferable aspect of the present invention: when the Oven is marked as an Absormal state, the Oven correlation analysis module searches historical test data of the Oven, meanwhile, compared with the yield of other same programs, the system grabs a temperature curve in the test process, calculates whether the temperature rising and falling time is within an allowable range, and if the temperature rising and falling time and the temperature falling time are within an acceptable range, the Absormal mark of the Oven is cancelled and outputs the summary of a hardware part to the failure model analysis module.
And further: if the yield analysis is not marked as Normal, the program Bin Gap analysis module carries out program analysis, automatically compares Fail Bin gaps of the same test, analyzes the yield abnormal problem caused by the specific Fail Bin number, analyzes the Fail item of Fail Bin according to the corresponding Bin Gap analysis result and the test log, finds out the main failure reason, analyzes whether Fail of a certain Bin is concentrated on a certain board or not, and outputs Bin Fail report to the failure model analysis module.
As a further scheme of the invention: the failure item analysis module analyzes the failed test item according to the test data, captures Top3 of the failure item Fail in the Fail Bin, calculates whether Fail of TOP3 concentrates on a certain board to exceed 30%, and outputs an analysis result to the failure model analysis module.
As a still further scheme of the invention: the failure model analysis module is maintained through a database, the failure model analysis module can enter through a root cause related to personal maintenance after the reason is investigated according to the occurring analysis results, analysis reference is provided in the subsequent analysis according to the condition that whether similar analysis exists in the history or not is provided for the analysis results of failure item analysis and neutral analysis, an analysis report is finally output, and an engineer is required to provide the root cause for maintenance after the final reason is investigated.
The invention has the beneficial effects that:
1. by establishing corresponding relation between the yield and the correlation of the machine, whether abnormal points such as low yield, failure concentration, bin Gap and continuous fail appear in the test process is automatically compared in the production process, so that abnormal data can be found in time.
2. Meanwhile, the correlation and the concentration of different hardware of the comparison machine can be generated, so that the reason of possible failure can be rapidly judged, and the timeliness of data analysis can be improved.
3. After the hardware problem is eliminated, the test data can be analyzed, so that a client can be timely confirmed whether the memory chip has a problem in the preorder step.
Drawings
FIG. 1 is a schematic diagram of a yield analysis structure of a DRAM burn-in data analysis system according to the present invention;
FIG. 2 is a schematic diagram of a yield data determination module of a DRAM aging test data analysis system according to the present invention;
FIG. 3 is a schematic diagram of a Bin Map centralized analysis structure of a DRAM aging test data analysis system according to the present invention;
FIG. 4 is a schematic diagram of a Slot correlation analysis structure of a DRAM aging test data analysis system according to the present invention;
FIG. 5 is a schematic structural diagram of a BIB correlation analysis module of a DRAM aging test data analysis system according to the present invention;
FIG. 6 is a schematic structural diagram of an Oven correlation analysis module of a DRAM aging test data analysis system according to the present invention;
FIG. 7 is a schematic diagram of a program Bin Gap analysis structure of a DRAM aging test data analysis system according to the present invention;
FIG. 8 is a schematic diagram of a failure item analysis structure of a DRAM burn-in test data analysis system according to the present invention;
FIG. 9 is a schematic diagram of a failure model analysis structure of a DRAM burn-in data analysis system according to the present invention.
Detailed Description
The technical solution of the present patent will be described in further detail with reference to the following embodiments.
Reference will now be made in detail to embodiments of the present patent, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present patent and are not to be construed as limiting the present patent.
In the description of this patent, it is noted that unless otherwise specifically stated or limited, the terms "mounted," "connected," and "disposed" are to be construed broadly and can include, for example, fixedly connected, disposed, detachably connected, disposed, or integrally connected and disposed. The specific meaning of the above terms in this patent may be understood by those of ordinary skill in the art as appropriate.
Example 1:
a DRAM aging test data analysis system is shown in figure 1 and comprises a historical test database, a test data input module, a yield data judgment module, a Bin Map centralized analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model input module, an analysis report and an early warning module.
Example 2:
a DRAM aging test data analysis system is characterized in that after one Lot is batched, a test data input module utilizes a yield data judgment module to judge data, a logic block diagram is shown in FIG. 2, the yield is controlled based on a yield card set by a system capture system, historical production yields of programs of the same type are compared, the standard of the yield is judged, when no abnormality occurs, the yield is judged to be Normal, the judgment process is Abnormal, the Abnormal condition is summarized, lot is marked based on Normal, abnormal and New Program, if the Lot is not in the Normal state, an Oven correspondingly produced is marked to be in an Abnormal state, and hardware analysis and Program analysis are carried out;
preferably, when the test procedure is a first run, an analysis report may be generated by the system, confirming and stopping problem propagation in the event of an anomaly.
Preferably, after the yield data judgment module analyzes and finds that the yield is abnormal, the yield data judgment module analyzes according to two aspects;
(1) Entering a Bin Map concentration analysis module, and the system can capture a test result and generate a corresponding Bin Map according to the Dut of the BIB;
(2) Analyzing whether concentrated Fail exists on Bin distribution, observing whether continuous Fail and concentrated Fail exist, marking Abnormal Oven and Slot under Abnormal conditions, wherein BIB is Abnormal, outputting a summary result, and entering a Slot correlation analysis module.
Preferably, a system block diagram of the Slot correlation analysis module is shown in fig. 4; the Slot correlation analysis module analyzes the Bin Map concentration problem, the Slot correlation analysis module compares whether the yield of each Slot is abnormal after the Bin Map concentration problem is not found, marks the Slot, the BIB is abnormal, the Slot correlation module can capture historical test information of the abnormal Slot, compares the yield of the abnormal Slot with the yield of other slots of the same Oven according to the test information, judges whether the abnormal Slot belongs to the abnormality of the Slot, outputs a judgment result, and cancels the Slot abnormal mark if the judgment result is normal, and enters the BIB correlation analysis module.
Preferably, the BIB correlation analysis module system block diagram is shown in fig. 5, in the former analysis module, the abnormal BIB is input to the BIB correlation analysis module, the BIB correlation analysis module performs analysis in two aspects,
(1) Capturing historical test information of the abnormal BIB, and comparing the abnormal BIB with the yield of other BIBs same as the Oven according to the test information;
(2) Capturing historical Fail Bin distribution of the BIB, then overlapping Fail Bin, and checking whether fixed Dut continuous Fail exists;
and the BIB analysis module outputs a judgment result according to the two aspects, and after the two aspects are not abnormal, the BIB abrormal identification is cancelled and the results enter the Oven correlation analysis module.
Preferably, as shown in fig. 6, when Oven is marked as an Abnormal state, historical test data of Oven is retrieved, and compared with yields of other identical programs, the system captures a temperature curve during the test process, calculates whether the time for raising and lowering the temperature is within an allowable range, and if both are within an acceptable range, the Abnormal mark of Oven is cancelled and summarized to the failure model analysis module.
Preferably, the failure model analysis module is maintained through a database, a system block diagram is shown in fig. 9, for an occurring analysis result, the failure model analysis module enters through a root cause related to personal maintenance after a reason is investigated, in a subsequent analysis, for a case that whether history has similar analysis is provided for analysis results of failure item analysis and neutral analysis, an analysis reference is provided, an analysis report is finally output, and an engineer is required to provide the root cause for maintenance after a final reason is investigated.
Example 3:
a DRAM aging test data analysis system is used for analyzing a program if the program is not identified as Normal in yield analysis, firstly, the Normal enters a program Bin Gap analysis module, a system block diagram is shown in FIG. 7, the Bin Gap analysis module automatically compares Fail Bin gaps of the same test, analyzes yield abnormity caused by excessive number of specific Fail Bin, analyzes failure item of Fail Bin according to a corresponding Bin Gap analysis result and a test log to find a main failure reason, analyzes whether Fail of a certain Bin is concentrated on a certain board or not, and outputs Bin Fail to be reported to the failure item analysis module.
Preferably, the failed item analysis module, as shown in fig. 8, analyzes the failed test item according to the test data, captures Top3 of failed item Fail in Fail Bin, calculates whether Fail of Top3 is concentrated on a certain board by more than 30%, and outputs the analysis result to the failure model analysis module.
The above description is for the purpose of illustrating the preferred embodiments of the present invention and is not intended to be exhaustive or to limit the invention to the precise embodiments disclosed, and all modifications, equivalents, and improvements that may occur to those skilled in the art and that fall within the spirit and scope of the invention are intended to be embraced therein.
Claims (9)
1. A DRAM aging test data analysis system comprises a historical test database, a test data input module, a yield data judgment module, a Bin Map centralized analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model input module, an analysis report and an early warning module.
2. The system as claimed in claim 1, wherein the yield data determining module performs data determination on the test data input module, determines the yield standard based on yield control set by the system capture system and historical production yield comparison of the same type of Program, determines that the yield is Normal when no abnormality occurs, determines that the yield is Normal when an abnormality occurs, summarizes Abnormal conditions in the determining process, marks Lot as Normal, abrormal, and New Program, and if Lot is not Normal, marks Oven corresponding to production as abrormal state, and performs hardware analysis and Program analysis.
3. The system as claimed in claim 2, wherein the Bin Map centralized analysis module analyzes the yield data according to two aspects after the yield data judgment module analyzes the yield data to find out the yield abnormality;
(1) Entering a Bin Map centralized analysis module, and the system captures a test result and generates a corresponding Bin Map according to the Dut of the BIB;
(2) Analyzing whether concentrated Fail exists on Bin distribution, observing whether continuous Fail and concentrated Fail exist, marking Abnormal Oven and Slot under Abnormal conditions, wherein BIB is Abnormal, outputting a summary result, and entering a Slot correlation analysis module.
4. The system for analyzing data of the DRAM aging test as recited in claim 3, wherein the Slot correlation analysis module analyzes the Bin Map concentration problem, the Slot correlation analysis module compares whether the yield of each Slot is abnormal after the Bin Map concentration problem is not found, marks the Slot, the BIB is abnormal, the Slot correlation module captures historical test information of the abnormal Slot, judges whether the abnormal Slot belongs to the abnormality of the Slot according to the comparison of the yield of the abnormal Slot and the yields of other slots of the same Oven by the test information, outputs a judgment result, cancels the Slot normal mark if the judgment result is normal, and enters the BIB correlation analysis module.
5. The DRAM burn-in data analysis system as claimed in claim 4, wherein said BIB correlation analysis module receives BIB of input exception, the BIB correlation analysis module analyzes in two aspects,
(1) Capturing historical test information of the abnormal BIB, and comparing the abnormal BIB with the yield of other BIBs same as the Oven according to the test information;
(2) Capturing historical Fail Bin distribution of BIB, then overlapping Fail Bin, and checking whether fixed Dut continuous Fail exists;
and the BIB analysis module outputs a judgment result according to the two aspects, and cancels the BIB abrormal mark and enters the Oven correlation analysis module after the two aspects are not abnormal.
6. The system of claim 5, wherein the Oven correlation analysis module retrieves historical test data of Oven when Oven is marked as an Absnormal state, and compares the yields of other same programs, the system captures the temperature curve during the test process, calculates whether the temperature rise and fall time is within an allowable range, and if both are within an acceptable range, the Absnormal mark of Oven is cancelled and summarized to the failure model analysis module.
7. The DRAM burn-in data analysis system of claim 6, wherein said program Bin Gap analysis module performs program analysis in yield analysis if not identified as Normal, automatically compares Fail Bin gaps of the same test, analyzes yield anomaly problem caused by specific Fail Bin number, analyzes Fail item of Fail Bin according to corresponding Bin Gap analysis result and test log, finds main failure cause, analyzes whether Fail item of a Bin is concentrated on a board or not, and outputs Bin Fail report to the failure model analysis module.
8. The system of claim 7, wherein the failure item analysis module analyzes the failed item according to the test data, captures Top3 of failed item Fail in the Fail Bin, calculates whether Fail of TOP3 is concentrated on a board more than 30%, and outputs the analysis result to the failure model analysis module.
9. The system of claim 8, wherein the failure model analysis module is maintained through a database, and enters a related root cause for personal maintenance after investigation of a cause according to an analysis result, and provides an analysis reference for a case that whether similar analysis exists in history according to analysis results of failure item analysis and neutral analysis in subsequent analysis, and finally outputs an analysis report, and an engineer is required to provide the root cause for maintenance after investigation of a final cause.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117711473A (en) * | 2024-02-06 | 2024-03-15 | 南京扬贺扬微电子科技有限公司 | Self-checking data management system and method based on memory device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117711473A (en) * | 2024-02-06 | 2024-03-15 | 南京扬贺扬微电子科技有限公司 | Self-checking data management system and method based on memory device |
| CN117711473B (en) * | 2024-02-06 | 2024-05-14 | 南京扬贺扬微电子科技有限公司 | Self-checking data management system and method based on memory device |
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